arpci.c revision 1.1
1 /* $NetBSD: arpci.c,v 1.1 2011/07/07 05:06:44 matt Exp $ */ 2 /*- 3 * Copyright (c) 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Matt Thomas of 3am Software Foundry. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 33 __KERNEL_RCSID(0, "$NetBSD: arpci.c,v 1.1 2011/07/07 05:06:44 matt Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 39 #include <dev/pci/pcivar.h> 40 41 #include <mips/atheros/include/arbusvar.h> 42 #include <mips/atheros/include/ar9344reg.h> 43 44 #define PCI_CMD_CFG_READ 0xa 45 #define PCI_CMD_CFG_WRITE 0xb 46 47 struct arpci_softc { 48 device_t sc_dev; 49 bus_dma_tag_t sc_dmat; 50 bus_space_tag_t sc_bst; 51 bus_space_handle_t sc_bsh; 52 struct mips_bus_space sc_memt; 53 struct mips_pci_chipset sc_pc; 54 u_int sc_pba_flags; 55 }; 56 57 static void arpci_bus_mem_init(bus_space_tag_t, void *); 58 59 static void 60 arpci_attach_hook(device_t parent, device_t self, 61 struct pcibus_attach_args *pba) 62 { 63 } 64 65 static int 66 arpci_bus_maxdevs(void *v, int busno) 67 { 68 //struct arpci_softc * const sc = v; 69 70 if (busno == 0) 71 return 22; 72 73 return 32; 74 } 75 76 static pcitag_t 77 arpci_make_tag(void *v, int bus, int dev, int func) 78 { 79 if (bus == 0 && dev == 0) { 80 /* 81 * Local access 82 */ 83 return (func << 8); 84 } 85 86 if (bus == 0 && dev < 21) { 87 /* 88 * Type 0 can only access 21 (32 - 11) devices starting at * device 0 (0 is needed for inbound transactions). 89 * AD[11:32] encodes the idsel for the transaction 90 * (only one bit can be set). 91 * AD[8:11] contains function 92 * AD[2:7] contains the register offset. 93 * AD[0:1] must be zero. 94 */ 95 return (1 << (dev + 11)) | (func << 8); 96 } 97 98 /* 99 * Type 1 Confugration Transaction. 100 */ 101 return (bus << 16) | (dev << 11) | (func << 8) | 1; 102 } 103 104 static void 105 arpci_decompose_tag(void *v, pcitag_t tag, int *busp, int *devp, int *funcp) 106 { 107 if (tag & 1) { 108 if (busp) 109 *busp = (tag >> 16) & 255; 110 if (devp) 111 *devp = (tag >> 11) & 31; 112 } else { 113 if (busp) 114 *busp = 0; 115 if (devp) { 116 if (tag & ~0x7ff) { 117 *devp = ffs(tag >> 11) - 1; 118 } else { 119 *devp = 0; 120 } 121 } 122 } 123 if (funcp) 124 *funcp = (tag >> 8) & 7; 125 } 126 127 static pcireg_t 128 arpci_conf_read(void *v, pcitag_t tag, int reg) 129 { 130 struct arpci_softc * const sc = v; 131 pcireg_t rv = 0xffffffff; 132 133 if ((tag & 0x00ff0001) == 1) { 134 KASSERT(((tag >> 11) & 31) > 20); 135 /* 136 * This was a type 0 transaction for a device > 20 which 137 * we can't support. 138 */ 139 return rv; 140 } 141 142 tag |= reg & -4; 143 144 #if 0 145 bus_space_read_4(sc->sc_bst, sc->sc_bsh, AR7100_PCI_ERROR); 146 bus_space_write_4(sc->sc_bst, sc->sc_bsh, AR7100_PCI_ERROR, 147 bus_space_read_4(sc->sc_bst, sc->sc_bsh, AR7100_PCI_ERROR) & 3); 148 #endif 149 150 bus_space_handle_t addr = sc->sc_bsh; 151 if ((tag & ~0x7fe) == 0) { 152 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 153 AR7100_PCI_LCL_CFG_CMD, AR7100_PCI_LCL_CFG_CMD_READ | tag); 154 addr += AR7100_PCI_LCL_CFG_RDATA; 155 printf("%s: tag %#lx ", __func__, tag); 156 } else { 157 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 158 AR7100_PCI_CFG_ADDR, tag); 159 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 160 AR7100_PCI_CFG_CMD, PCI_CMD_CFG_READ); 161 addr += AR7100_PCI_CFG_RDATA; 162 printf("%s: AD[0:31] 0x%08lx: ", __func__, tag); 163 } 164 165 rv = kfetch_32((void *)addr, 0xffffffff); 166 printf("%#x\n", rv); 167 168 return rv; 169 } 170 171 static void 172 arpci_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data) 173 { 174 struct arpci_softc * const sc = v; 175 176 if ((tag & 0x00ff0001) == 1) { 177 KASSERT(((tag >> 11) & 31) > 20); 178 /* 179 * This was a type 0 transaction for a device > 20 which 180 * we can't support. 181 */ 182 return; 183 } 184 185 tag |= reg & -4; 186 187 if ((tag & ~0x7fe) == 0) { 188 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 189 AR7100_PCI_LCL_CFG_CMD, AR7100_PCI_LCL_CFG_CMD_WRITE | tag); 190 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 191 AR7100_PCI_LCL_CFG_WDATA, data); 192 } else { 193 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 194 AR7100_PCI_CFG_ADDR, tag); 195 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 196 AR7100_PCI_CFG_CMD, PCI_CMD_CFG_WRITE); 197 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 198 AR7100_PCI_CFG_WDATA, data); 199 } 200 } 201 202 static int 203 arpci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 204 { 205 return EINVAL; 206 } 207 208 static const char * 209 arpci_intr_string(void *v, pci_intr_handle_t ih) 210 { 211 return NULL; 212 } 213 214 static const struct evcnt * 215 arpci_intr_evcnt(void *v, pci_intr_handle_t ih) 216 { 217 return NULL; 218 } 219 220 static void * 221 arpci_intr_establish(void *v, pci_intr_handle_t ih, 222 int ipl, int (*func)(void *), void *arg) 223 { 224 return NULL; 225 } 226 227 static void 228 arpci_intr_disestablish(void *v, void *cookie) 229 { 230 } 231 232 static void 233 arpci_conf_interrupt(void *v, int bus, int dev, int func, int swiz, int *ilinep) 234 { 235 } 236 237 static void 238 arpci_chipset_init(struct arpci_softc *sc) 239 { 240 pci_chipset_tag_t pc = &sc->sc_pc; 241 242 pc->pc_conf_v = sc; 243 pc->pc_attach_hook = arpci_attach_hook; 244 pc->pc_bus_maxdevs = arpci_bus_maxdevs; 245 pc->pc_make_tag = arpci_make_tag; 246 pc->pc_decompose_tag = arpci_decompose_tag; 247 pc->pc_conf_read = arpci_conf_read; 248 pc->pc_conf_write = arpci_conf_write; 249 250 pc->pc_intr_v = sc; 251 pc->pc_intr_map = arpci_intr_map; 252 pc->pc_intr_string = arpci_intr_string; 253 pc->pc_intr_evcnt = arpci_intr_evcnt; 254 pc->pc_intr_establish = arpci_intr_establish; 255 pc->pc_intr_disestablish = arpci_intr_disestablish; 256 257 pc->pc_conf_interrupt = arpci_conf_interrupt; 258 259 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 260 //pc->pc_pciide_compat_intr_establish = arpci_pciide_compat_intr_establish; 261 #endif 262 } 263 264 static int 265 arpci_match(device_t parent, cfdata_t cf, void *aux) 266 { 267 struct arbus_attach_args * const aa = aux; 268 bus_space_handle_t bsh; 269 270 if (strcmp(aa->aa_name, cf->cf_name) != 0) 271 return 0; 272 273 if (bus_space_map(aa->aa_bst, aa->aa_addr, aa->aa_size, 0, &bsh)) 274 return 0; 275 276 bus_space_unmap(aa->aa_bst, bsh, aa->aa_size); 277 278 return 1; 279 } 280 281 static void 282 arpci_attach(device_t parent, device_t self, void *aux) 283 { 284 struct arbus_attach_args * const aa = aux; 285 struct arpci_softc * const sc = device_private(self); 286 287 sc->sc_dev = self; 288 sc->sc_bst = aa->aa_bst; 289 sc->sc_dmat = aa->aa_dmat; 290 291 if (bus_space_map(aa->aa_bst, aa->aa_addr, aa->aa_size, 0, 292 &sc->sc_bsh)) { 293 aprint_error(": failed to map registers\n"); 294 return; 295 } 296 297 aprint_normal("\n"); 298 arpci_bus_mem_init(&sc->sc_memt, sc); 299 arpci_chipset_init(sc); 300 301 sc->sc_pba_flags |= PCI_FLAGS_MEM_OKAY; 302 303 struct pcibus_attach_args pba; 304 memset(&pba, 0, sizeof(pba)); 305 306 pba.pba_flags = sc->sc_pba_flags; 307 if (pba.pba_flags & PCI_FLAGS_MEM_OKAY) 308 pba.pba_memt = &sc->sc_memt; 309 pba.pba_dmat = aa->aa_dmat; 310 pba.pba_pc = &sc->sc_pc; 311 pba.pba_bus = 0; 312 313 config_found_ia(self, "pcibus", &pba, pcibusprint); 314 } 315 316 CFATTACH_DECL_NEW(arpci, sizeof(struct arpci_softc), 317 arpci_match, arpci_attach, NULL, NULL); 318 319 #define CHIP arpci 320 #define CHIP_LITTLE_ENDIAN /* defined */ 321 #define CHIP_MEM /* defined */ 322 #define CHIP_EXTENT /* defined */ 323 #define CHIP_EX_MALLOC_SAFE(v) true 324 #define CHIP_W1_BUS_START(v) 0x10000000UL 325 #define CHIP_W1_BUS_END(v) 0x16ffffffUL 326 #define CHIP_W1_SYS_START(v) CHIP_W1_BUS_START(v) 327 #define CHIP_W1_SYS_END(v) CHIP_W1_BUS_END(v) 328 329 #include <mips/mips/bus_space_alignstride_chipdep.c> 330
Indexes created Wed Sep 24 05:09:52 GMT 2025