octeon_smi.c revision 1.1 1 1.1 hikaru /* $NetBSD: octeon_smi.c,v 1.1 2015/04/29 08:32:01 hikaru Exp $ */
2 1.1 hikaru
3 1.1 hikaru /*
4 1.1 hikaru * Copyright (c) 2007 Internet Initiative Japan, Inc.
5 1.1 hikaru * All rights reserved.
6 1.1 hikaru *
7 1.1 hikaru * Redistribution and use in source and binary forms, with or without
8 1.1 hikaru * modification, are permitted provided that the following conditions
9 1.1 hikaru * are met:
10 1.1 hikaru * 1. Redistributions of source code must retain the above copyright
11 1.1 hikaru * notice, this list of conditions and the following disclaimer.
12 1.1 hikaru * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 hikaru * notice, this list of conditions and the following disclaimer in the
14 1.1 hikaru * documentation and/or other materials provided with the distribution.
15 1.1 hikaru *
16 1.1 hikaru * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
17 1.1 hikaru * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 1.1 hikaru * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 1.1 hikaru * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
20 1.1 hikaru * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 1.1 hikaru * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 1.1 hikaru * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 1.1 hikaru * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 1.1 hikaru * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 1.1 hikaru * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 1.1 hikaru * SUCH DAMAGE.
27 1.1 hikaru */
28 1.1 hikaru
29 1.1 hikaru #include <sys/cdefs.h>
30 1.1 hikaru __KERNEL_RCSID(0, "$NetBSD: octeon_smi.c,v 1.1 2015/04/29 08:32:01 hikaru Exp $");
31 1.1 hikaru
32 1.1 hikaru #include <sys/param.h>
33 1.1 hikaru #include <sys/systm.h>
34 1.1 hikaru #include <sys/malloc.h>
35 1.1 hikaru #include <sys/mbuf.h>
36 1.1 hikaru #include <mips/locore.h>
37 1.1 hikaru #include <mips/cavium/octeonvar.h>
38 1.1 hikaru #include <mips/cavium/dev/octeon_fpavar.h>
39 1.1 hikaru #include <mips/cavium/dev/octeon_pipreg.h>
40 1.1 hikaru #include <mips/cavium/dev/octeon_smireg.h>
41 1.1 hikaru #include <mips/cavium/dev/octeon_smivar.h>
42 1.1 hikaru
43 1.1 hikaru static void octeon_smi_enable(struct octeon_smi_softc *);
44 1.1 hikaru
45 1.1 hikaru /* XXX */
46 1.1 hikaru void
47 1.1 hikaru octeon_smi_init(struct octeon_smi_attach_args *aa,
48 1.1 hikaru struct octeon_smi_softc **rsc)
49 1.1 hikaru {
50 1.1 hikaru struct octeon_smi_softc *sc;
51 1.1 hikaru int status;
52 1.1 hikaru
53 1.1 hikaru sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
54 1.1 hikaru if (sc == NULL)
55 1.1 hikaru panic("can't allocate memory: %s", __func__);
56 1.1 hikaru
57 1.1 hikaru sc->sc_port = aa->aa_port;
58 1.1 hikaru sc->sc_regt = aa->aa_regt;
59 1.1 hikaru
60 1.1 hikaru status = bus_space_map(sc->sc_regt, SMI_BASE, SMI_SIZE, 0,
61 1.1 hikaru &sc->sc_regh);
62 1.1 hikaru if (status != 0)
63 1.1 hikaru panic("can't map %s space", "smi register");
64 1.1 hikaru
65 1.1 hikaru octeon_smi_enable(sc);
66 1.1 hikaru
67 1.1 hikaru *rsc = sc;
68 1.1 hikaru }
69 1.1 hikaru
70 1.1 hikaru #define _SMI_RD8(sc, off) \
71 1.1 hikaru bus_space_read_8((sc)->sc_regt, (sc)->sc_regh, (off))
72 1.1 hikaru #define _SMI_WR8(sc, off, v) \
73 1.1 hikaru bus_space_write_8((sc)->sc_regt, (sc)->sc_regh, (off), (v))
74 1.1 hikaru
75 1.1 hikaru int
76 1.1 hikaru octeon_smi_read(struct octeon_smi_softc *sc, int phy_addr, int reg)
77 1.1 hikaru {
78 1.1 hikaru uint64_t smi_rd;
79 1.1 hikaru int timo;
80 1.1 hikaru
81 1.1 hikaru _SMI_WR8(sc, SMI_CMD_OFFSET, SMI_CMD_PHY_OP |
82 1.1 hikaru (phy_addr << SMI_CMD_PHY_ADR_SHIFT) |
83 1.1 hikaru (reg << SMI_CMD_REG_ADR_SHIFT));
84 1.1 hikaru
85 1.1 hikaru timo = 10000;
86 1.1 hikaru smi_rd = _SMI_RD8(sc, SMI_RD_DAT_OFFSET);
87 1.1 hikaru while (ISSET(smi_rd, SMI_RD_DAT_PENDING)) {
88 1.1 hikaru if (timo-- == 0)
89 1.1 hikaru break;
90 1.1 hikaru delay(10);
91 1.1 hikaru smi_rd = _SMI_RD8(sc, SMI_RD_DAT_OFFSET);
92 1.1 hikaru }
93 1.1 hikaru if (ISSET(smi_rd, SMI_RD_DAT_PENDING)) {
94 1.1 hikaru return -1;
95 1.1 hikaru }
96 1.1 hikaru
97 1.1 hikaru return ISSET(smi_rd, SMI_RD_DAT_VAL) ? (smi_rd & SMI_RD_DAT_DAT) : 0;
98 1.1 hikaru }
99 1.1 hikaru
100 1.1 hikaru void
101 1.1 hikaru octeon_smi_write(struct octeon_smi_softc *sc, int phy_addr, int reg, int value)
102 1.1 hikaru {
103 1.1 hikaru uint64_t smi_wr;
104 1.1 hikaru int timo;
105 1.1 hikaru
106 1.1 hikaru smi_wr = 0;
107 1.1 hikaru SET(smi_wr, value);
108 1.1 hikaru _SMI_WR8(sc, SMI_WR_DAT_OFFSET, smi_wr);
109 1.1 hikaru
110 1.1 hikaru _SMI_WR8(sc, SMI_CMD_OFFSET, (phy_addr << SMI_CMD_PHY_ADR_SHIFT) |
111 1.1 hikaru (reg << SMI_CMD_REG_ADR_SHIFT));
112 1.1 hikaru
113 1.1 hikaru timo = 10000;
114 1.1 hikaru smi_wr = _SMI_RD8(sc, SMI_WR_DAT_OFFSET);
115 1.1 hikaru while (ISSET(smi_wr, SMI_WR_DAT_PENDING)) {
116 1.1 hikaru if (timo-- == 0)
117 1.1 hikaru break;
118 1.1 hikaru delay(10);
119 1.1 hikaru smi_wr = _SMI_RD8(sc, SMI_WR_DAT_OFFSET);
120 1.1 hikaru }
121 1.1 hikaru if (ISSET(smi_wr, SMI_WR_DAT_PENDING)) {
122 1.1 hikaru /* XXX log */
123 1.1 hikaru printf("ERROR: cnmac_mii_writereg(0x%x, 0x%x, 0x%x) timed out.\n",
124 1.1 hikaru phy_addr, reg, value);
125 1.1 hikaru }
126 1.1 hikaru }
127 1.1 hikaru
128 1.1 hikaru static void
129 1.1 hikaru octeon_smi_enable(struct octeon_smi_softc *sc)
130 1.1 hikaru {
131 1.1 hikaru _SMI_WR8(sc, SMI_EN_OFFSET, SMI_EN_EN);
132 1.1 hikaru }
133 1.1 hikaru
134 1.1 hikaru void
135 1.1 hikaru octeon_smi_set_clock(struct octeon_smi_softc *sc, uint64_t clock)
136 1.1 hikaru {
137 1.1 hikaru _SMI_WR8(sc, SMI_CLK_OFFSET, clock);
138 1.1 hikaru }
139 1.1 hikaru
140