octeon_smi.c revision 1.4 1 1.4 simonb /* $NetBSD: octeon_smi.c,v 1.4 2020/06/18 13:52:08 simonb Exp $ */
2 1.1 hikaru
3 1.1 hikaru /*
4 1.1 hikaru * Copyright (c) 2007 Internet Initiative Japan, Inc.
5 1.1 hikaru * All rights reserved.
6 1.1 hikaru *
7 1.1 hikaru * Redistribution and use in source and binary forms, with or without
8 1.1 hikaru * modification, are permitted provided that the following conditions
9 1.1 hikaru * are met:
10 1.1 hikaru * 1. Redistributions of source code must retain the above copyright
11 1.1 hikaru * notice, this list of conditions and the following disclaimer.
12 1.1 hikaru * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 hikaru * notice, this list of conditions and the following disclaimer in the
14 1.1 hikaru * documentation and/or other materials provided with the distribution.
15 1.1 hikaru *
16 1.1 hikaru * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
17 1.1 hikaru * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 1.1 hikaru * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 1.1 hikaru * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
20 1.1 hikaru * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 1.1 hikaru * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 1.1 hikaru * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 1.1 hikaru * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 1.1 hikaru * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 1.1 hikaru * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 1.1 hikaru * SUCH DAMAGE.
27 1.1 hikaru */
28 1.1 hikaru
29 1.1 hikaru #include <sys/cdefs.h>
30 1.4 simonb __KERNEL_RCSID(0, "$NetBSD: octeon_smi.c,v 1.4 2020/06/18 13:52:08 simonb Exp $");
31 1.1 hikaru
32 1.1 hikaru #include <sys/param.h>
33 1.1 hikaru #include <sys/systm.h>
34 1.1 hikaru #include <sys/malloc.h>
35 1.1 hikaru #include <sys/mbuf.h>
36 1.1 hikaru #include <mips/locore.h>
37 1.1 hikaru #include <mips/cavium/octeonvar.h>
38 1.4 simonb #include <mips/cavium/dev/octeon_fpareg.h>
39 1.1 hikaru #include <mips/cavium/dev/octeon_fpavar.h>
40 1.1 hikaru #include <mips/cavium/dev/octeon_pipreg.h>
41 1.1 hikaru #include <mips/cavium/dev/octeon_smireg.h>
42 1.1 hikaru #include <mips/cavium/dev/octeon_smivar.h>
43 1.1 hikaru
44 1.3 simonb static void octsmi_enable(struct octsmi_softc *);
45 1.1 hikaru
46 1.1 hikaru /* XXX */
47 1.1 hikaru void
48 1.3 simonb octsmi_init(struct octsmi_attach_args *aa, struct octsmi_softc **rsc)
49 1.1 hikaru {
50 1.3 simonb struct octsmi_softc *sc;
51 1.1 hikaru int status;
52 1.1 hikaru
53 1.1 hikaru sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
54 1.1 hikaru if (sc == NULL)
55 1.1 hikaru panic("can't allocate memory: %s", __func__);
56 1.1 hikaru
57 1.1 hikaru sc->sc_port = aa->aa_port;
58 1.1 hikaru sc->sc_regt = aa->aa_regt;
59 1.1 hikaru
60 1.1 hikaru status = bus_space_map(sc->sc_regt, SMI_BASE, SMI_SIZE, 0,
61 1.1 hikaru &sc->sc_regh);
62 1.1 hikaru if (status != 0)
63 1.1 hikaru panic("can't map %s space", "smi register");
64 1.1 hikaru
65 1.3 simonb octsmi_enable(sc);
66 1.1 hikaru
67 1.1 hikaru *rsc = sc;
68 1.1 hikaru }
69 1.1 hikaru
70 1.1 hikaru #define _SMI_RD8(sc, off) \
71 1.1 hikaru bus_space_read_8((sc)->sc_regt, (sc)->sc_regh, (off))
72 1.1 hikaru #define _SMI_WR8(sc, off, v) \
73 1.1 hikaru bus_space_write_8((sc)->sc_regt, (sc)->sc_regh, (off), (v))
74 1.1 hikaru
75 1.1 hikaru int
76 1.3 simonb octsmi_read(struct octsmi_softc *sc, int phy_addr, int reg, uint16_t *val)
77 1.1 hikaru {
78 1.1 hikaru uint64_t smi_rd;
79 1.1 hikaru int timo;
80 1.1 hikaru
81 1.4 simonb _SMI_WR8(sc, SMI_CMD_OFFSET,
82 1.4 simonb __SHIFTIN(SMI_CMD_PHY_OP_READ, SMI_CMD_PHY_OP) |
83 1.4 simonb __SHIFTIN(phy_addr, SMI_CMD_PHY_ADR) |
84 1.4 simonb __SHIFTIN(reg, SMI_CMD_REG_ADR));
85 1.1 hikaru
86 1.1 hikaru timo = 10000;
87 1.1 hikaru smi_rd = _SMI_RD8(sc, SMI_RD_DAT_OFFSET);
88 1.1 hikaru while (ISSET(smi_rd, SMI_RD_DAT_PENDING)) {
89 1.1 hikaru if (timo-- == 0)
90 1.2 msaitoh return ETIMEDOUT;
91 1.1 hikaru delay(10);
92 1.1 hikaru smi_rd = _SMI_RD8(sc, SMI_RD_DAT_OFFSET);
93 1.1 hikaru }
94 1.2 msaitoh
95 1.2 msaitoh if (ISSET(smi_rd, SMI_RD_DAT_VAL)) {
96 1.2 msaitoh *val = (smi_rd & SMI_RD_DAT_DAT);
97 1.2 msaitoh return 0;
98 1.1 hikaru }
99 1.1 hikaru
100 1.2 msaitoh return -1;
101 1.1 hikaru }
102 1.1 hikaru
103 1.2 msaitoh int
104 1.3 simonb octsmi_write(struct octsmi_softc *sc, int phy_addr, int reg, uint16_t value)
105 1.1 hikaru {
106 1.1 hikaru uint64_t smi_wr;
107 1.1 hikaru int timo;
108 1.1 hikaru
109 1.1 hikaru smi_wr = 0;
110 1.1 hikaru SET(smi_wr, value);
111 1.1 hikaru _SMI_WR8(sc, SMI_WR_DAT_OFFSET, smi_wr);
112 1.1 hikaru
113 1.4 simonb _SMI_WR8(sc, SMI_CMD_OFFSET,
114 1.4 simonb __SHIFTIN(SMI_CMD_PHY_OP_WRITE, SMI_CMD_PHY_OP) |
115 1.4 simonb __SHIFTIN(phy_addr, SMI_CMD_PHY_ADR) |
116 1.4 simonb __SHIFTIN(reg, SMI_CMD_REG_ADR));
117 1.1 hikaru
118 1.1 hikaru timo = 10000;
119 1.1 hikaru smi_wr = _SMI_RD8(sc, SMI_WR_DAT_OFFSET);
120 1.1 hikaru while (ISSET(smi_wr, SMI_WR_DAT_PENDING)) {
121 1.2 msaitoh if (timo-- == 0) {
122 1.2 msaitoh /* XXX log */
123 1.2 msaitoh printf("ERROR: cnmac_mii_writereg(0x%x, 0x%x, 0x%hx) "
124 1.2 msaitoh "timed out.\n", phy_addr, reg, value);
125 1.2 msaitoh return ETIMEDOUT;
126 1.2 msaitoh }
127 1.1 hikaru delay(10);
128 1.1 hikaru smi_wr = _SMI_RD8(sc, SMI_WR_DAT_OFFSET);
129 1.1 hikaru }
130 1.2 msaitoh
131 1.2 msaitoh return 0;
132 1.1 hikaru }
133 1.1 hikaru
134 1.1 hikaru static void
135 1.3 simonb octsmi_enable(struct octsmi_softc *sc)
136 1.1 hikaru {
137 1.1 hikaru _SMI_WR8(sc, SMI_EN_OFFSET, SMI_EN_EN);
138 1.1 hikaru }
139 1.1 hikaru
140 1.1 hikaru void
141 1.3 simonb octsmi_set_clock(struct octsmi_softc *sc, uint64_t clock)
142 1.1 hikaru {
143 1.1 hikaru _SMI_WR8(sc, SMI_CLK_OFFSET, clock);
144 1.1 hikaru }
145 1.1 hikaru
146