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octeon_smi.c revision 1.9
      1  1.9     skrll /*	$NetBSD: octeon_smi.c,v 1.9 2022/09/29 07:00:46 skrll Exp $	*/
      2  1.1    hikaru 
      3  1.1    hikaru /*
      4  1.1    hikaru  * Copyright (c) 2007 Internet Initiative Japan, Inc.
      5  1.1    hikaru  * All rights reserved.
      6  1.1    hikaru  *
      7  1.1    hikaru  * Redistribution and use in source and binary forms, with or without
      8  1.1    hikaru  * modification, are permitted provided that the following conditions
      9  1.1    hikaru  * are met:
     10  1.1    hikaru  * 1. Redistributions of source code must retain the above copyright
     11  1.1    hikaru  *    notice, this list of conditions and the following disclaimer.
     12  1.1    hikaru  * 2. Redistributions in binary form must reproduce the above copyright
     13  1.1    hikaru  *    notice, this list of conditions and the following disclaimer in the
     14  1.1    hikaru  *    documentation and/or other materials provided with the distribution.
     15  1.1    hikaru  *
     16  1.1    hikaru  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     17  1.1    hikaru  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     18  1.1    hikaru  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     19  1.1    hikaru  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     20  1.1    hikaru  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     21  1.1    hikaru  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     22  1.1    hikaru  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     23  1.1    hikaru  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     24  1.1    hikaru  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  1.1    hikaru  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  1.1    hikaru  * SUCH DAMAGE.
     27  1.1    hikaru  */
     28  1.1    hikaru 
     29  1.1    hikaru #include <sys/cdefs.h>
     30  1.9     skrll __KERNEL_RCSID(0, "$NetBSD: octeon_smi.c,v 1.9 2022/09/29 07:00:46 skrll Exp $");
     31  1.1    hikaru 
     32  1.1    hikaru #include <sys/param.h>
     33  1.1    hikaru #include <sys/systm.h>
     34  1.5    simonb #include <sys/bus.h>
     35  1.5    simonb #include <sys/device.h>
     36  1.1    hikaru #include <sys/mbuf.h>
     37  1.6  jmcneill #include <sys/queue.h>
     38  1.6  jmcneill #include <sys/kmem.h>
     39  1.5    simonb 
     40  1.1    hikaru #include <mips/locore.h>
     41  1.1    hikaru #include <mips/cavium/octeonvar.h>
     42  1.4    simonb #include <mips/cavium/dev/octeon_fpareg.h>
     43  1.1    hikaru #include <mips/cavium/dev/octeon_fpavar.h>
     44  1.1    hikaru #include <mips/cavium/dev/octeon_pipreg.h>
     45  1.1    hikaru #include <mips/cavium/dev/octeon_smireg.h>
     46  1.1    hikaru #include <mips/cavium/dev/octeon_smivar.h>
     47  1.5    simonb #include <mips/cavium/include/iobusvar.h>
     48  1.1    hikaru 
     49  1.6  jmcneill #include <dev/fdt/fdtvar.h>
     50  1.6  jmcneill 
     51  1.5    simonb /*
     52  1.5    simonb  * System Management Interface
     53  1.5    simonb  *
     54  1.5    simonb  *
     55  1.5    simonb  * CN30XX  - 1 SMI interface
     56  1.5    simonb  * CN31XX  - 1 SMI interface
     57  1.5    simonb  * CN38XX  - 1 SMI interface
     58  1.5    simonb  * CN50XX  - 1 SMI interface
     59  1.5    simonb  * CN52XX  - 2 SMI interfaces
     60  1.5    simonb  * CN56XX  - 2 SMI interfaces
     61  1.5    simonb  * CN58XX  - 1 SMI interface
     62  1.5    simonb  * CN61XX  - 2 SMI interfaces
     63  1.5    simonb  * CN63XX  - 2 SMI interfaces
     64  1.5    simonb  * CN66XX  - 2 SMI interfaces
     65  1.5    simonb  * CN68XX  - 4 SMI interfaces
     66  1.5    simonb  * CN70XX  - 2 SMI interfaces
     67  1.5    simonb  * CN73XX  - 2 SMI interfaces
     68  1.5    simonb  * CN78XX  - 4 SMI interfaces
     69  1.5    simonb  * CNF71XX - 2 SMI interfaces
     70  1.5    simonb  * CNF75XX - 2 SMI interfaces
     71  1.5    simonb  */
     72  1.5    simonb 
     73  1.6  jmcneill static int	octsmi_iobus_match(device_t, struct cfdata *, void *);
     74  1.6  jmcneill static void	octsmi_iobus_attach(device_t, device_t, void *);
     75  1.6  jmcneill 
     76  1.6  jmcneill static int	octsmi_fdt_match(device_t, struct cfdata *, void *);
     77  1.6  jmcneill static void	octsmi_fdt_attach(device_t, device_t, void *);
     78  1.6  jmcneill 
     79  1.6  jmcneill static void	octsmi_attach_common(struct octsmi_softc *, int);
     80  1.5    simonb 
     81  1.6  jmcneill struct octsmi_instance {
     82  1.6  jmcneill 	struct octsmi_softc *	sc;
     83  1.6  jmcneill 	int			phandle;
     84  1.6  jmcneill 	TAILQ_ENTRY(octsmi_instance) next;
     85  1.6  jmcneill };
     86  1.6  jmcneill 
     87  1.6  jmcneill static TAILQ_HEAD(, octsmi_instance) octsmi_instances =
     88  1.6  jmcneill     TAILQ_HEAD_INITIALIZER(octsmi_instances);
     89  1.5    simonb 
     90  1.5    simonb #define	_SMI_RD8(sc, off) \
     91  1.5    simonb 	bus_space_read_8((sc)->sc_regt, (sc)->sc_regh, (off))
     92  1.5    simonb #define	_SMI_WR8(sc, off, v) \
     93  1.5    simonb 	bus_space_write_8((sc)->sc_regt, (sc)->sc_regh, (off), (v))
     94  1.5    simonb 
     95  1.6  jmcneill CFATTACH_DECL_NEW(octsmi_iobus, sizeof(struct octsmi_softc),
     96  1.6  jmcneill     octsmi_iobus_match, octsmi_iobus_attach, NULL, NULL);
     97  1.6  jmcneill 
     98  1.6  jmcneill CFATTACH_DECL_NEW(octsmi_fdt, sizeof(struct octsmi_softc),
     99  1.6  jmcneill     octsmi_fdt_match, octsmi_fdt_attach, NULL, NULL);
    100  1.6  jmcneill 
    101  1.7   thorpej static const struct device_compatible_entry compat_data[] = {
    102  1.7   thorpej 	{ .compat = "cavium,octeon-3860-mdio" },
    103  1.7   thorpej 	DEVICE_COMPAT_EOL
    104  1.6  jmcneill };
    105  1.5    simonb 
    106  1.5    simonb static int
    107  1.6  jmcneill octsmi_iobus_match(device_t parent, struct cfdata *cf, void *aux)
    108  1.5    simonb {
    109  1.5    simonb 	struct iobus_attach_args *aa = aux;
    110  1.5    simonb 
    111  1.5    simonb 	if (strcmp(cf->cf_name, aa->aa_name) != 0)
    112  1.5    simonb 		return 0;
    113  1.5    simonb 	if (aa->aa_unitno < SMI_NUNITS)
    114  1.5    simonb 		return 1;
    115  1.5    simonb 	else
    116  1.5    simonb 		return 0;
    117  1.5    simonb }
    118  1.1    hikaru 
    119  1.5    simonb static void
    120  1.6  jmcneill octsmi_iobus_attach(device_t parent, device_t self, void *aux)
    121  1.1    hikaru {
    122  1.5    simonb 	struct octsmi_softc *sc = device_private(self);
    123  1.5    simonb 	struct iobus_attach_args *aa = aux;
    124  1.1    hikaru 	int status;
    125  1.1    hikaru 
    126  1.5    simonb 	sc->sc_dev = self;
    127  1.5    simonb 	sc->sc_regt = aa->aa_bust;
    128  1.1    hikaru 
    129  1.5    simonb 	aprint_normal("\n");
    130  1.1    hikaru 
    131  1.5    simonb 	status = bus_space_map(sc->sc_regt, aa->aa_unit->addr, SMI_SIZE, 0,
    132  1.1    hikaru 	    &sc->sc_regh);
    133  1.5    simonb 	if (status != 0) {
    134  1.5    simonb 		aprint_error_dev(self, "could not map registers\n");
    135  1.5    simonb 		return;
    136  1.5    simonb 	}
    137  1.1    hikaru 
    138  1.6  jmcneill 	octsmi_attach_common(sc, 0);
    139  1.6  jmcneill }
    140  1.6  jmcneill 
    141  1.6  jmcneill static int
    142  1.6  jmcneill octsmi_fdt_match(device_t parent, struct cfdata *cf, void *aux)
    143  1.6  jmcneill {
    144  1.6  jmcneill 	struct fdt_attach_args * const faa = aux;
    145  1.6  jmcneill 
    146  1.7   thorpej 	return of_compatible_match(faa->faa_phandle, compat_data);
    147  1.6  jmcneill }
    148  1.6  jmcneill 
    149  1.6  jmcneill static void
    150  1.6  jmcneill octsmi_fdt_attach(device_t parent, device_t self, void *aux)
    151  1.6  jmcneill {
    152  1.6  jmcneill 	struct octsmi_softc *sc = device_private(self);
    153  1.6  jmcneill 	struct fdt_attach_args * const faa = aux;
    154  1.6  jmcneill 	const int phandle = faa->faa_phandle;
    155  1.6  jmcneill 	bus_addr_t addr;
    156  1.6  jmcneill 	bus_size_t size;
    157  1.6  jmcneill 
    158  1.6  jmcneill 	if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
    159  1.6  jmcneill 		aprint_error(": couldn't get registers\n");
    160  1.6  jmcneill 		return;
    161  1.6  jmcneill 	}
    162  1.6  jmcneill 
    163  1.6  jmcneill 	sc->sc_dev = self;
    164  1.6  jmcneill 	sc->sc_regt = faa->faa_bst;
    165  1.6  jmcneill 
    166  1.6  jmcneill 	if (bus_space_map(sc->sc_regt, addr, size, 0, &sc->sc_regh) != 0) {
    167  1.6  jmcneill 		aprint_error(": couldn't map registers\n");
    168  1.6  jmcneill 		return;
    169  1.6  jmcneill 	}
    170  1.6  jmcneill 
    171  1.6  jmcneill 	aprint_normal("\n");
    172  1.6  jmcneill 
    173  1.6  jmcneill 	octsmi_attach_common(sc, phandle);
    174  1.6  jmcneill }
    175  1.6  jmcneill 
    176  1.6  jmcneill static void
    177  1.6  jmcneill octsmi_attach_common(struct octsmi_softc *sc, int phandle)
    178  1.6  jmcneill {
    179  1.6  jmcneill 	struct octsmi_instance *oi;
    180  1.6  jmcneill 
    181  1.6  jmcneill 	oi = kmem_alloc(sizeof(*oi), KM_SLEEP);
    182  1.6  jmcneill 	oi->sc = sc;
    183  1.6  jmcneill 	oi->phandle = phandle;
    184  1.6  jmcneill 	TAILQ_INSERT_TAIL(&octsmi_instances, oi, next);
    185  1.1    hikaru 
    186  1.5    simonb 	const uint64_t magic_value =
    187  1.5    simonb 	    SMI_CLK_PREAMBLE |
    188  1.5    simonb 	    __SHIFTIN(0x4, SMI_CLK_SAMPLE) |		/* XXX magic 0x4 */
    189  1.5    simonb 	    __SHIFTIN(0x64, SMI_CLK_PHASE);		/* XXX magic 0x64 */
    190  1.5    simonb 	_SMI_WR8(sc, SMI_CLK_OFFSET, magic_value);
    191  1.5    simonb 	_SMI_WR8(sc, SMI_EN_OFFSET, SMI_EN_EN);
    192  1.1    hikaru }
    193  1.1    hikaru 
    194  1.1    hikaru int
    195  1.3    simonb octsmi_read(struct octsmi_softc *sc, int phy_addr, int reg, uint16_t *val)
    196  1.1    hikaru {
    197  1.1    hikaru 	uint64_t smi_rd;
    198  1.1    hikaru 	int timo;
    199  1.1    hikaru 
    200  1.8     skrll 	_SMI_WR8(sc, SMI_CMD_OFFSET,
    201  1.4    simonb 	    __SHIFTIN(SMI_CMD_PHY_OP_READ, SMI_CMD_PHY_OP) |
    202  1.4    simonb 	    __SHIFTIN(phy_addr, SMI_CMD_PHY_ADR) |
    203  1.4    simonb 	    __SHIFTIN(reg, SMI_CMD_REG_ADR));
    204  1.1    hikaru 
    205  1.1    hikaru 	timo = 10000;
    206  1.1    hikaru 	smi_rd = _SMI_RD8(sc, SMI_RD_DAT_OFFSET);
    207  1.1    hikaru 	while (ISSET(smi_rd, SMI_RD_DAT_PENDING)) {
    208  1.1    hikaru 		if (timo-- == 0)
    209  1.2   msaitoh 			return ETIMEDOUT;
    210  1.1    hikaru 		delay(10);
    211  1.1    hikaru 		smi_rd = _SMI_RD8(sc, SMI_RD_DAT_OFFSET);
    212  1.1    hikaru 	}
    213  1.2   msaitoh 
    214  1.2   msaitoh 	if (ISSET(smi_rd, SMI_RD_DAT_VAL)) {
    215  1.2   msaitoh 		*val = (smi_rd & SMI_RD_DAT_DAT);
    216  1.2   msaitoh 		return 0;
    217  1.1    hikaru 	}
    218  1.1    hikaru 
    219  1.2   msaitoh 	return -1;
    220  1.1    hikaru }
    221  1.1    hikaru 
    222  1.2   msaitoh int
    223  1.3    simonb octsmi_write(struct octsmi_softc *sc, int phy_addr, int reg, uint16_t value)
    224  1.1    hikaru {
    225  1.1    hikaru 	uint64_t smi_wr;
    226  1.1    hikaru 	int timo;
    227  1.1    hikaru 
    228  1.1    hikaru 	smi_wr = 0;
    229  1.1    hikaru 	SET(smi_wr, value);
    230  1.1    hikaru 	_SMI_WR8(sc, SMI_WR_DAT_OFFSET, smi_wr);
    231  1.1    hikaru 
    232  1.4    simonb 	_SMI_WR8(sc, SMI_CMD_OFFSET,
    233  1.4    simonb 	    __SHIFTIN(SMI_CMD_PHY_OP_WRITE, SMI_CMD_PHY_OP) |
    234  1.4    simonb 	    __SHIFTIN(phy_addr, SMI_CMD_PHY_ADR) |
    235  1.4    simonb 	    __SHIFTIN(reg, SMI_CMD_REG_ADR));
    236  1.1    hikaru 
    237  1.1    hikaru 	timo = 10000;
    238  1.1    hikaru 	smi_wr = _SMI_RD8(sc, SMI_WR_DAT_OFFSET);
    239  1.1    hikaru 	while (ISSET(smi_wr, SMI_WR_DAT_PENDING)) {
    240  1.2   msaitoh 		if (timo-- == 0) {
    241  1.2   msaitoh 			return ETIMEDOUT;
    242  1.2   msaitoh 		}
    243  1.1    hikaru 		delay(10);
    244  1.1    hikaru 		smi_wr = _SMI_RD8(sc, SMI_WR_DAT_OFFSET);
    245  1.1    hikaru 	}
    246  1.5    simonb 	if (ISSET(smi_wr, SMI_WR_DAT_PENDING)) {
    247  1.5    simonb 		/* XXX log */
    248  1.5    simonb 		printf("ERROR: octsmi_write(0x%x, 0x%x, 0x%hx) timed out.\n",
    249  1.5    simonb 		    phy_addr, reg, value);
    250  1.5    simonb 	}
    251  1.2   msaitoh 
    252  1.2   msaitoh 	return 0;
    253  1.1    hikaru }
    254  1.1    hikaru 
    255  1.5    simonb struct octsmi_softc *
    256  1.5    simonb octsmi_lookup(int phandle, int port)
    257  1.1    hikaru {
    258  1.6  jmcneill 	struct octsmi_instance *oi;
    259  1.5    simonb 
    260  1.6  jmcneill #if notyet
    261  1.6  jmcneill 	TAILQ_FOREACH(oi, &octsmi_instances, list) {
    262  1.6  jmcneill 		if (oi->phandle == phandle)
    263  1.6  jmcneill 			return oi->sc;
    264  1.6  jmcneill 	}
    265  1.1    hikaru 
    266  1.6  jmcneill 	return NULL;
    267  1.6  jmcneill #else
    268  1.6  jmcneill 	oi = TAILQ_FIRST(&octsmi_instances);
    269  1.6  jmcneill 	return oi == NULL ? NULL : oi->sc;
    270  1.6  jmcneill #endif
    271  1.1    hikaru }
    272