octeon_smireg.h revision 1.1.2.2
1 1.1.2.2 skrll /* $NetBSD: octeon_smireg.h,v 1.1.2.2 2015/06/06 14:40:01 skrll Exp $ */ 2 1.1.2.2 skrll 3 1.1.2.2 skrll /* 4 1.1.2.2 skrll * Copyright (c) 2007 Internet Initiative Japan, Inc. 5 1.1.2.2 skrll * All rights reserved. 6 1.1.2.2 skrll * 7 1.1.2.2 skrll * Redistribution and use in source and binary forms, with or without 8 1.1.2.2 skrll * modification, are permitted provided that the following conditions 9 1.1.2.2 skrll * are met: 10 1.1.2.2 skrll * 1. Redistributions of source code must retain the above copyright 11 1.1.2.2 skrll * notice, this list of conditions and the following disclaimer. 12 1.1.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 13 1.1.2.2 skrll * notice, this list of conditions and the following disclaimer in the 14 1.1.2.2 skrll * documentation and/or other materials provided with the distribution. 15 1.1.2.2 skrll * 16 1.1.2.2 skrll * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 17 1.1.2.2 skrll * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 1.1.2.2 skrll * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 1.1.2.2 skrll * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 20 1.1.2.2 skrll * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 1.1.2.2 skrll * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 1.1.2.2 skrll * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 1.1.2.2 skrll * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 1.1.2.2 skrll * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 1.1.2.2 skrll * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 1.1.2.2 skrll * SUCH DAMAGE. 27 1.1.2.2 skrll */ 28 1.1.2.2 skrll 29 1.1.2.2 skrll /* 30 1.1.2.2 skrll * SMI Registers 31 1.1.2.2 skrll */ 32 1.1.2.2 skrll 33 1.1.2.2 skrll #ifndef _OCTEON_SMIREG_H_ 34 1.1.2.2 skrll #define _OCTEON_SMIREG_H_ 35 1.1.2.2 skrll 36 1.1.2.2 skrll #define SMI_CMD 0x0001180000001800ULL 37 1.1.2.2 skrll #define SMI_WR_DAT 0x0001180000001808ULL 38 1.1.2.2 skrll #define SMI_RD_DAT 0x0001180000001810ULL 39 1.1.2.2 skrll #define SMI_CLK 0x0001180000001818ULL 40 1.1.2.2 skrll #define SMI_EN 0x0001180000001820ULL 41 1.1.2.2 skrll 42 1.1.2.2 skrll #define SMI_CMD_OFFSET 0x00ULL 43 1.1.2.2 skrll #define SMI_WR_DAT_OFFSET 0x08ULL 44 1.1.2.2 skrll #define SMI_RD_DAT_OFFSET 0x10ULL 45 1.1.2.2 skrll #define SMI_CLK_OFFSET 0x18ULL 46 1.1.2.2 skrll #define SMI_EN_OFFSET 0x20ULL 47 1.1.2.2 skrll 48 1.1.2.2 skrll #define SMI_BASE 0x0001180000001800ULL 49 1.1.2.2 skrll #define SMI_SIZE 0x028ULL 50 1.1.2.2 skrll 51 1.1.2.2 skrll /* SMI CMD */ 52 1.1.2.2 skrll #define SMI_CMD_63_17 UINT64_C(0xfffffffffffe0000) 53 1.1.2.2 skrll #define SMI_CMD_PHY_OP UINT64_C(0x0000000000010000) 54 1.1.2.2 skrll #define SMI_CMD_15_13 UINT64_C(0x000000000000e000) 55 1.1.2.2 skrll #define SMI_CMD_PHY_ADR UINT64_C(0x0000000000001f00) 56 1.1.2.2 skrll #define SMI_CMD_PHY_ADR_SHIFT 8 57 1.1.2.2 skrll #define SMI_CMD_7_5 UINT64_C(0x00000000000000e0) 58 1.1.2.2 skrll #define SMI_CMD_REG_ADR UINT64_C(0x000000000000001f) 59 1.1.2.2 skrll #define SMI_CMD_REG_ADR_SHIFT 0 60 1.1.2.2 skrll 61 1.1.2.2 skrll /* SMI_WR_DAT */ 62 1.1.2.2 skrll #define SMI_WR_DAT_63_18 UINT64_C(0xfffffffffffc0000) 63 1.1.2.2 skrll #define SMI_WR_DAT_PENDING UINT64_C(0x0000000000020000) 64 1.1.2.2 skrll #define SMI_WR_DAT_VAL UINT64_C(0x0000000000010000) 65 1.1.2.2 skrll #define SMI_WR_DAT_DAT UINT64_C(0x000000000000ffff) 66 1.1.2.2 skrll 67 1.1.2.2 skrll /* SMI_RD_DAT */ 68 1.1.2.2 skrll #define SMI_RD_DAT_63_18 UINT64_C(0xfffffffffffc0000) 69 1.1.2.2 skrll #define SMI_RD_DAT_PENDING UINT64_C(0x0000000000020000) 70 1.1.2.2 skrll #define SMI_RD_DAT_VAL UINT64_C(0x0000000000010000) 71 1.1.2.2 skrll #define SMI_RD_DAT_DAT UINT64_C(0x000000000000ffff) 72 1.1.2.2 skrll 73 1.1.2.2 skrll /* SMI_CLK */ 74 1.1.2.2 skrll #define SMI_CLK_63_21 UINT64_C(0xffffffffffe00000) 75 1.1.2.2 skrll #define SMI_CLK_SAMPLE_HI UINT64_C(0x00000000001f0000) 76 1.1.2.2 skrll #define SMI_CLK_15_14 UINT64_C(0x000000000000c000) 77 1.1.2.2 skrll #define SMI_CLK_CLK_IDLE UINT64_C(0x0000000000002000) 78 1.1.2.2 skrll #define SMI_CLK_PREAMBLE UINT64_C(0x0000000000001000) 79 1.1.2.2 skrll #define SMI_CLK_SAMPLE UINT64_C(0x0000000000000f00) 80 1.1.2.2 skrll #define SMI_CLK_PHASE UINT64_C(0x00000000000000ff) 81 1.1.2.2 skrll 82 1.1.2.2 skrll /* SMI_EN */ 83 1.1.2.2 skrll #define SMI_EN_63_1 UINT64_C(0xfffffffffffffffe) 84 1.1.2.2 skrll #define SMI_EN_EN UINT64_C(0x0000000000000001) 85 1.1.2.2 skrll 86 1.1.2.2 skrll /* XXX */ 87 1.1.2.2 skrll 88 1.1.2.2 skrll #endif /* _OCTEON_SMIREG_H_ */ 89
Indexes created Tue Oct 21 16:10:11 GMT 2025