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      1 /*	$NetBSD: octeon_smireg.h,v 1.3 2020/06/23 05:18:02 simonb Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 2007 Internet Initiative Japan, Inc.
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  * SUCH DAMAGE.
     27  */
     28 
     29 /*
     30  * SMI Registers
     31  */
     32 
     33 #ifndef _OCTEON_SMIREG_H_
     34 #define _OCTEON_SMIREG_H_
     35 
     36 #define	SMI_CMD_OFFSET			0x00ULL
     37 #define	SMI_WR_DAT_OFFSET		0x08ULL
     38 #define	SMI_RD_DAT_OFFSET		0x10ULL
     39 #define	SMI_CLK_OFFSET			0x18ULL
     40 #define	SMI_EN_OFFSET			0x20ULL
     41 
     42 #define SMI_BASE			0x0001180000001800ULL
     43 #define SMI_SIZE			0x040ULL
     44 /* XXX - support 1 SMI unit for direct attach; some CPUs have 4 SMIs */
     45 #define SMI_NUNITS			1
     46 
     47 /* SMI CMD */
     48 #define SMI_CMD_63_17			UINT64_C(0xfffffffffffe0000)
     49 #define SMI_CMD_PHY_OP			UINT64_C(0x0000000000010000)
     50 #define   SMI_CMD_PHY_OP_READ		  1
     51 #define   SMI_CMD_PHY_OP_WRITE		  0
     52 #define SMI_CMD_15_13			UINT64_C(0x000000000000e000)
     53 #define SMI_CMD_PHY_ADR			UINT64_C(0x0000000000001f00)
     54 #define SMI_CMD_7_5			UINT64_C(0x00000000000000e0)
     55 #define SMI_CMD_REG_ADR			UINT64_C(0x000000000000001f)
     56 
     57 /* SMI_WR_DAT */
     58 #define SMI_WR_DAT_63_18		UINT64_C(0xfffffffffffc0000)
     59 #define SMI_WR_DAT_PENDING		UINT64_C(0x0000000000020000)
     60 #define SMI_WR_DAT_VAL			UINT64_C(0x0000000000010000)
     61 #define SMI_WR_DAT_DAT			UINT64_C(0x000000000000ffff)
     62 
     63 /* SMI_RD_DAT */
     64 #define SMI_RD_DAT_63_18		UINT64_C(0xfffffffffffc0000)
     65 #define SMI_RD_DAT_PENDING		UINT64_C(0x0000000000020000)
     66 #define SMI_RD_DAT_VAL			UINT64_C(0x0000000000010000)
     67 #define SMI_RD_DAT_DAT			UINT64_C(0x000000000000ffff)
     68 
     69 /* SMI_CLK */
     70 #define SMI_CLK_63_21			UINT64_C(0xffffffffffe00000)
     71 #define SMI_CLK_SAMPLE_HI		UINT64_C(0x00000000001f0000)
     72 #define SMI_CLK_15_14			UINT64_C(0x000000000000c000)
     73 #define SMI_CLK_CLK_IDLE		UINT64_C(0x0000000000002000)
     74 #define SMI_CLK_PREAMBLE		UINT64_C(0x0000000000001000)
     75 #define SMI_CLK_SAMPLE			UINT64_C(0x0000000000000f00)
     76 #define SMI_CLK_PHASE			UINT64_C(0x00000000000000ff)
     77 
     78 /* SMI_EN */
     79 #define SMI_EN_63_1			UINT64_C(0xfffffffffffffffe)
     80 #define SMI_EN_EN			UINT64_C(0x0000000000000001)
     81 
     82 /* XXX */
     83 
     84 #endif /* _OCTEON_SMIREG_H_ */
     85