octeonvar.h revision 1.2.2.3
1 1.2.2.3 skrll /* $NetBSD: octeonvar.h,v 1.2.2.3 2015/09/22 12:05:47 skrll Exp $ */ 2 1.2.2.2 skrll 3 1.2.2.2 skrll /*- 4 1.2.2.2 skrll * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 1.2.2.2 skrll * All rights reserved. 6 1.2.2.2 skrll * 7 1.2.2.2 skrll * This code is derived from software contributed to The NetBSD Foundation 8 1.2.2.2 skrll * by Jason R. Thorpe. 9 1.2.2.2 skrll * 10 1.2.2.2 skrll * Redistribution and use in source and binary forms, with or without 11 1.2.2.2 skrll * modification, are permitted provided that the following conditions 12 1.2.2.2 skrll * are met: 13 1.2.2.2 skrll * 1. Redistributions of source code must retain the above copyright 14 1.2.2.2 skrll * notice, this list of conditions and the following disclaimer. 15 1.2.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 16 1.2.2.2 skrll * notice, this list of conditions and the following disclaimer in the 17 1.2.2.2 skrll * documentation and/or other materials provided with the distribution. 18 1.2.2.2 skrll * 19 1.2.2.2 skrll * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 1.2.2.2 skrll * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 1.2.2.2 skrll * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 1.2.2.2 skrll * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 1.2.2.2 skrll * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 1.2.2.2 skrll * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 1.2.2.2 skrll * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 1.2.2.2 skrll * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 1.2.2.2 skrll * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 1.2.2.2 skrll * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 1.2.2.2 skrll * POSSIBILITY OF SUCH DAMAGE. 30 1.2.2.2 skrll */ 31 1.2.2.2 skrll 32 1.2.2.2 skrll #ifndef _MIPS_OCTEON_OCTEONVAR_H_ 33 1.2.2.2 skrll #define _MIPS_OCTEON_OCTEONVAR_H_ 34 1.2.2.2 skrll 35 1.2.2.2 skrll #include <sys/bus.h> 36 1.2.2.2 skrll #include <sys/evcnt.h> 37 1.2.2.3 skrll #include <sys/kcpuset.h> 38 1.2.2.2 skrll #include <mips/locore.h> 39 1.2.2.2 skrll #include <dev/pci/pcivar.h> 40 1.2.2.2 skrll 41 1.2.2.2 skrll /* XXX elsewhere */ 42 1.2.2.2 skrll #define _ASM_PROLOGUE \ 43 1.2.2.2 skrll " .set push \n" \ 44 1.2.2.2 skrll " .set noreorder \n" 45 1.2.2.2 skrll #define _ASM_PROLOGUE_MIPS64 \ 46 1.2.2.2 skrll _ASM_PROLOGUE \ 47 1.2.2.2 skrll " .set mips64 \n" 48 1.2.2.2 skrll #define _ASM_PROLOGUE_OCTEON \ 49 1.2.2.2 skrll _ASM_PROLOGUE \ 50 1.2.2.2 skrll " .set arch=octeon \n" 51 1.2.2.2 skrll #define _ASM_EPILOGUE \ 52 1.2.2.2 skrll " .set pop \n" 53 1.2.2.2 skrll /* 54 1.2.2.2 skrll * subbits = __BITS64_GET(XXX, bits); 55 1.2.2.2 skrll * bits = __BITS64_SET(XXX, subbits); 56 1.2.2.2 skrll */ 57 1.2.2.2 skrll #ifndef __BITS64_GET 58 1.2.2.2 skrll #define __BITS64_GET(name, bits) \ 59 1.2.2.2 skrll (((uint64_t)(bits) & name) >> name##_SHIFT) 60 1.2.2.2 skrll #endif 61 1.2.2.2 skrll #ifndef __BITS64_SET 62 1.2.2.2 skrll #define __BITS64_SET(name, subbits) \ 63 1.2.2.2 skrll (((uint64_t)(subbits) << name##_SHIFT) & name) 64 1.2.2.2 skrll #endif 65 1.2.2.2 skrll 66 1.2.2.2 skrll struct octeon_config { 67 1.2.2.2 skrll struct mips_bus_space mc_iobus_bust; 68 1.2.2.2 skrll struct mips_bus_space mc_bootbus_bust; 69 1.2.2.2 skrll struct mips_pci_chipset mc_pc; 70 1.2.2.2 skrll 71 1.2.2.2 skrll struct mips_bus_dma_tag mc_iobus_dmat; 72 1.2.2.2 skrll struct mips_bus_dma_tag mc_bootbus_dmat; 73 1.2.2.2 skrll struct mips_bus_dma_tag mc_core1_dmat; 74 1.2.2.2 skrll 75 1.2.2.2 skrll struct extent *mc_io_ex; 76 1.2.2.2 skrll struct extent *mc_mem_ex; 77 1.2.2.2 skrll 78 1.2.2.2 skrll int mc_mallocsafe; 79 1.2.2.2 skrll }; 80 1.2.2.2 skrll 81 1.2.2.2 skrll #define NIRQS 64 82 1.2.2.2 skrll 83 1.2.2.2 skrll struct cpu_softc { 84 1.2.2.2 skrll struct cpu_info *cpu_ci; 85 1.2.2.3 skrll 86 1.2.2.2 skrll uint64_t cpu_int0_sum0; 87 1.2.2.2 skrll uint64_t cpu_int1_sum0; 88 1.2.2.2 skrll uint64_t cpu_int2_sum0; 89 1.2.2.2 skrll 90 1.2.2.2 skrll uint64_t cpu_int0_en0; 91 1.2.2.2 skrll uint64_t cpu_int1_en0; 92 1.2.2.2 skrll uint64_t cpu_int2_en0; 93 1.2.2.2 skrll 94 1.2.2.2 skrll uint64_t cpu_int0_en1; 95 1.2.2.2 skrll uint64_t cpu_int1_en1; 96 1.2.2.2 skrll uint64_t cpu_int2_en1; 97 1.2.2.2 skrll 98 1.2.2.2 skrll uint64_t cpu_int32_en; 99 1.2.2.2 skrll 100 1.2.2.2 skrll struct evcnt cpu_intr_evs[NIRQS]; 101 1.2.2.2 skrll 102 1.2.2.2 skrll uint64_t cpu_int0_enable0; 103 1.2.2.2 skrll uint64_t cpu_int1_enable0; 104 1.2.2.2 skrll uint64_t cpu_int2_enable0; 105 1.2.2.2 skrll 106 1.2.2.3 skrll void *cpu_wdog_sih; // wdog softint handler 107 1.2.2.3 skrll uint64_t cpu_wdog; 108 1.2.2.3 skrll uint64_t cpu_pp_poke; 109 1.2.2.3 skrll 110 1.2.2.2 skrll #ifdef MULTIPROCESSOR 111 1.2.2.2 skrll uint64_t cpu_mbox_set; 112 1.2.2.2 skrll uint64_t cpu_mbox_clr; 113 1.2.2.2 skrll #endif 114 1.2.2.2 skrll }; 115 1.2.2.2 skrll 116 1.2.2.2 skrll /* 117 1.2.2.2 skrll * FPA map 118 1.2.2.2 skrll */ 119 1.2.2.2 skrll 120 1.2.2.2 skrll #define OCTEON_POOL_NO_PKT 0 121 1.2.2.2 skrll #define OCTEON_POOL_NO_WQE 1 122 1.2.2.2 skrll #define OCTEON_POOL_NO_CMD 2 123 1.2.2.2 skrll #define OCTEON_POOL_NO_SG 3 124 1.2.2.2 skrll #define OCTEON_POOL_NO_XXX_4 4 125 1.2.2.2 skrll #define OCTEON_POOL_NO_XXX_5 5 126 1.2.2.2 skrll #define OCTEON_POOL_NO_XXX_6 6 127 1.2.2.2 skrll #define OCTEON_POOL_NO_DUMP 7 /* FPA debug dump */ 128 1.2.2.2 skrll 129 1.2.2.2 skrll #define OCTEON_POOL_SIZE_PKT 2048 /* 128 x 16 */ 130 1.2.2.2 skrll #define OCTEON_POOL_SIZE_WQE 128 /* 128 x 1 */ 131 1.2.2.2 skrll #define OCTEON_POOL_SIZE_CMD 1024 /* 128 x 8 */ 132 1.2.2.2 skrll #define OCTEON_POOL_SIZE_SG 512 /* 128 x 4 */ 133 1.2.2.2 skrll #define OCTEON_POOL_SIZE_XXX_4 0 134 1.2.2.2 skrll #define OCTEON_POOL_SIZE_XXX_5 0 135 1.2.2.2 skrll #define OCTEON_POOL_SIZE_XXX_6 0 136 1.2.2.2 skrll #define OCTEON_POOL_SIZE_XXX_7 0 137 1.2.2.2 skrll 138 1.2.2.2 skrll #define OCTEON_POOL_NELEMS_PKT 4096 139 1.2.2.2 skrll #define OCTEON_POOL_NELEMS_WQE 4096 140 1.2.2.2 skrll #define OCTEON_POOL_NELEMS_CMD 32 141 1.2.2.2 skrll #define OCTEON_POOL_NELEMS_SG 1024 142 1.2.2.2 skrll #define OCTEON_POOL_NELEMS_XXX_4 0 143 1.2.2.2 skrll #define OCTEON_POOL_NELEMS_XXX_5 0 144 1.2.2.2 skrll #define OCTEON_POOL_NELEMS_XXX_6 0 145 1.2.2.2 skrll #define OCTEON_POOL_NELEMS_XXX_7 0 146 1.2.2.2 skrll 147 1.2.2.2 skrll /* 148 1.2.2.2 skrll * CVMSEG (``scratch'') memory map 149 1.2.2.2 skrll */ 150 1.2.2.2 skrll struct octeon_cvmseg_map { 151 1.2.2.2 skrll /* 0-3 */ 152 1.2.2.2 skrll uint64_t csm_xxx_0; 153 1.2.2.2 skrll uint64_t csm_xxx_1; 154 1.2.2.2 skrll uint64_t csm_xxx_2; 155 1.2.2.2 skrll uint64_t csm_pow_intr; 156 1.2.2.2 skrll 157 1.2.2.2 skrll /* 4-19 */ 158 1.2.2.2 skrll struct octeon_cvmseg_ether_map { 159 1.2.2.2 skrll uint64_t csm_ether_fau_req; 160 1.2.2.2 skrll uint64_t csm_ether_fau_done; 161 1.2.2.2 skrll uint64_t csm_ether_fau_cmdptr; 162 1.2.2.2 skrll uint64_t csm_ether_xxx_3; 163 1.2.2.2 skrll } csm_ether[4/* XXX */]; 164 1.2.2.2 skrll 165 1.2.2.2 skrll /* 20-32 */ 166 1.2.2.2 skrll uint64_t xxx_20_32[32 - 20]; 167 1.2.2.2 skrll } __packed; 168 1.2.2.2 skrll #define OCTEON_CVMSEG_OFFSET(entry) \ 169 1.2.2.2 skrll offsetof(struct octeon_cvmseg_map, entry) 170 1.2.2.2 skrll #define OCTEON_CVMSEG_ETHER_OFFSET(n, entry) \ 171 1.2.2.2 skrll (offsetof(struct octeon_cvmseg_map, csm_ether) + \ 172 1.2.2.2 skrll sizeof(struct octeon_cvmseg_ether_map) * (n) + \ 173 1.2.2.2 skrll offsetof(struct octeon_cvmseg_ether_map, entry)) 174 1.2.2.2 skrll 175 1.2.2.2 skrll /* 176 1.2.2.2 skrll * FAU register map 177 1.2.2.2 skrll * 178 1.2.2.2 skrll * => FAU registers exist in FAU unit 179 1.2.2.2 skrll * => devices (PKO) can access these registers 180 1.2.2.2 skrll * => CPU can read those values after loading them into CVMSEG 181 1.2.2.2 skrll */ 182 1.2.2.2 skrll struct octeon_fau_map { 183 1.2.2.2 skrll struct { 184 1.2.2.2 skrll /* PKO command index */ 185 1.2.2.2 skrll uint64_t _fau_map_port_pkocmdidx; 186 1.2.2.2 skrll /* send requested */ 187 1.2.2.2 skrll uint64_t _fau_map_port_txreq; 188 1.2.2.2 skrll /* send completed */ 189 1.2.2.2 skrll uint64_t _fau_map_port_txdone; 190 1.2.2.2 skrll /* XXX */ 191 1.2.2.2 skrll uint64_t _fau_map_port_pad; 192 1.2.2.2 skrll } __packed _fau_map_port[3]; 193 1.2.2.2 skrll }; 194 1.2.2.2 skrll 195 1.2.2.2 skrll /* 196 1.2.2.2 skrll * POW qos/group map 197 1.2.2.2 skrll */ 198 1.2.2.2 skrll 199 1.2.2.2 skrll #define OCTEON_POW_QOS_PIP 0 200 1.2.2.2 skrll #define OCTEON_POW_QOS_CORE1 1 201 1.2.2.2 skrll #define OCTEON_POW_QOS_XXX_2 2 202 1.2.2.2 skrll #define OCTEON_POW_QOS_XXX_3 3 203 1.2.2.2 skrll #define OCTEON_POW_QOS_XXX_4 4 204 1.2.2.2 skrll #define OCTEON_POW_QOS_XXX_5 5 205 1.2.2.2 skrll #define OCTEON_POW_QOS_XXX_6 6 206 1.2.2.2 skrll #define OCTEON_POW_QOS_XXX_7 7 207 1.2.2.2 skrll 208 1.2.2.2 skrll #define OCTEON_POW_GROUP_PIP 0 209 1.2.2.2 skrll #define OCTEON_POW_GROUP_XXX_1 1 210 1.2.2.2 skrll #define OCTEON_POW_GROUP_XXX_2 2 211 1.2.2.2 skrll #define OCTEON_POW_GROUP_XXX_3 3 212 1.2.2.2 skrll #define OCTEON_POW_GROUP_XXX_4 4 213 1.2.2.2 skrll #define OCTEON_POW_GROUP_XXX_5 5 214 1.2.2.2 skrll #define OCTEON_POW_GROUP_XXX_6 6 215 1.2.2.2 skrll #define OCTEON_POW_GROUP_CORE1_SEND 7 216 1.2.2.2 skrll #define OCTEON_POW_GROUP_CORE1_TASK_0 8 217 1.2.2.2 skrll #define OCTEON_POW_GROUP_CORE1_TASK_1 9 218 1.2.2.2 skrll #define OCTEON_POW_GROUP_CORE1_TASK_2 10 219 1.2.2.2 skrll #define OCTEON_POW_GROUP_CORE1_TASK_3 11 220 1.2.2.2 skrll #define OCTEON_POW_GROUP_CORE1_TASK_4 12 221 1.2.2.2 skrll #define OCTEON_POW_GROUP_CORE1_TASK_5 13 222 1.2.2.2 skrll #define OCTEON_POW_GROUP_CORE1_TASK_6 14 223 1.2.2.2 skrll #define OCTEON_POW_GROUP_CORE1_TASK_7 15 224 1.2.2.2 skrll 225 1.2.2.2 skrll #ifdef _KERNEL 226 1.2.2.2 skrll extern struct octeon_config octeon_configuration; 227 1.2.2.2 skrll #ifdef MULTIPROCESSOR 228 1.2.2.3 skrll extern kcpuset_t *cpus_booted; 229 1.2.2.2 skrll extern struct cpu_softc octeon_cpu1_softc; 230 1.2.2.2 skrll #endif 231 1.2.2.2 skrll 232 1.2.2.2 skrll void octeon_bus_io_init(bus_space_tag_t, void *); 233 1.2.2.2 skrll void octeon_bus_mem_init(bus_space_tag_t, void *); 234 1.2.2.2 skrll void octeon_cal_timer(int); 235 1.2.2.2 skrll void octeon_dma_init(struct octeon_config *); 236 1.2.2.2 skrll void octeon_intr_init(struct cpu_info *); 237 1.2.2.2 skrll void octeon_iointr(int, vaddr_t, uint32_t); 238 1.2.2.2 skrll void octeon_pci_init(pci_chipset_tag_t, struct octeon_config *); 239 1.2.2.2 skrll void *octeon_intr_establish(int, int, int (*)(void *), void *); 240 1.2.2.2 skrll void octeon_intr_disestablish(void *cookie); 241 1.2.2.2 skrll 242 1.2.2.2 skrll uint64_t mips_cp0_cvmctl_read(void); 243 1.2.2.2 skrll void mips_cp0_cvmctl_write(uint64_t); 244 1.2.2.2 skrll 245 1.2.2.2 skrll #endif /* _KERNEL */ 246 1.2.2.2 skrll 247 1.2.2.2 skrll #if defined(__mips_n32) 248 1.2.2.2 skrll #define ffs64 __builtin_ffsll 249 1.2.2.2 skrll #elif defined(_LP64) 250 1.2.2.2 skrll #define ffs64 __builtin_ffsl 251 1.2.2.2 skrll #else 252 1.2.2.2 skrll #error unknown ABI 253 1.2.2.2 skrll #endif 254 1.2.2.2 skrll 255 1.2.2.3 skrll /* 256 1.2.2.2 skrll * Prefetch 257 1.2.2.2 skrll * 258 1.2.2.2 skrll * OCTEON_PREF normal (L1 and L2) 259 1.2.2.2 skrll * OCTEON_PREF_L1 L1 only 260 1.2.2.2 skrll * OCTEON_PREF_L2 L2 only 261 1.2.2.2 skrll * OCTEON_PREF_DWB don't write back 262 1.2.2.2 skrll * OCTEON_PREF_PFS prepare for store 263 1.2.2.2 skrll */ 264 1.2.2.2 skrll #define __OCTEON_PREF_N(n, base, offset) \ 265 1.2.2.2 skrll __asm __volatile ( \ 266 1.2.2.2 skrll " .set push \ 267 1.2.2.2 skrll " .set arch=octeon \n" \ 268 1.2.2.2 skrll " pref "#n", "#offset"(%[base]) \n" \ 269 1.2.2.2 skrll " .set pop \ 270 1.2.2.2 skrll : : [base] "d" (base) \ 271 1.2.2.2 skrll ) 272 1.2.2.2 skrll #define __OCTEON_PREF_0(base, offset) __OCTEON_PREF_N(0, base, offset) 273 1.2.2.2 skrll #define __OCTEON_PREF_4(base, offset) __OCTEON_PREF_N(4, base, offset) 274 1.2.2.2 skrll #define __OCTEON_PREF_28(base, offset) __OCTEON_PREF_N(28, base, offset) 275 1.2.2.2 skrll #define __OCTEON_PREF_29(base, offset) __OCTEON_PREF_N(29, base, offset) 276 1.2.2.2 skrll #define __OCTEON_PREF_30(base, offset) __OCTEON_PREF_N(30, base, offset) 277 1.2.2.2 skrll #define OCTEON_PREF(base, offset) __OCTEON_PREF_0(base, offset) 278 1.2.2.2 skrll #define OCTEON_PREF_L1(base, offset) __OCTEON_PREF_4(base, offset) 279 1.2.2.2 skrll #define OCTEON_PREF_L2(base, offset) __OCTEON_PREF_28(base, offset) 280 1.2.2.2 skrll #define OCTEON_PREF_DWB(base, offset) __OCTEON_PREF_29(base, offset) 281 1.2.2.2 skrll #define OCTEON_PREF_PFS(base, offset) __OCTEON_PREF_30(base, offset) 282 1.2.2.2 skrll 283 1.2.2.2 skrll /* 284 1.2.2.2 skrll * Sync 285 1.2.2.2 skrll */ 286 1.2.2.2 skrll #define OCTEON_SYNCCOMMON(name) \ 287 1.2.2.2 skrll __asm __volatile ( \ 288 1.2.2.2 skrll _ASM_PROLOGUE_OCTEON \ 289 1.2.2.2 skrll " "#name" \n" \ 290 1.2.2.2 skrll _ASM_EPILOGUE \ 291 1.2.2.2 skrll ::: "memory") 292 1.2.2.2 skrll #define OCTEON_SYNCIOBDMA OCTEON_SYNCCOMMON(synciobdma) 293 1.2.2.2 skrll #define OCTEON_SYNCW OCTEON_SYNCCOMMON(syncw) 294 1.2.2.2 skrll #define OCTEON_SYNC OCTEON_SYNCCOMMON(sync) 295 1.2.2.2 skrll #define OCTEON_SYNCWS OCTEON_SYNCCOMMON(syncws) 296 1.2.2.2 skrll #define OCTEON_SYNCS OCTEON_SYNCCOMMON(syncs) 297 1.2.2.2 skrll /* XXX backward compatibility */ 298 1.2.2.2 skrll #if 1 299 1.2.2.2 skrll #define OCT_SYNCIOBDMA OCTEON_SYNCIOBDMA 300 1.2.2.2 skrll #define OCT_SYNCW OCTEON_SYNCW 301 1.2.2.2 skrll #define OCT_SYNC OCTEON_SYNC 302 1.2.2.2 skrll #define OCT_SYNCWS OCTEON_SYNCWS 303 1.2.2.2 skrll #define OCT_SYNCS OCTEON_SYNCS 304 1.2.2.2 skrll #endif 305 1.2.2.2 skrll 306 1.2.2.2 skrll /* octeon core does not use cca to determine cacheability */ 307 1.2.2.2 skrll #define OCTEON_CCA_NONE UINT64_C(0) 308 1.2.2.2 skrll 309 1.2.2.2 skrll static inline uint64_t 310 1.2.2.2 skrll octeon_xkphys_read_8(paddr_t address) 311 1.2.2.2 skrll { 312 1.2.2.2 skrll return mips64_ld_a64(MIPS_PHYS_TO_XKPHYS(OCTEON_CCA_NONE, address)); 313 1.2.2.2 skrll } 314 1.2.2.2 skrll 315 1.2.2.2 skrll static inline void 316 1.2.2.2 skrll octeon_xkphys_write_8(paddr_t address, uint64_t value) 317 1.2.2.2 skrll { 318 1.2.2.2 skrll mips64_sd_a64(MIPS_PHYS_TO_XKPHYS(OCTEON_CCA_NONE, address), value); 319 1.2.2.2 skrll } 320 1.2.2.2 skrll 321 1.2.2.2 skrll /* XXX backward compatibility */ 322 1.2.2.2 skrll #if 1 323 1.2.2.2 skrll #define octeon_read_csr(address) \ 324 1.2.2.2 skrll octeon_xkphys_read_8(address) 325 1.2.2.2 skrll #define octeon_write_csr(address, value) \ 326 1.2.2.2 skrll octeon_xkphys_write_8(address, value) 327 1.2.2.2 skrll #endif 328 1.2.2.2 skrll 329 1.2.2.2 skrll static inline void 330 1.2.2.2 skrll octeon_iobdma_write_8(uint64_t value) 331 1.2.2.2 skrll { 332 1.2.2.2 skrll uint64_t addr = UINT64_C(0xffffffffffffa200); 333 1.2.2.2 skrll 334 1.2.2.2 skrll octeon_xkphys_write_8(addr, value); 335 1.2.2.2 skrll } 336 1.2.2.2 skrll 337 1.2.2.2 skrll static inline uint64_t 338 1.2.2.2 skrll octeon_cvmseg_read_8(size_t offset) 339 1.2.2.2 skrll { 340 1.2.2.2 skrll return octeon_xkphys_read_8(UINT64_C(0xffffffffffff8000) + offset); 341 1.2.2.2 skrll } 342 1.2.2.2 skrll 343 1.2.2.2 skrll static inline void 344 1.2.2.2 skrll octeon_cvmseg_write_8(size_t offset, uint64_t value) 345 1.2.2.2 skrll { 346 1.2.2.2 skrll octeon_xkphys_write_8(UINT64_C(0xffffffffffff8000) + offset, value); 347 1.2.2.2 skrll } 348 1.2.2.2 skrll 349 1.2.2.2 skrll /* XXX */ 350 1.2.2.2 skrll static inline uint32_t 351 1.2.2.2 skrll octeon_disable_interrupt(uint32_t *new) 352 1.2.2.2 skrll { 353 1.2.2.2 skrll uint32_t s, tmp; 354 1.2.2.3 skrll 355 1.2.2.2 skrll __asm __volatile ( 356 1.2.2.2 skrll _ASM_PROLOGUE 357 1.2.2.2 skrll " mfc0 %[s], $12 \n" 358 1.2.2.2 skrll " and %[tmp], %[s], ~1 \n" 359 1.2.2.2 skrll " mtc0 %[tmp], $12 \n" 360 1.2.2.2 skrll _ASM_EPILOGUE 361 1.2.2.2 skrll : [s]"=&r"(s), [tmp]"=&r"(tmp)); 362 1.2.2.2 skrll if (new) 363 1.2.2.2 skrll *new = tmp; 364 1.2.2.2 skrll return s; 365 1.2.2.2 skrll } 366 1.2.2.2 skrll 367 1.2.2.2 skrll /* XXX */ 368 1.2.2.2 skrll static inline void 369 1.2.2.2 skrll octeon_restore_status(uint32_t s) 370 1.2.2.2 skrll { 371 1.2.2.2 skrll __asm __volatile ( 372 1.2.2.2 skrll _ASM_PROLOGUE 373 1.2.2.2 skrll " mtc0 %[s], $12 \n" 374 1.2.2.2 skrll _ASM_EPILOGUE 375 1.2.2.2 skrll :: [s]"r"(s)); 376 1.2.2.2 skrll } 377 1.2.2.2 skrll 378 1.2.2.2 skrll static inline uint64_t 379 1.2.2.2 skrll octeon_get_cycles(void) 380 1.2.2.3 skrll { 381 1.2.2.2 skrll #if defined(__mips_o32) 382 1.2.2.2 skrll uint32_t s, lo, hi; 383 1.2.2.3 skrll 384 1.2.2.2 skrll s = octeon_disable_interrupt((void *)0); 385 1.2.2.2 skrll __asm __volatile ( 386 1.2.2.2 skrll _ASM_PROLOGUE_MIPS64 387 1.2.2.2 skrll " dmfc0 %[lo], $9, 6 \n" 388 1.2.2.2 skrll " add %[hi], %[lo], $0 \n" 389 1.2.2.2 skrll " srl %[hi], 32 \n" 390 1.2.2.2 skrll " sll %[lo], 32 \n" 391 1.2.2.2 skrll " srl %[lo], 32 \n" 392 1.2.2.2 skrll _ASM_EPILOGUE 393 1.2.2.2 skrll : [lo]"=&r"(lo), [hi]"=&r"(hi)); 394 1.2.2.2 skrll octeon_restore_status(s); 395 1.2.2.2 skrll return ((uint64_t)hi << 32) + (uint64_t)lo; 396 1.2.2.2 skrll #else 397 1.2.2.2 skrll uint64_t tmp; 398 1.2.2.2 skrll 399 1.2.2.2 skrll __asm __volatile ( 400 1.2.2.2 skrll _ASM_PROLOGUE_MIPS64 401 1.2.2.2 skrll " dmfc0 %[tmp], $9, 6 \n" 402 1.2.2.2 skrll _ASM_EPILOGUE 403 1.2.2.2 skrll : [tmp]"=&r"(tmp)); 404 1.2.2.2 skrll return tmp; 405 1.2.2.2 skrll #endif 406 1.2.2.2 skrll } 407 1.2.2.2 skrll 408 1.2.2.2 skrll /* -------------------------------------------------------------------------- */ 409 1.2.2.2 skrll 410 1.2.2.2 skrll /* ---- event counter */ 411 1.2.2.2 skrll 412 1.2.2.2 skrll #if defined(OCTEON_ETH_DEBUG) 413 1.2.2.2 skrll #define OCTEON_EVCNT_INC(sc, name) \ 414 1.2.2.2 skrll do { (sc)->sc_ev_##name.ev_count++; } while (0) 415 1.2.2.2 skrll #define OCTEON_EVCNT_ADD(sc, name, n) \ 416 1.2.2.2 skrll do { (sc)->sc_ev_##name.ev_count += (n); } while (0) 417 1.2.2.2 skrll #define OCTEON_EVCNT_ATTACH_EVCNTS(sc, entries, devname) \ 418 1.2.2.2 skrll do { \ 419 1.2.2.2 skrll int i; \ 420 1.2.2.2 skrll const struct octeon_evcnt_entry *ee; \ 421 1.2.2.2 skrll \ 422 1.2.2.2 skrll for (i = 0; i < (int)__arraycount(entries); i++) { \ 423 1.2.2.2 skrll ee = &(entries)[i]; \ 424 1.2.2.2 skrll evcnt_attach_dynamic( \ 425 1.2.2.2 skrll (struct evcnt *)((uintptr_t)(sc) + ee->ee_offset), \ 426 1.2.2.2 skrll ee->ee_type, ee->ee_parent, devname, \ 427 1.2.2.2 skrll ee->ee_name); \ 428 1.2.2.2 skrll } \ 429 1.2.2.2 skrll } while (0) 430 1.2.2.2 skrll #else 431 1.2.2.2 skrll #define OCTEON_EVCNT_INC(sc, name) 432 1.2.2.2 skrll #define OCTEON_EVCNT_ADD(sc, name, n) 433 1.2.2.2 skrll #define OCTEON_EVCNT_ATTACH_EVCNTS(sc, entries, devname) 434 1.2.2.2 skrll #endif 435 1.2.2.2 skrll 436 1.2.2.2 skrll struct octeon_evcnt_entry { 437 1.2.2.2 skrll size_t ee_offset; 438 1.2.2.2 skrll int ee_type; 439 1.2.2.2 skrll struct evcnt *ee_parent; 440 1.2.2.2 skrll const char *ee_name; 441 1.2.2.2 skrll }; 442 1.2.2.2 skrll 443 1.2.2.2 skrll #define OCTEON_EVCNT_ENTRY(_sc_type, _var, _ev_type, _parent, _name) \ 444 1.2.2.2 skrll { \ 445 1.2.2.2 skrll .ee_offset = offsetof(_sc_type, sc_ev_##_var), \ 446 1.2.2.2 skrll .ee_type = EVCNT_TYPE_##_ev_type, \ 447 1.2.2.2 skrll .ee_parent = _parent, \ 448 1.2.2.2 skrll .ee_name = _name \ 449 1.2.2.2 skrll } 450 1.2.2.2 skrll 451 1.2.2.2 skrll #endif /* _MIPS_OCTEON_OCTEONVAR_H_ */ 452
Indexes created Wed Oct 15 16:09:53 GMT 2025