octeonvar.h revision 1.10
1 /* $NetBSD: octeonvar.h,v 1.10 2020/06/15 07:48:12 simonb Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _MIPS_OCTEON_OCTEONVAR_H_ 33 #define _MIPS_OCTEON_OCTEONVAR_H_ 34 35 #include <sys/bus.h> 36 #include <sys/evcnt.h> 37 #include <sys/kcpuset.h> 38 #include <mips/locore.h> 39 #include <dev/pci/pcivar.h> 40 41 /* XXX elsewhere */ 42 #define _ASM_PROLOGUE \ 43 " .set push \n" \ 44 " .set noreorder \n" 45 #define _ASM_PROLOGUE_MIPS64 \ 46 _ASM_PROLOGUE \ 47 " .set mips64 \n" 48 #define _ASM_PROLOGUE_OCTEON \ 49 _ASM_PROLOGUE \ 50 " .set arch=octeon \n" 51 #define _ASM_EPILOGUE \ 52 " .set pop \n" 53 /* 54 * subbits = __BITS64_GET(XXX, bits); 55 * bits = __BITS64_SET(XXX, subbits); 56 */ 57 #ifndef __BITS64_GET 58 #define __BITS64_GET(name, bits) \ 59 (((uint64_t)(bits) & name) >> name##_SHIFT) 60 #endif 61 #ifndef __BITS64_SET 62 #define __BITS64_SET(name, subbits) \ 63 (((uint64_t)(subbits) << name##_SHIFT) & name) 64 #endif 65 66 #ifdef _KERNEL 67 extern int octeon_core_ver; 68 #endif /* _KERNEL */ 69 #define OCTEON_1 1 70 #define OCTEON_PLUS 10 /* arbitary, keep sequence for others */ 71 #define OCTEON_2 2 72 #define OCTEON_3 3 73 74 struct octeon_config { 75 struct mips_bus_space mc_iobus_bust; 76 struct mips_bus_space mc_bootbus_bust; 77 struct mips_pci_chipset mc_pc; 78 79 struct mips_bus_dma_tag mc_iobus_dmat; 80 struct mips_bus_dma_tag mc_bootbus_dmat; 81 struct mips_bus_dma_tag mc_core1_dmat; 82 struct mips_bus_dma_tag mc_fpa_dmat; 83 84 struct extent *mc_io_ex; 85 struct extent *mc_mem_ex; 86 87 int mc_mallocsafe; 88 }; 89 90 #define NIRQS 64 91 92 struct cpu_softc { 93 struct cpu_info *cpu_ci; 94 95 uint64_t cpu_int0_sum0; 96 uint64_t cpu_int1_sum0; 97 uint64_t cpu_int2_sum0; 98 99 uint64_t cpu_int0_en0; 100 uint64_t cpu_int1_en0; 101 uint64_t cpu_int2_en0; 102 103 uint64_t cpu_int0_en1; 104 uint64_t cpu_int1_en1; 105 uint64_t cpu_int2_en1; 106 107 uint64_t cpu_int32_en; 108 109 struct evcnt cpu_intr_evs[NIRQS]; 110 111 uint64_t cpu_int0_enable0; 112 uint64_t cpu_int1_enable0; 113 uint64_t cpu_int2_enable0; 114 115 void *cpu_wdog_sih; // wdog softint handler 116 uint64_t cpu_wdog; 117 uint64_t cpu_pp_poke; 118 119 #ifdef MULTIPROCESSOR 120 uint64_t cpu_mbox_set; 121 uint64_t cpu_mbox_clr; 122 #endif 123 }; 124 125 /* 126 * FPA map 127 */ 128 129 #define OCTEON_POOL_NO_PKT 0 130 #define OCTEON_POOL_NO_WQE 1 131 #define OCTEON_POOL_NO_CMD 2 132 #define OCTEON_POOL_NO_SG 3 133 #define OCTEON_POOL_NO_XXX_4 4 134 #define OCTEON_POOL_NO_XXX_5 5 135 #define OCTEON_POOL_NO_XXX_6 6 136 #define OCTEON_POOL_NO_DUMP 7 /* FPA debug dump */ 137 138 #define OCTEON_POOL_SIZE_PKT 2048 /* 128 x 16 */ 139 #define OCTEON_POOL_SIZE_WQE 128 /* 128 x 1 */ 140 #define OCTEON_POOL_SIZE_CMD 1024 /* 128 x 8 */ 141 #define OCTEON_POOL_SIZE_SG 512 /* 128 x 4 */ 142 #define OCTEON_POOL_SIZE_XXX_4 0 143 #define OCTEON_POOL_SIZE_XXX_5 0 144 #define OCTEON_POOL_SIZE_XXX_6 0 145 #define OCTEON_POOL_SIZE_XXX_7 0 146 147 #define OCTEON_POOL_NELEMS_PKT 4096 148 #define OCTEON_POOL_NELEMS_WQE 4096 149 #define OCTEON_POOL_NELEMS_CMD 32 150 #define OCTEON_POOL_NELEMS_SG 1024 151 #define OCTEON_POOL_NELEMS_XXX_4 0 152 #define OCTEON_POOL_NELEMS_XXX_5 0 153 #define OCTEON_POOL_NELEMS_XXX_6 0 154 #define OCTEON_POOL_NELEMS_XXX_7 0 155 156 /* 157 * CVMSEG (``scratch'') memory map 158 */ 159 160 #define CVMSEG_LM_RNM_SIZE 16 /* limited by CN70XX hardware (why?) */ 161 #define CVMSEG_LM_ETHER_COUNT 4 /* limits number of cnmac devices */ 162 163 struct octeon_cvmseg_map { 164 uint64_t csm_pow_intr; 165 166 struct octeon_cvmseg_ether_map { 167 uint64_t csm_ether_fau_done; 168 } csm_ether[CVMSEG_LM_ETHER_COUNT]; 169 170 uint64_t csm_rnm[CVMSEG_LM_RNM_SIZE]; 171 } __packed; 172 #define OCTEON_CVMSEG_OFFSET(entry) \ 173 offsetof(struct octeon_cvmseg_map, entry) 174 #define OCTEON_CVMSEG_ETHER_OFFSET(n, entry) \ 175 (offsetof(struct octeon_cvmseg_map, csm_ether) + \ 176 sizeof(struct octeon_cvmseg_ether_map) * (n) + \ 177 offsetof(struct octeon_cvmseg_ether_map, entry)) 178 179 /* 180 * FAU register map 181 * 182 * => FAU registers exist in FAU unit 183 * => devices (PKO) can access these registers 184 * => CPU can read those values after loading them into CVMSEG 185 */ 186 struct octfau_map { 187 struct { 188 /* PKO command index */ 189 uint64_t _fau_map_port_pkocmdidx; 190 /* send requested */ 191 uint64_t _fau_map_port_txreq; 192 /* send completed */ 193 uint64_t _fau_map_port_txdone; 194 /* XXX */ 195 uint64_t _fau_map_port_pad; 196 } __packed _fau_map_port[3]; 197 }; 198 199 /* 200 * POW qos/group map 201 */ 202 203 #define OCTEON_POW_QOS_PIP 0 204 #define OCTEON_POW_QOS_CORE1 1 205 #define OCTEON_POW_QOS_XXX_2 2 206 #define OCTEON_POW_QOS_XXX_3 3 207 #define OCTEON_POW_QOS_XXX_4 4 208 #define OCTEON_POW_QOS_XXX_5 5 209 #define OCTEON_POW_QOS_XXX_6 6 210 #define OCTEON_POW_QOS_XXX_7 7 211 212 #define OCTEON_POW_GROUP_PIP 0 213 #define OCTEON_POW_GROUP_XXX_1 1 214 #define OCTEON_POW_GROUP_XXX_2 2 215 #define OCTEON_POW_GROUP_XXX_3 3 216 #define OCTEON_POW_GROUP_XXX_4 4 217 #define OCTEON_POW_GROUP_XXX_5 5 218 #define OCTEON_POW_GROUP_XXX_6 6 219 #define OCTEON_POW_GROUP_CORE1_SEND 7 220 #define OCTEON_POW_GROUP_CORE1_TASK_0 8 221 #define OCTEON_POW_GROUP_CORE1_TASK_1 9 222 #define OCTEON_POW_GROUP_CORE1_TASK_2 10 223 #define OCTEON_POW_GROUP_CORE1_TASK_3 11 224 #define OCTEON_POW_GROUP_CORE1_TASK_4 12 225 #define OCTEON_POW_GROUP_CORE1_TASK_5 13 226 #define OCTEON_POW_GROUP_CORE1_TASK_6 14 227 #define OCTEON_POW_GROUP_CORE1_TASK_7 15 228 229 #ifdef _KERNEL 230 extern struct octeon_config octeon_configuration; 231 #ifdef MULTIPROCESSOR 232 extern kcpuset_t *cpus_booted; 233 extern struct cpu_softc octeon_cpu1_softc; 234 #endif 235 236 const char *octeon_cpu_model(mips_prid_t); 237 238 void octeon_bus_io_init(bus_space_tag_t, void *); 239 void octeon_bus_mem_init(bus_space_tag_t, void *); 240 void octeon_cal_timer(int); 241 void octeon_dma_init(struct octeon_config *); 242 void octeon_intr_init(struct cpu_info *); 243 void octeon_iointr(int, vaddr_t, uint32_t); 244 void octpci_init(pci_chipset_tag_t, struct octeon_config *); 245 void *octeon_intr_establish(int, int, int (*)(void *), void *); 246 void octeon_intr_disestablish(void *cookie); 247 248 int octeon_ioclock_speed(void); 249 void octeon_soft_reset(void); 250 251 void octeon_reset_vector(void); 252 uint64_t mips_cp0_cvmctl_read(void); 253 void mips_cp0_cvmctl_write(uint64_t); 254 #endif /* _KERNEL */ 255 256 #if defined(__mips_n32) 257 #define ffs64 __builtin_ffsll 258 #elif defined(_LP64) 259 #define ffs64 __builtin_ffsl 260 #else 261 #error unknown ABI 262 #endif 263 264 /* 265 * Prefetch 266 * 267 * OCTEON_PREF normal (L1 and L2) 268 * OCTEON_PREF_L1 L1 only 269 * OCTEON_PREF_L2 L2 only 270 * OCTEON_PREF_DWB don't write back 271 * OCTEON_PREF_PFS prepare for store 272 */ 273 #define __OCTEON_PREF_N(n, base, offset) \ 274 __asm __volatile ( \ 275 " .set push \ 276 " .set arch=octeon \n" \ 277 " pref "#n", "#offset"(%[base]) \n" \ 278 " .set pop \ 279 : : [base] "d" (base) \ 280 ) 281 #define __OCTEON_PREF_0(base, offset) __OCTEON_PREF_N(0, base, offset) 282 #define __OCTEON_PREF_4(base, offset) __OCTEON_PREF_N(4, base, offset) 283 #define __OCTEON_PREF_28(base, offset) __OCTEON_PREF_N(28, base, offset) 284 #define __OCTEON_PREF_29(base, offset) __OCTEON_PREF_N(29, base, offset) 285 #define __OCTEON_PREF_30(base, offset) __OCTEON_PREF_N(30, base, offset) 286 #define OCTEON_PREF(base, offset) __OCTEON_PREF_0(base, offset) 287 #define OCTEON_PREF_L1(base, offset) __OCTEON_PREF_4(base, offset) 288 #define OCTEON_PREF_L2(base, offset) __OCTEON_PREF_28(base, offset) 289 #define OCTEON_PREF_DWB(base, offset) __OCTEON_PREF_29(base, offset) 290 #define OCTEON_PREF_PFS(base, offset) __OCTEON_PREF_30(base, offset) 291 292 /* 293 * Sync 294 */ 295 #define OCTEON_SYNCCOMMON(name) \ 296 __asm __volatile ( \ 297 _ASM_PROLOGUE_OCTEON \ 298 " "#name" \n" \ 299 _ASM_EPILOGUE \ 300 ::: "memory") 301 #define OCTEON_SYNCIOBDMA OCTEON_SYNCCOMMON(synciobdma) 302 #define OCTEON_SYNCW OCTEON_SYNCCOMMON(syncw) 303 #define OCTEON_SYNC OCTEON_SYNCCOMMON(sync) 304 #define OCTEON_SYNCWS OCTEON_SYNCCOMMON(syncws) 305 #define OCTEON_SYNCS OCTEON_SYNCCOMMON(syncs) 306 /* XXX backward compatibility */ 307 #if 1 308 #define OCT_SYNCIOBDMA OCTEON_SYNCIOBDMA 309 #define OCT_SYNCW OCTEON_SYNCW 310 #define OCT_SYNC OCTEON_SYNC 311 #define OCT_SYNCWS OCTEON_SYNCWS 312 #define OCT_SYNCS OCTEON_SYNCS 313 #endif 314 315 /* octeon core does not use cca to determine cacheability */ 316 #define OCTEON_CCA_NONE UINT64_C(0) 317 318 static __inline uint64_t 319 octeon_xkphys_read_8(paddr_t address) 320 { 321 return mips3_ld(MIPS_PHYS_TO_XKPHYS(OCTEON_CCA_NONE, address)); 322 } 323 324 static __inline void 325 octeon_xkphys_write_8(paddr_t address, uint64_t value) 326 { 327 mips3_sd(MIPS_PHYS_TO_XKPHYS(OCTEON_CCA_NONE, address), value); 328 } 329 330 /* XXX backward compatibility */ 331 #if 1 332 #define octeon_read_csr(address) \ 333 octeon_xkphys_read_8(address) 334 #define octeon_write_csr(address, value) \ 335 octeon_xkphys_write_8(address, value) 336 #endif 337 338 static __inline void 339 octeon_iobdma_write_8(uint64_t value) 340 { 341 uint64_t addr = UINT64_C(0xffffffffffffa200); 342 343 octeon_xkphys_write_8(addr, value); 344 } 345 346 static __inline uint64_t 347 octeon_cvmseg_read_8(size_t offset) 348 { 349 return octeon_xkphys_read_8(UINT64_C(0xffffffffffff8000) + offset); 350 } 351 352 static __inline void 353 octeon_cvmseg_write_8(size_t offset, uint64_t value) 354 { 355 octeon_xkphys_write_8(UINT64_C(0xffffffffffff8000) + offset, value); 356 } 357 358 /* XXX */ 359 static __inline uint32_t 360 octeon_disable_interrupt(uint32_t *new) 361 { 362 uint32_t s, tmp; 363 364 __asm __volatile ( 365 _ASM_PROLOGUE 366 " mfc0 %[s], $12 \n" 367 " and %[tmp], %[s], ~1 \n" 368 " mtc0 %[tmp], $12 \n" 369 _ASM_EPILOGUE 370 : [s]"=&r"(s), [tmp]"=&r"(tmp)); 371 if (new) 372 *new = tmp; 373 return s; 374 } 375 376 /* XXX */ 377 static __inline void 378 octeon_restore_status(uint32_t s) 379 { 380 __asm __volatile ( 381 _ASM_PROLOGUE 382 " mtc0 %[s], $12 \n" 383 _ASM_EPILOGUE 384 :: [s]"r"(s)); 385 } 386 387 static __inline uint64_t 388 octeon_get_cycles(void) 389 { 390 #if defined(__mips_o32) 391 uint32_t s, lo, hi; 392 393 s = octeon_disable_interrupt((void *)0); 394 __asm __volatile ( 395 _ASM_PROLOGUE_MIPS64 396 " dmfc0 %[lo], $9, 6 \n" 397 " add %[hi], %[lo], $0 \n" 398 " srl %[hi], 32 \n" 399 " sll %[lo], 32 \n" 400 " srl %[lo], 32 \n" 401 _ASM_EPILOGUE 402 : [lo]"=&r"(lo), [hi]"=&r"(hi)); 403 octeon_restore_status(s); 404 return ((uint64_t)hi << 32) + (uint64_t)lo; 405 #else 406 uint64_t tmp; 407 408 __asm __volatile ( 409 _ASM_PROLOGUE_MIPS64 410 " dmfc0 %[tmp], $9, 6 \n" 411 _ASM_EPILOGUE 412 : [tmp]"=&r"(tmp)); 413 return tmp; 414 #endif 415 } 416 417 /* -------------------------------------------------------------------------- */ 418 419 /* ---- event counter */ 420 421 #if defined(CNMAC_DEBUG) 422 #define OCTEON_EVCNT_INC(sc, name) \ 423 do { (sc)->sc_ev_##name.ev_count++; } while (0) 424 #define OCTEON_EVCNT_ADD(sc, name, n) \ 425 do { (sc)->sc_ev_##name.ev_count += (n); } while (0) 426 #define OCTEON_EVCNT_ATTACH_EVCNTS(sc, entries, devname) \ 427 do { \ 428 int i; \ 429 const struct octeon_evcnt_entry *ee; \ 430 \ 431 for (i = 0; i < (int)__arraycount(entries); i++) { \ 432 ee = &(entries)[i]; \ 433 evcnt_attach_dynamic( \ 434 (struct evcnt *)((uintptr_t)(sc) + ee->ee_offset), \ 435 ee->ee_type, ee->ee_parent, devname, \ 436 ee->ee_name); \ 437 } \ 438 } while (0) 439 #else 440 #define OCTEON_EVCNT_INC(sc, name) 441 #define OCTEON_EVCNT_ADD(sc, name, n) 442 #define OCTEON_EVCNT_ATTACH_EVCNTS(sc, entries, devname) 443 #endif 444 445 struct octeon_evcnt_entry { 446 size_t ee_offset; 447 int ee_type; 448 struct evcnt *ee_parent; 449 const char *ee_name; 450 }; 451 452 #define OCTEON_EVCNT_ENTRY(_sc_type, _var, _ev_type, _parent, _name) \ 453 { \ 454 .ee_offset = offsetof(_sc_type, sc_ev_##_var), \ 455 .ee_type = EVCNT_TYPE_##_ev_type, \ 456 .ee_parent = _parent, \ 457 .ee_name = _name \ 458 } 459 460 #endif /* _MIPS_OCTEON_OCTEONVAR_H_ */ 461
Indexes created Sun Sep 28 16:09:52 GMT 2025