asm.h revision 1.58
1 /* $NetBSD: asm.h,v 1.58 2020/08/06 10:00:20 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)machAsmDefs.h 8.1 (Berkeley) 6/10/93 35 */ 36 37 /* 38 * machAsmDefs.h -- 39 * 40 * Macros used when writing assembler programs. 41 * 42 * Copyright (C) 1989 Digital Equipment Corporation. 43 * Permission to use, copy, modify, and distribute this software and 44 * its documentation for any purpose and without fee is hereby granted, 45 * provided that the above copyright notice appears in all copies. 46 * Digital Equipment Corporation makes no representations about the 47 * suitability of this software for any purpose. It is provided "as is" 48 * without express or implied warranty. 49 * 50 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAsmDefs.h, 51 * v 1.2 89/08/15 18:28:24 rab Exp SPRITE (DECWRL) 52 */ 53 54 #ifndef _MIPS_ASM_H 55 #define _MIPS_ASM_H 56 57 #include "opt_cputype.h" 58 #include "opt_lockdebug.h" 59 #include "opt_multiprocessor.h" 60 61 #include <sys/cdefs.h> /* for API selection */ 62 #include <mips/regdef.h> 63 64 /* 65 * Define -pg profile entry code. 66 * Must always be noreorder, must never use a macro instruction 67 * Final addiu to t9 must always equal the size of this _KERN_MCOUNT 68 */ 69 #define _KERN_MCOUNT \ 70 .set push; \ 71 .set noreorder; \ 72 .set noat; \ 73 subu sp,sp,16; \ 74 sw t9,12(sp); \ 75 move AT,ra; \ 76 lui t9,%hi(_mcount); \ 77 addiu t9,t9,%lo(_mcount); \ 78 jalr t9; \ 79 nop; \ 80 lw t9,4(sp); \ 81 addiu sp,sp,8; \ 82 addiu t9,t9,40; \ 83 .set pop; 84 85 #ifdef GPROF 86 #define MCOUNT _KERN_MCOUNT 87 #else 88 #define MCOUNT 89 #endif 90 91 #ifdef USE_AENT 92 #define AENT(x) \ 93 .aent x, 0 94 #else 95 #define AENT(x) 96 #endif 97 98 /* 99 * WEAK_ALIAS: create a weak alias. 100 */ 101 #define WEAK_ALIAS(alias,sym) \ 102 .weak alias; \ 103 alias = sym 104 /* 105 * STRONG_ALIAS: create a strong alias. 106 */ 107 #define STRONG_ALIAS(alias,sym) \ 108 .globl alias; \ 109 alias = sym 110 111 /* 112 * WARN_REFERENCES: create a warning if the specified symbol is referenced. 113 */ 114 #define WARN_REFERENCES(sym,msg) \ 115 .pushsection __CONCAT(.gnu.warning.,sym); \ 116 .ascii msg; \ 117 .popsection 118 119 /* 120 * STATIC_LEAF_NOPROFILE 121 * No profilable local leaf routine. 122 */ 123 #define STATIC_LEAF_NOPROFILE(x) \ 124 .ent _C_LABEL(x); \ 125 _C_LABEL(x): ; \ 126 .frame sp, 0, ra 127 128 /* 129 * LEAF_NOPROFILE 130 * No profilable leaf routine. 131 */ 132 #define LEAF_NOPROFILE(x) \ 133 .globl _C_LABEL(x); \ 134 STATIC_LEAF_NOPROFILE(x) 135 136 /* 137 * STATIC_LEAF 138 * Declare a local leaf function. 139 */ 140 #define STATIC_LEAF(x) \ 141 STATIC_LEAF_NOPROFILE(x); \ 142 MCOUNT 143 144 /* 145 * LEAF 146 * A leaf routine does 147 * - call no other function, 148 * - never use any register that callee-saved (S0-S8), and 149 * - not use any local stack storage. 150 */ 151 #define LEAF(x) \ 152 LEAF_NOPROFILE(x); \ 153 MCOUNT 154 155 /* 156 * STATIC_XLEAF 157 * declare alternate entry to a static leaf routine 158 */ 159 #define STATIC_XLEAF(x) \ 160 AENT (_C_LABEL(x)); \ 161 _C_LABEL(x): 162 163 /* 164 * XLEAF 165 * declare alternate entry to leaf routine 166 */ 167 #define XLEAF(x) \ 168 .globl _C_LABEL(x); \ 169 STATIC_XLEAF(x) 170 171 /* 172 * STATIC_NESTED_NOPROFILE 173 * No profilable local nested routine. 174 */ 175 #define STATIC_NESTED_NOPROFILE(x, fsize, retpc) \ 176 .ent _C_LABEL(x); \ 177 .type _C_LABEL(x), @function; \ 178 _C_LABEL(x): ; \ 179 .frame sp, fsize, retpc 180 181 /* 182 * NESTED_NOPROFILE 183 * No profilable nested routine. 184 */ 185 #define NESTED_NOPROFILE(x, fsize, retpc) \ 186 .globl _C_LABEL(x); \ 187 STATIC_NESTED_NOPROFILE(x, fsize, retpc) 188 189 /* 190 * NESTED 191 * A function calls other functions and needs 192 * therefore stack space to save/restore registers. 193 */ 194 #define NESTED(x, fsize, retpc) \ 195 NESTED_NOPROFILE(x, fsize, retpc); \ 196 MCOUNT 197 198 /* 199 * STATIC_NESTED 200 * No profilable local nested routine. 201 */ 202 #define STATIC_NESTED(x, fsize, retpc) \ 203 STATIC_NESTED_NOPROFILE(x, fsize, retpc); \ 204 MCOUNT 205 206 /* 207 * XNESTED 208 * declare alternate entry point to nested routine. 209 */ 210 #define XNESTED(x) \ 211 .globl _C_LABEL(x); \ 212 AENT (_C_LABEL(x)); \ 213 _C_LABEL(x): 214 215 /* 216 * END 217 * Mark end of a procedure. 218 */ 219 #define END(x) \ 220 .end _C_LABEL(x); \ 221 .size _C_LABEL(x), . - _C_LABEL(x) 222 223 /* 224 * IMPORT -- import external symbol 225 */ 226 #define IMPORT(sym, size) \ 227 .extern _C_LABEL(sym),size 228 229 /* 230 * EXPORT -- export definition of symbol 231 */ 232 #define EXPORT(x) \ 233 .globl _C_LABEL(x); \ 234 _C_LABEL(x): 235 236 /* 237 * VECTOR 238 * exception vector entrypoint 239 * XXX: regmask should be used to generate .mask 240 */ 241 #define VECTOR(x, regmask) \ 242 .ent _C_LABEL(x); \ 243 EXPORT(x); \ 244 245 #define VECTOR_END(x) \ 246 EXPORT(__CONCAT(x,_end)); \ 247 END(x); \ 248 .org _C_LABEL(x) + 0x80 249 250 /* 251 * Macros to panic and printf from assembly language. 252 */ 253 #define PANIC(msg) \ 254 PTR_LA a0, 9f; \ 255 jal _C_LABEL(panic); \ 256 nop; \ 257 MSG(msg) 258 259 #define PRINTF(msg) \ 260 PTR_LA a0, 9f; \ 261 jal _C_LABEL(printf); \ 262 nop; \ 263 MSG(msg) 264 265 #define MSG(msg) \ 266 .rdata; \ 267 9: .asciz msg; \ 268 .text 269 270 #define ASMSTR(str) \ 271 .asciz str; \ 272 .align 3 273 274 #define RCSID(x) .pushsection ".ident","MS",@progbits,1; \ 275 .asciz x; \ 276 .popsection 277 278 /* 279 * XXX retain dialects XXX 280 */ 281 #define ALEAF(x) XLEAF(x) 282 #define NLEAF(x) LEAF_NOPROFILE(x) 283 #define NON_LEAF(x, fsize, retpc) NESTED(x, fsize, retpc) 284 #define NNON_LEAF(x, fsize, retpc) NESTED_NOPROFILE(x, fsize, retpc) 285 286 #if defined(__mips_o32) 287 #define SZREG 4 288 #else 289 #define SZREG 8 290 #endif 291 292 #if defined(__mips_o32) || defined(__mips_o64) 293 #define ALSK 7 /* stack alignment */ 294 #define ALMASK -7 /* stack alignment */ 295 #define SZFPREG 4 296 #define FP_L lwc1 297 #define FP_S swc1 298 #else 299 #define ALSK 15 /* stack alignment */ 300 #define ALMASK -15 /* stack alignment */ 301 #define SZFPREG 8 302 #define FP_L ldc1 303 #define FP_S sdc1 304 #endif 305 306 /* 307 * standard callframe { 308 * register_t cf_args[4]; arg0 - arg3 (only on o32 and o64) 309 * register_t cf_pad[N]; o32/64 (N=0), n32 (N=1) n64 (N=1) 310 * register_t cf_gp; global pointer (only on n32 and n64) 311 * register_t cf_sp; frame pointer 312 * register_t cf_ra; return address 313 * }; 314 */ 315 #if defined(__mips_o32) || defined(__mips_o64) 316 #define CALLFRAME_SIZ (SZREG * (4 + 2)) 317 #define CALLFRAME_S0 0 318 #elif defined(__mips_n32) || defined(__mips_n64) 319 #define CALLFRAME_SIZ (SZREG * 4) 320 #define CALLFRAME_S0 (CALLFRAME_SIZ - 4 * SZREG) 321 #endif 322 #ifndef _KERNEL 323 #define CALLFRAME_GP (CALLFRAME_SIZ - 3 * SZREG) 324 #endif 325 #define CALLFRAME_SP (CALLFRAME_SIZ - 2 * SZREG) 326 #define CALLFRAME_RA (CALLFRAME_SIZ - 1 * SZREG) 327 328 /* 329 * While it would be nice to be compatible with the SGI 330 * REG_L and REG_S macros, because they do not take parameters, it 331 * is impossible to use them with the _MIPS_SIM_ABIX32 model. 332 * 333 * These macros hide the use of mips3 instructions from the 334 * assembler to prevent the assembler from generating 64-bit style 335 * ABI calls. 336 */ 337 #ifdef __mips_o32 338 #define PTR_ADD add 339 #define PTR_ADDI addi 340 #define PTR_ADDU addu 341 #define PTR_ADDIU addiu 342 #define PTR_SUB subu 343 #define PTR_SUBI subi 344 #define PTR_SUBU subu 345 #define PTR_SUBIU subu 346 #define PTR_L lw 347 #define PTR_LA la 348 #define PTR_S sw 349 #define PTR_SLL sll 350 #define PTR_SLLV sllv 351 #define PTR_SRL srl 352 #define PTR_SRLV srlv 353 #define PTR_SRA sra 354 #define PTR_SRAV srav 355 #define PTR_LL ll 356 #define PTR_SC sc 357 #define PTR_WORD .word 358 #define PTR_SCALESHIFT 2 359 #else /* _MIPS_SZPTR == 64 */ 360 #define PTR_ADD dadd 361 #define PTR_ADDI daddi 362 #define PTR_ADDU daddu 363 #define PTR_ADDIU daddiu 364 #define PTR_SUB dsubu 365 #define PTR_SUBI dsubi 366 #define PTR_SUBU dsubu 367 #define PTR_SUBIU dsubu 368 #ifdef __mips_n32 369 #define PTR_L lw 370 #define PTR_LL ll 371 #define PTR_SC sc 372 #define PTR_S sw 373 #define PTR_SCALESHIFT 2 374 #define PTR_WORD .word 375 #else 376 #define PTR_L ld 377 #define PTR_LL lld 378 #define PTR_SC scd 379 #define PTR_S sd 380 #define PTR_SCALESHIFT 3 381 #define PTR_WORD .dword 382 #endif 383 #define PTR_LA dla 384 #define PTR_SLL dsll 385 #define PTR_SLLV dsllv 386 #define PTR_SRL dsrl 387 #define PTR_SRLV dsrlv 388 #define PTR_SRA dsra 389 #define PTR_SRAV dsrav 390 #endif /* _MIPS_SZPTR == 64 */ 391 392 #if _MIPS_SZINT == 32 393 #define INT_ADD add 394 #define INT_ADDI addi 395 #define INT_ADDU addu 396 #define INT_ADDIU addiu 397 #define INT_SUB subu 398 #define INT_SUBI subi 399 #define INT_SUBU subu 400 #define INT_SUBIU subu 401 #define INT_L lw 402 #define INT_LA la 403 #define INT_S sw 404 #define INT_SLL sll 405 #define INT_SLLV sllv 406 #define INT_SRL srl 407 #define INT_SRLV srlv 408 #define INT_SRA sra 409 #define INT_SRAV srav 410 #define INT_LL ll 411 #define INT_SC sc 412 #define INT_WORD .word 413 #define INT_SCALESHIFT 2 414 #else 415 #define INT_ADD dadd 416 #define INT_ADDI daddi 417 #define INT_ADDU daddu 418 #define INT_ADDIU daddiu 419 #define INT_SUB dsubu 420 #define INT_SUBI dsubi 421 #define INT_SUBU dsubu 422 #define INT_SUBIU dsubu 423 #define INT_L ld 424 #define INT_LA dla 425 #define INT_S sd 426 #define INT_SLL dsll 427 #define INT_SLLV dsllv 428 #define INT_SRL dsrl 429 #define INT_SRLV dsrlv 430 #define INT_SRA dsra 431 #define INT_SRAV dsrav 432 #define INT_LL lld 433 #define INT_SC scd 434 #define INT_WORD .dword 435 #define INT_SCALESHIFT 3 436 #endif 437 438 #if _MIPS_SZLONG == 32 439 #define LONG_ADD add 440 #define LONG_ADDI addi 441 #define LONG_ADDU addu 442 #define LONG_ADDIU addiu 443 #define LONG_SUB subu 444 #define LONG_SUBI subi 445 #define LONG_SUBU subu 446 #define LONG_SUBIU subu 447 #define LONG_L lw 448 #define LONG_LA la 449 #define LONG_S sw 450 #define LONG_SLL sll 451 #define LONG_SLLV sllv 452 #define LONG_SRL srl 453 #define LONG_SRLV srlv 454 #define LONG_SRA sra 455 #define LONG_SRAV srav 456 #define LONG_LL ll 457 #define LONG_SC sc 458 #define LONG_WORD .word 459 #define LONG_SCALESHIFT 2 460 #else 461 #define LONG_ADD dadd 462 #define LONG_ADDI daddi 463 #define LONG_ADDU daddu 464 #define LONG_ADDIU daddiu 465 #define LONG_SUB dsubu 466 #define LONG_SUBI dsubi 467 #define LONG_SUBU dsubu 468 #define LONG_SUBIU dsubu 469 #define LONG_L ld 470 #define LONG_LA dla 471 #define LONG_S sd 472 #define LONG_SLL dsll 473 #define LONG_SLLV dsllv 474 #define LONG_SRL dsrl 475 #define LONG_SRLV dsrlv 476 #define LONG_SRA dsra 477 #define LONG_SRAV dsrav 478 #define LONG_LL lld 479 #define LONG_SC scd 480 #define LONG_WORD .dword 481 #define LONG_SCALESHIFT 3 482 #endif 483 484 #if SZREG == 4 485 #define REG_L lw 486 #define REG_S sw 487 #define REG_LI li 488 #define REG_ADDU addu 489 #define REG_SLL sll 490 #define REG_SLLV sllv 491 #define REG_SRL srl 492 #define REG_SRLV srlv 493 #define REG_SRA sra 494 #define REG_SRAV srav 495 #define REG_LL ll 496 #define REG_SC sc 497 #define REG_SCALESHIFT 2 498 #else 499 #define REG_L ld 500 #define REG_S sd 501 #define REG_LI dli 502 #define REG_ADDU daddu 503 #define REG_SLL dsll 504 #define REG_SLLV dsllv 505 #define REG_SRL dsrl 506 #define REG_SRLV dsrlv 507 #define REG_SRA dsra 508 #define REG_SRAV dsrav 509 #define REG_LL lld 510 #define REG_SC scd 511 #define REG_SCALESHIFT 3 512 #endif 513 514 #if (MIPS1 + MIPS2) > 0 515 #define NOP_L nop 516 #else 517 #define NOP_L /* nothing */ 518 #endif 519 520 #if defined(MULTIPROCESSOR) 521 #if defined(MIPS64_OCTEON) 522 /* early cnMIPS have erratum which means 2 */ 523 #define LLSCSYNC sync 4; sync 4 524 #define SYNC sync 4 /* sync 4 == syncw - sync all writes */ 525 #define BDSYNC sync 4 /* sync 4 == syncw - sync all writes */ 526 #else 527 #define LLSCSYNC /* nothing (something?) */ 528 #define SYNC sync 529 #define BDSYNC sync 530 #endif 531 #else 532 #define LLSCSYNC /* nothing */ 533 #define SYNC /* nothing */ 534 #define BDSYNC nop 535 #endif /* defined(MULTIPROCESSOR) */ 536 537 538 /* CPU dependent hook for cp0 load delays */ 539 #if defined(MIPS1) || defined(MIPS2) || defined(MIPS3) 540 #define MFC0_HAZARD sll $0,$0,1 /* super scalar nop */ 541 #else 542 #define MFC0_HAZARD /* nothing */ 543 #endif 544 545 #if _MIPS_ISA == _MIPS_ISA_MIPS1 || _MIPS_ISA == _MIPS_ISA_MIPS2 || \ 546 _MIPS_ISA == _MIPS_ISA_MIPS32 547 #define MFC0 mfc0 548 #define MTC0 mtc0 549 #endif 550 #if _MIPS_ISA == _MIPS_ISA_MIPS3 || _MIPS_ISA == _MIPS_ISA_MIPS4 || \ 551 _MIPS_ISA == _MIPS_ISA_MIPS64 552 #define MFC0 dmfc0 553 #define MTC0 dmtc0 554 #endif 555 556 #if defined(__mips_o32) || defined(__mips_o64) 557 558 #ifdef __mips_abicalls 559 #define CPRESTORE(r) .cprestore r 560 #define CPLOAD(r) .cpload r 561 #else 562 #define CPRESTORE(r) /* not needed */ 563 #define CPLOAD(r) /* not needed */ 564 #endif 565 566 #define SETUP_GP \ 567 .set push; \ 568 .set noreorder; \ 569 .cpload t9; \ 570 .set pop 571 #define SETUP_GPX(r) \ 572 .set push; \ 573 .set noreorder; \ 574 move r,ra; /* save old ra */ \ 575 bal 7f; \ 576 nop; \ 577 7: .cpload ra; \ 578 move ra,r; \ 579 .set pop 580 #define SETUP_GPX_L(r,lbl) \ 581 .set push; \ 582 .set noreorder; \ 583 move r,ra; /* save old ra */ \ 584 bal lbl; \ 585 nop; \ 586 lbl: .cpload ra; \ 587 move ra,r; \ 588 .set pop 589 #define SAVE_GP(x) .cprestore x 590 591 #define SETUP_GP64(a,b) /* n32/n64 specific */ 592 #define SETUP_GP64_R(a,b) /* n32/n64 specific */ 593 #define SETUP_GPX64(a,b) /* n32/n64 specific */ 594 #define SETUP_GPX64_L(a,b,c) /* n32/n64 specific */ 595 #define RESTORE_GP64 /* n32/n64 specific */ 596 #define USE_ALT_CP(a) /* n32/n64 specific */ 597 #endif /* __mips_o32 || __mips_o64 */ 598 599 #if defined(__mips_o32) || defined(__mips_o64) 600 #define REG_PROLOGUE .set push 601 #define REG_EPILOGUE .set pop 602 #endif 603 #if defined(__mips_n32) || defined(__mips_n64) 604 #define REG_PROLOGUE .set push ; .set mips3 605 #define REG_EPILOGUE .set pop 606 #endif 607 608 #if defined(__mips_n32) || defined(__mips_n64) 609 #define SETUP_GP /* o32 specific */ 610 #define SETUP_GPX(r) /* o32 specific */ 611 #define SETUP_GPX_L(r,lbl) /* o32 specific */ 612 #define SAVE_GP(x) /* o32 specific */ 613 #define SETUP_GP64(a,b) .cpsetup $25, a, b 614 #define SETUP_GPX64(a,b) \ 615 .set push; \ 616 move b,ra; \ 617 .set noreorder; \ 618 bal 7f; \ 619 nop; \ 620 7: .set pop; \ 621 .cpsetup ra, a, 7b; \ 622 move ra,b 623 #define SETUP_GPX64_L(a,b,c) \ 624 .set push; \ 625 move b,ra; \ 626 .set noreorder; \ 627 bal c; \ 628 nop; \ 629 c: .set pop; \ 630 .cpsetup ra, a, c; \ 631 move ra,b 632 #define RESTORE_GP64 .cpreturn 633 #define USE_ALT_CP(a) .cplocal a 634 #endif /* __mips_n32 || __mips_n64 */ 635 636 /* 637 * The DYNAMIC_STATUS_MASK option adds an additional masking operation 638 * when updating the hardware interrupt mask in the status register. 639 * 640 * This is useful for platforms that need to at run-time mask 641 * interrupts based on motherboard configuration or to handle 642 * slowly clearing interrupts. 643 * 644 * XXX this is only currently implemented for mips3. 645 */ 646 #ifdef MIPS_DYNAMIC_STATUS_MASK 647 #define DYNAMIC_STATUS_MASK(sr,scratch) \ 648 lw scratch, mips_dynamic_status_mask; \ 649 and sr, sr, scratch 650 651 #define DYNAMIC_STATUS_MASK_TOUSER(sr,scratch1) \ 652 ori sr, (MIPS_INT_MASK | MIPS_SR_INT_IE); \ 653 DYNAMIC_STATUS_MASK(sr,scratch1) 654 #else 655 #define DYNAMIC_STATUS_MASK(sr,scratch) 656 #define DYNAMIC_STATUS_MASK_TOUSER(sr,scratch1) 657 #endif 658 659 /* See lock_stubs.S. */ 660 #define LOG2_MIPS_LOCK_RAS_SIZE 8 661 #define MIPS_LOCK_RAS_SIZE 256 /* 16 bytes left over */ 662 663 #define CPUVAR(off) _C_LABEL(cpu_info_store)+__CONCAT(CPU_INFO_,off) 664 665 #endif /* _MIPS_ASM_H */ 666
Indexes created Tue Sep 23 21:09:50 GMT 2025