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History log of /src/sys/arch/mips/include/asm.h
RevisionDateAuthorComments
 1.77  06-Jan-2025  martin PR 58960: fix misunderstanding in semantic and provide both the original
id string as well as _NETBSD_REVISIONID.
Do not rely on string concatenation in the inline assembler, use .ascii
and .asciz for individual string parts instead.
 1.76  04-Jan-2025  martin PR 58960: mips/asm.h: Respect NETBSD_REVISIONID.
 1.75  14-Sep-2023  rin branches: 1.75.6;
mips: Add initial support to gprof(1) for n64 userland

Use gp relative call for _mcount().

Stop using macro name MCOUNT as well for clarity. It has nothing to
do with one provided by <machine/profile.h>.

Now, gprof(1) works just fine for C programs. On the other hand, some
C++ profiling tests of ATF fail as partially observed for n32.

More C++ profile tests become broken for GCC12 in comparison to GCC10.
Something needs to be adjusted for us, or GCC, or both.
 1.74  23-Feb-2023  riastradh mips: Add missing barriers in cpu_switchto.

Details in comments.

PR kern/57240

XXX pullup-8
XXX pullup-9
XXX pullup-10
 1.73  20-Feb-2023  riastradh mips/asm.h: Make membar macros conditional on MULTIPROCESSOR.

For !MULTIPROCESSOR, define them to be empty or nop as appropriate.
 1.72  13-Feb-2023  riastradh mips/asm.h: Cite source for Cavium sync plunger business.
 1.71  21-Apr-2022  riastradh branches: 1.71.4;
mips/cavium: Take advantage of Octeon's guaranteed r/rw ordering.
 1.70  09-Apr-2022  riastradh mips/rmi: Hack to get XLSATX64.MP kernel building again.

Using <mips/asm.h> in a .c file is kinda grody but CALLFRAME_SIZ
doesn't seem to be defined anywhere else. Not sure how this was ever
supposed to work...
 1.69  27-Feb-2022  riastradh mips: Redefine LLSCSYNC as empty on non-Octeon MP.

This change deletes memory barriers on non-Octeon MP. However, all
the appropriate acquire and release barriers are already used in
mutex stubs, and no barriers are needed in atomic_* unless we set
__HAVE_ATOMIC_AS_MEMBAR which we don't on MIPS. So this should be
safe.

Unclear whether we need this even on Octeon -- don't have a clear
reference on why it's here.
 1.68  27-Feb-2022  riastradh mips: Redefine BDSYNC as sync on Octeon, not syncw.

BDSYNC is used for membar_sync, which is supposed to be a full
sequential consistency barrier, which is not provided by syncw, so
this is necessary for correctness.

BDSYNC is not used for anything else, so this can't hurt performance,
except where it was necessary for correctness anyway or where the
semantic choice of membar_sync was too strong anyway.
 1.67  27-Feb-2022  riastradh mips: Omit needless SYNC in mutex_exit.

This change deletes a memory barrier. However, it should be safe:
The semantic requirement for this is already provided by the SYNC_REL
above, before the ll. And as currently defined, SYNC_REL is at least
as strong as SYNC, so this change can't hurt correctness on its own
(barring CPU errata, which would apply to other users of SYNC_REL and
can be addressed in the definition of SYNC_REL).

Later, perhaps we can relax SYNC_REL to syncw on Octeon if we prove
that it is correct (e.g., if Octeon follows the SPARCv9 partial store
order semantics).

Nix now-unused SYNC macro in asm.h.
 1.66  27-Feb-2022  riastradh mips: Membar audit.

This change should be safe because it doesn't remove or weaken any
memory barriers, but does add, clarify, or strengthen barriers.

Goals:

- Make sure mutex_enter/exit and mutex_spin_enter/exit have
acquire/release semantics.

- New macros make maintenance easier and purpose clearer:

. SYNC_ACQ is for load-before-load/store barrier, and BDSYNC_ACQ
for a branch delay slot -- currently defined as plain sync for MP
and nothing, or nop, for UP; thus it is no weaker than SYNC and
BDSYNC as currently defined, which is syncw on Octeon, plain sync
on non-Octeon MP, and nothing/nop on UP.

It is not clear to me whether load-then-syncw or ll/sc-then-syncw
or even bare load provides load-acquire semantics on Octeon -- if
no, this will fix bugs; if yes (like it is on SPARC PSO), we can
relax SYNC_ACQ to be syncw or nothing later.

. SYNC_REL is for load/store-before-store barrier -- currently
defined as plain sync for MP and nothing for UP.

It is not clear to me whether syncw-then-store is enough for
store-release on Octeon -- if no, we can leave this as is; if
yes, we can relax SYNC_REL to be syncw on Octeon.

. SYNC_PLUNGER is there to flush clogged Cavium store buffers, and
BDSYNC_PLUNGER for a branch delay slot -- syncw on Octeon,
nothing or nop on non-Octeon.

=> This is not necessary (or, as far as I'm aware, sufficient)
for acquire semantics -- it serves only to flush store buffers
where stores might otherwise linger for hundreds of thousands
of cycles, which would, e.g., cause spin locks to be held for
unreasonably long durations.

Newerish revisions of the MIPS ISA also have finer-grained sync
variants that could be plopped in here.

Mechanism:

Insert these barriers in the right places, replacing only those where
the definition is currently equivalent, so this change is safe.

- Replace #ifdef _MIPS_ARCH_OCTEONP / syncw / #endif at the end of
atomic_cas_* by SYNC_PLUNGER, which is `sync 4' (a.k.a. syncw) if
__OCTEON__ and empty otherwise.

=> From what I can tell, __OCTEON__ is defined in at least as many
contexts as _MIPS_ARCH_OCTEONP -- i.e., there are some Octeons
with no _MIPS_ARCH_OCTEONP, but I don't know if any of them are
relevant to us or ever saw the light of day outside Cavium; we
seem to buid with `-march=octeonp' so this is unlikely to make a
difference. If it turns out that we do care, well, now there's
a central place to make the distinction for sync instructions.

- Replace post-ll/sc SYNC by SYNC_ACQ in _atomic_cas_*, which are
internal kernel versions used in sys/arch/mips/include/lock.h where
it assumes they have load-acquire semantics. Should move this to
lock.h later, since we _don't_ define __HAVE_ATOMIC_AS_MEMBAR on
MIPS and so the extra barrier might be costly.

- Insert SYNC_REL before ll/sc, and replace post-ll/sc SYNC by
SYNC_ACQ, in _ucas_*, which is used without any barriers in futex
code and doesn't mention barriers in the man page so I have to
assume it is required to be a release/acquire barrier.

- Change BDSYNC to BDSYNC_ACQ in mutex_enter and mutex_spin_enter.
This is necessary to provide load-acquire semantics -- unclear if
it was provided already by syncw on Octeon, but it seems more
likely that either (a) no sync or syncw is needed at all, or (b)
syncw is not enough and sync is needed, since syncw is only a
store-before-store ordering barrier.

- Insert SYNC_REL before ll/sc in mutex_exit and mutex_spin_exit.
This is currently redundant with the SYNC already there, but
SYNC_REL more clearly identifies the necessary semantics in case we
want to define it differently on different systems, and having a
sync in the middle of an ll/sc is a bit weird and possibly not a
good idea, so I intend to (carefully) remove the redundant SYNC in
a later change.

- Change BDSYNC to BDSYNC_PLUNGER at the end of mutex_exit. This has
no semantic change right now -- it's syncw on Octeon, sync on
non-Octeon MP, nop on UP -- but we can relax it later to nop on
non-Cavium MP.

- Leave LLSCSYNC in for now -- it is apparently there for a Cavium
erratum, but I'm not sure what the erratum is, exactly, and I have
no reference for it. I suspect these can be safely removed, but we
might have to double up some other syncw instructions -- Linux uses
it only in store-release sequences, not at the head of every ll/sc.
 1.65  18-Feb-2021  simonb Add an abicalls version of asm mcount prologue. XXX not tested because
profiled programs fail to link, but fixes build. Thanks dholland@ for
help analysing this.

While here, rename _KERN_MCOUNT to _MIPS_ASM_MCOUNT - it's not kernel
specific.
 1.64  16-Feb-2021  simonb Working kernel profiling for n32/n64:
- Different MCOUNT and _KERN_MCOUNT macros for n32/n64.
- Don't profile mipsXX_lwp_trampoline().
- Allow a few new instructions in the stub fixups.
 1.63  04-Feb-2021  skrll Use t9 instead of $25 in the SETUP_GP64 macro to hopefully make things
a bit clearer. Same libc binary after.
 1.62  26-Sep-2020  simonb branches: 1.62.2;
Add EXPORT_OBJECT - export definition of symbol of symbol type Object,
visible to ksyms(4) address search.
 1.61  12-Aug-2020  skrll Provide assmebler versions of BITS(3) macros. These are only good for
32 bit masks
 1.60  10-Aug-2020  skrll More SYNC centralisation
 1.59  09-Aug-2020  skrll Use compiler defines to determine which LLSCSYNC, et al
to provide.

This should fix mips builds.
 1.58  06-Aug-2020  skrll Centralise SYNC/BDSYNC in asm.h and introduce a new LLCSCSYNC and use it
before any ll/sc sequences.

Define LLSCSYNC as syncw; syncw for cnMIPS - issue two as early cnMIPS
has errat{um,a} that means the first can fail.
 1.57  26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.56  17-Apr-2020  joerg Mark the .ident section as mergable string section to avoid redundant
entries.
 1.55  04-Sep-2018  mrg branches: 1.55.4; 1.55.10;
mark STATIC_NESTED_NOPROFILE() functions as functions.
 1.54  25-Feb-2017  joerg branches: 1.54.6; 1.54.12; 1.54.14;
Switch from __ABICALLS__ to __mips_abicalls like upstream GCC does in
the generic MIPS target logic.
 1.53  11-Nov-2016  maya branches: 1.53.2;
switch mfc0_hazard to be superscalar nop, some mips3 are superscalar
and need this to do the right thing
 1.52  09-Nov-2016  maya Move MFC0_HAZARD definition to asm.h instead of defining it twice
 1.51  13-Aug-2016  skrll Move the NOP_L macro into asm.h
 1.50  13-Aug-2016  skrll Trailing whitespace
 1.49  11-Jul-2016  matt branches: 1.49.2;
Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch
 1.48  17-Sep-2014  joerg branches: 1.48.2;
Normal spelling is .asciz, so use that on MIPS too.
 1.47  30-May-2014  joerg Drop undocumented and redundant 0 argument to .ent.
 1.46  10-Nov-2011  joerg branches: 1.46.10; 1.46.24;
Don't redefine _C_LABEL.
 1.45  01-Jul-2011  matt branches: 1.45.2;
xxx_SUB macros should use a variant of subu, not add
 1.44  20-Feb-2011  matt Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU
 1.43  20-Dec-2010  joerg branches: 1.43.2; 1.43.4;
Consistently use .gnu.warning with .pushsectio and .popsection on all
architectures instead of obsolete STABS frames for linker warnings.
 1.42  07-Jul-2010  chs implement ucas_* for mips.
 1.41  14-Dec-2009  matt branches: 1.41.2; 1.41.4;
Merge from matt-nb5-mips64
Merge mips-specific arch files.
 1.40  17-Oct-2007  garbled branches: 1.40.20; 1.40.38;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.
 1.39  17-May-2007  yamt branches: 1.39.2; 1.39.10;
merge yamt-idlelwp branch. asked by core@. some ports still needs work.

from doc/BRANCHES:

idle lwp, and some changes depending on it.

1. separate context switching and thread scheduling.
(cf. gmcgarry_ctxsw)
2. implement idle lwp.
3. clean up related MD/MI interfaces.
4. make scheduler(s) modular.
 1.38  09-Feb-2007  ad branches: 1.38.2; 1.38.6; 1.38.8; 1.38.14;
Merge newlock2 to head.
 1.37  20-Jan-2006  christos branches: 1.37.18;
Add a STRONG_ALIAS macro
 1.36  11-Dec-2005  christos branches: 1.36.2;
merge ktrace-lwp.
 1.35  07-Aug-2003  agc branches: 1.35.16;
Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.
 1.34  27-Jun-2003  simonb branches: 1.34.2;
Add STATIC_LEAF and STATIC_XLEAF macros, ala the alpha port.
 1.33  05-Jun-2002  simonb Remove an ELF-related comment that isn't needed any more.
 1.32  13-May-2002  simonb branches: 1.32.2;
Oops, remove an #endif leftover from the previous change.
 1.31  13-May-2002  simonb All MIPS ports have been ELF for a long time (most since they were
created); remove non-ELF assembly support.
 1.30  05-Mar-2002  simonb Include <machine/cdefs.h> to select 32/64bit APIs.
 1.29  14-Dec-2000  jeffs branches: 1.29.4; 1.29.8;
For MIPS software masking option, when returning to user mode apply
the mask to all interrupts to catch changes in the mask state faster.
Does not affect platforms w/o this option enabled.
 1.28  30-Aug-2000  jeffs Correct _KERN_MCOUNT restoration of $t9.
From Ethan Solomita (ethan@geocast.com).
 1.27  09-Aug-2000  jeffs Fix a bug in how .S routines call _mcount to allocate stack before
use. By Ethan Solomita (ethan@geocast.com).
 1.26  27-Jul-2000  cgd add nops after jals in PANIC and PRINTF. (these macros are often used in
code which has noreorder set, and they're not used with nops afterwards,
as is appropriate in that case, so put the nops in the macros.)
 1.25  25-Jul-2000  jeffs Add option to apply additional mask to the SR at run-time for MIPS3 platforms.
By default this is off, and only slightly changes the code to load SR when
a temp register is available. This can be used by the platform code to
handle slow to clear interrupts (our case) or to mask off any interrupt
any interrupt at run-time. This can be very useful for embedded platforms
that have less than desirable interrupt properties.
 1.24  23-Jun-2000  kleink Add a WEAK_ALIAS() macro.
 1.23  12-Jun-2000  castor branches: 1.23.2;
Profiling fixes from Ethan Solomita <ethan@geocast.com>.

Merge Kernel MCOUNT and user MCOUNT.

The earlier code which was inserted to call _mcount in profiling
assembler routines is busted badly. This gets it working with PIC
code and should work with any arbitrary assembler routine.
 1.22  24-Apr-1999  simonb branches: 1.22.2; 1.22.10;
Nuke register and remove trailling white space.
 1.21  01-Apr-1999  soda branches: 1.21.4;
do not include <machine/regdef.h>, but include <mips/regdef.h>,
requested by Matthias Drochner and Toru Nishimura.
 1.20  30-Mar-1999  soda - add _C_LABEL() to IMPORT(), to make this consistent with EXPORT().
- fix some oversight of previous my changes on defined(USE_AENT) or
!defined(__NO_LEADING_UNDERSCORES__) case.
 1.19  30-Mar-1999  soda - regdef.h is back, so use it.
- ALIAS() is not needed, use XLEAF() or XNESTED() instead
- use AENT() instead of .aent
- _END_LABEL() is not needed (and was wrong)
- define ALEAF(), NLEAF(), NON_LEAF(), NNON_LEAF() by
XLEAF(), LEAF_NONPROFILE(), NESTED(), NESTED_NONPROFILE()
 1.18  24-Feb-1999  drochner sync to [nisimura-pmax-wscons] version
(only change: include register definitions from regdef.h)
 1.17  16-Feb-1999  jonathan Add VECTOR() and VECTOR_END() macros for declaring exception-vector
code. Fold in <xxx>End names used to copy exception code to vector
locations. Use in mips3 locore code.
 1.16  31-Jan-1999  castor Remove genpubassym.cf stuff. The macro _MIPS_BSD_API allows selection of a
64-bit clean compilation model.
 1.15  14-Jan-1999  castor * Create mips_reg_t data type to allow register size to be
decoupled from long or int or long long. Define macros in asm.h to facilitate
choosing these on a port by port basis.

* Create <machine/pubassym.h> mechanism to allow jmp_buf structure size
to be calculated at system build time.

* Define _MIPS_BSD_SIM macro which specifies what calling style is appropritae
for the architecture. For 64-bit oriented systems set the Status Register
to allow 64-bit instructions.

* Remove UADDR related macros because kernel U structure is now mapped
normally.
* Separate cpu.h into cpu.h and cpuarch.h to keep things neat.
* Add support for QED 52xx processors
 1.14  02-Dec-1998  thorpej Implement WARN_REFERENCES().
 1.13  20-Jul-1997  jonathan branches: 1.13.10;
Don't emit ".set reorder ; .set noreorder" around mcount profiling
stubs if _LOCORE or _KERNEL are defined,. _LOCORE means we're
compiling locore. Locore assumes ".set noreorder" for the whole file.
 1.12  23-Jun-1997  jonathan Align to 8-byte boundary after ASMSTR(), for mips3.
 1.11  30-Nov-1996  jtc PROF -> GPROF
 1.10  13-Oct-1996  christos backout previous kprintf change
 1.9  11-Oct-1996  christos printf -> kprintf
 1.8  25-Mar-1996  jonathan Rename from pmax/include/machAsmDefs.h to mips/include/asm.h.
Update the include-idempotency preprocessor token to match.

References to machAsmDefs in vendor (sprite, 4.4bsd) headers left unchanged,
for historical accuracy.
 1.7  18-Jan-1995  mellon Support for alternate compilers and file formats
 1.6  15-Dec-1994  mycroft Make a new macro _C_LABEL(), which prepends an underscore to the argument unless
NO_UNDERSCORES is defined. Use it in the *LEAF() and END() macros.
 1.5  14-Nov-1994  dean Prepended underscores
 1.4  26-Oct-1994  cgd new RCS ID format.
 1.3  27-May-1994  glass bsd 4.4-lite pmax port as ported to NetBSD
 1.2  27-May-1994  glass upgrade to bsd 4.4-lite code base. only mod is rcsids
 1.1  12-Oct-1993  deraadt branches: 1.1.1;
Initial revision
 1.1.1.1  12-Oct-1993  deraadt pmax code from <ralphc@pyramid.com> & <rick@snowhite.cis.uoguelph.ca>
 1.13.10.3  06-Dec-1998  drochner pull up 1.14 - WARN_REFERENCES()
 1.13.10.2  30-Oct-1998  nisimura - Make pm.c monochrome-aware and compilable with UVM.
- Make trap.c compilable with UVM.
- Place #ifdef _KERNEL guard in cpu.h
- Make asm.h more MIPS standard-alike while retaining current definitions.
 1.13.10.1  15-Oct-1998  nisimura - cpuregs.h was modifed a bit, then renamed with cpuarch.h.
- mips_cpu.h has gone.
- CPU's register mnemonics in regdef.h is now a part of asm.h.
 1.21.4.1  21-Jun-1999  thorpej Sync w/ -current.
 1.22.10.1  22-Jun-2000  minoura Sync w/ netbsd-1-5-base.
 1.22.2.2  05-Jan-2001  bouyer Sync with HEAD
 1.22.2.1  20-Nov-2000  bouyer Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.
 1.23.2.2  07-Jun-2001  he Pull up revision 1.25 (requested by hubertf, reviewed by thorpej):
Implement power saving for RM5200 and RM7000 CPUs, as used in
e.g. Cobalt RaQ2.
 1.23.2.1  25-Jul-2000  kleink Pull up rev. 1.24 (approved by thorpej):
For ELF, add a WEAK_ALIAS() macro.
 1.29.8.2  20-Jun-2002  nathanw Catch up to -current.
 1.29.8.1  01-Apr-2002  nathanw Catch up to -current.
(CVS: It's not just a program. It's an adventure!)
 1.29.4.2  23-Jun-2002  jdolecek catch up with -current on kqueue branch
 1.29.4.1  16-Mar-2002  jdolecek Catch up with -current.
 1.32.2.1  14-Jul-2002  gehenna catch up with -current.
 1.34.2.3  21-Sep-2004  skrll Fix the sync with head I botched.
 1.34.2.2  18-Sep-2004  skrll Sync with HEAD.
 1.34.2.1  03-Aug-2004  skrll Sync with HEAD
 1.35.16.3  03-Sep-2007  yamt sync with head.
 1.35.16.2  26-Feb-2007  yamt sync with head.
 1.35.16.1  21-Jun-2006  yamt sync with head.
 1.36.2.1  01-Feb-2006  yamt sync with head.
 1.37.18.1  27-Jan-2007  ad Make mips systems work.
 1.38.14.1  22-May-2007  matt Update to HEAD.
 1.38.8.1  11-Jul-2007  mjf Sync with head.
 1.38.6.1  27-May-2007  ad Sync with head.
 1.38.2.1  18-Apr-2007  ad - Further adaptations to MIPS for the yamt-idlelwp branch.
- Make curlwp a register variable on MIPS.
 1.39.10.1  06-Nov-2007  matt sync with HEAD
 1.39.2.1  18-Jul-2007  matt Add PTR_L/PTR_S/ADDR_L/REGADD utility macros to make code portable between
o32/n32/n64.
 1.40.38.14  29-Apr-2011  matt Major merge to/from current.
Adds MIPS32/MIPS64 R2 support (24k, 74k, etc.) including COP0_USERLOCAL
Adds support for emulation of rdhwr $3,$29 instruction.
Major cleanup of SMP code. (stable on multi-core / single thread per core)
llsc locking code only used in MP capable kernels.
 1.40.38.13  24-Dec-2010  matt MIPS_LOCK_RAS_SIZE needs to be 256 since each RAS need 64 bytes and we can
have 4 of them.
 1.40.38.12  15-Feb-2010  matt Fix a comment.
 1.40.38.11  16-Jan-2010  matt Rework the exception code. All the exceptions (except for mips3_5900) are
now padded to 128 bytes each and placed in the right order so they can be
copied with one memcpy. This also allows us to branch to unused space space
since the relative locations will remain the same.

When leaving the exception vectors, k1 will now always contain the address
of CURLWP for that CPU. The rest of the exception code no longer needs (and
is not allowed to) to access CPUVAR(CURLWP).

kill outofworld and just let trap panic, if it can. Allow for sb1_subr.S
or rmixl_subr.S in the future. Fix TLB read/write code.
 1.40.38.10  15-Jan-2010  matt Get rid of most of the studly caps.
First to MULTIPROCESSOR support for pmap: move some pmap globals to cpu_info.
Define per-cpu ASID number spaces.
Remove some mips1/!mips1 difference in db_interface.c
Add mips32/64 knowledge to stacktrace.
 1.40.38.9  07-Sep-2009  matt Simplify PTR_ case (32 bit or 64 bit)
 1.40.38.8  05-Sep-2009  matt Add REG_LL/REG_SC/REG_ADDU
 1.40.38.7  03-Sep-2009  matt Don't use .set noorder/.set reorder.
instead use .set push; .set noreorder; .set pop
This will preserve noorder
 1.40.38.6  21-Aug-2009  matt For now use old callframe defs for O32 to reduce spurious code gen
differences make real differences easier to spot.
 1.40.38.5  20-Aug-2009  matt Add XXX_WORD for INT and LONG.
Use PTR_LA in the PANIC macro.
 1.40.38.4  19-Aug-2009  matt Add XXX_SCALESHIFT for all types, not just PTR
REG_PROLOGUE/REG_EPILOGUE cleanup.
 1.40.38.3  18-Aug-2009  matt Fix .cpsetup use $25 instead of $t9.
kill FPST/FPLD and use FP_S/FP_L which match INT_S/PTR_S/REG_S ...
 1.40.38.2  18-Aug-2009  uebayasi Provide FP_L / FP_S as aliases of FPLD / FPST. Fix build.
 1.40.38.1  16-Aug-2009  matt Completely rework to support multiple ABIs. Includes macros/ops to make
writing ABI independent assembly much easier. Add macros to handle PIC
for N32/N64 as well as O32/O64.
 1.40.20.2  11-Aug-2010  yamt sync with head.
 1.40.20.1  11-Mar-2010  yamt sync with head
 1.41.4.1  05-Mar-2011  rmind sync with head
 1.41.2.1  17-Aug-2010  uebayasi Sync with HEAD.
 1.43.4.1  05-Mar-2011  bouyer Sync with HEAD
 1.43.2.1  06-Jun-2011  jruoho Sync with HEAD.
 1.45.2.1  10-Nov-2011  yamt sync with head
 1.46.24.1  10-Aug-2014  tls Rebase.
 1.46.10.2  03-Dec-2017  jdolecek update from HEAD
 1.46.10.1  20-Aug-2014  tls Rebase to HEAD as of a few days ago.
 1.48.2.3  28-Aug-2017  skrll Sync with HEAD
 1.48.2.2  05-Dec-2016  skrll Sync with HEAD
 1.48.2.1  05-Oct-2016  skrll Sync with HEAD
 1.49.2.2  20-Mar-2017  pgoyette Sync with HEAD
 1.49.2.1  07-Jan-2017  pgoyette Sync with HEAD. (Note that most of these changes are simply $NetBSD$
tag issues.)
 1.53.2.1  21-Apr-2017  bouyer Sync with HEAD
 1.54.14.2  21-Apr-2020  martin Sync with HEAD
 1.54.14.1  10-Jun-2019  christos Sync with HEAD
 1.54.12.1  06-Sep-2018  pgoyette Sync with HEAD

Resolve a couple of conflicts (result of the uimin/uimax changes)
 1.54.6.2  01-Aug-2023  martin Apply patch, requested by riastradh in ticket #1859:

sys/arch/mips/include/asm.h (apply patch)

Additional build fix for mips1 (and mips2?)
(patch taken from [pullup-9 #1676])
 1.54.6.1  31-Jul-2023  martin Pull up following revision(s) (requested by riastradh in ticket #1859):

sys/arch/ia64/ia64/vm_machdep.c: revision 1.18
sys/arch/powerpc/powerpc/locore_subr.S: revision 1.67
sys/arch/aarch64/aarch64/locore.S: revision 1.91
sys/arch/mips/include/asm.h: revision 1.74
sys/arch/hppa/include/cpu.h: revision 1.13
sys/arch/arm/arm/armv6_start.S: revision 1.38
(applied also to sys/arch/arm/cortex/a9_mpsubr.S,
sys/arch/arm/cortex/a9_mpsubr.S,
sys/arch/arm/cortex/cortex_init.S)
sys/arch/evbmips/ingenic/cpu_startup.S: revision 1.2
sys/arch/mips/mips/locore.S: revision 1.229
sys/arch/alpha/include/asm.h: revision 1.45
(applied to sys/arch/alpha/alpha/multiproc.s)
sys/arch/sparc64/sparc64/locore.s: revision 1.432
sys/arch/vax/vax/subr.S: revision 1.42
sys/arch/mips/mips/locore_mips3.S: revision 1.116
sys/arch/ia64/ia64/machdep.c: revision 1.44
sys/arch/arm/arm32/cpuswitch.S: revision 1.106
sys/arch/sparc/sparc/locore.s: revision 1.284
(all via patch)

aarch64: Add missing barriers in cpu_switchto.
Details in comments.

Note: This is a conservative change that inserts a barrier where
there was a comment saying none is needed, which is probably correct.
The goal of this change is to systematically add barriers to be
confident in correctness; subsequent changes may remove some bariers,
as an optimization, with an explanation of why each barrier is not
needed.

PR kern/57240

alpha: Add missing barriers in cpu_switchto.
Details in comments.

arm32: Add missing barriers in cpu_switchto.
Details in comments.

hppa: Add missing barriers in cpu_switchto.
Not sure hppa has ever had working MULTIPROCESSOR, so maybe no
pullups needed?

ia64: Add missing barriers in cpu_switchto.
(ia64 has never really worked, so no pullups needed, right?)

mips: Add missing barriers in cpu_switchto.
Details in comments.

powerpc: Add missing barriers in cpu_switchto.
Details in comments.

sparc: Add missing barriers in cpu_switchto.

sparc64: Add missing barriers in cpu_switchto.
Details in comments.

vax: Note where cpu_switchto needs barriers.

Not sure vax has ever had working MULTIPROCESSOR, though, and I'm not
even sure how to spell store-before-load barriers on VAX, so no
functional change for now.
 1.55.10.1  20-Apr-2020  bouyer Sync with HEAD
 1.55.4.2  01-Aug-2023  martin Apply patch, requested by riastradh in ticket #1676:

sys/arch/mips/include/asm.h (apply patch)

Additional build fix for mips1 (and mips2?)
 1.55.4.1  31-Jul-2023  martin Pull up following revision(s) (requested by riastradh in ticket #1676):

sys/arch/ia64/ia64/vm_machdep.c: revision 1.18
sys/arch/powerpc/powerpc/locore_subr.S: revision 1.67
sys/arch/aarch64/aarch64/locore.S: revision 1.91
sys/arch/mips/include/asm.h: revision 1.74
sys/arch/hppa/include/cpu.h: revision 1.13
sys/arch/arm/arm/armv6_start.S: revision 1.38
sys/arch/evbmips/ingenic/cpu_startup.S: revision 1.2
sys/arch/mips/mips/locore.S: revision 1.229
sys/arch/aarch64/aarch64/cpuswitch.S: revision 1.40
sys/arch/alpha/include/asm.h: revision 1.45
sys/arch/sparc64/sparc64/locore.s: revision 1.432
sys/arch/vax/vax/subr.S: revision 1.42
sys/arch/mips/mips/locore_mips3.S: revision 1.116
sys/arch/ia64/ia64/machdep.c: revision 1.44
sys/arch/arm/arm32/cpuswitch.S: revision 1.106
sys/arch/sparc/sparc/locore.s: revision 1.284
(all via patch)

aarch64: Add missing barriers in cpu_switchto.
Details in comments.

Note: This is a conservative change that inserts a barrier where
there was a comment saying none is needed, which is probably correct.
The goal of this change is to systematically add barriers to be
confident in correctness; subsequent changes may remove some bariers,
as an optimization, with an explanation of why each barrier is not
needed.

PR kern/57240

alpha: Add missing barriers in cpu_switchto.
Details in comments.

arm32: Add missing barriers in cpu_switchto.
Details in comments.

hppa: Add missing barriers in cpu_switchto.
Not sure hppa has ever had working MULTIPROCESSOR, so maybe no
pullups needed?

ia64: Add missing barriers in cpu_switchto.
(ia64 has never really worked, so no pullups needed, right?)

mips: Add missing barriers in cpu_switchto.
Details in comments.

powerpc: Add missing barriers in cpu_switchto.
Details in comments.

sparc: Add missing barriers in cpu_switchto.

sparc64: Add missing barriers in cpu_switchto.
Details in comments.

vax: Note where cpu_switchto needs barriers.

Not sure vax has ever had working MULTIPROCESSOR, though, and I'm not
even sure how to spell store-before-load barriers on VAX, so no
functional change for now.
 1.62.2.1  03-Apr-2021  thorpej Sync with HEAD.
 1.71.4.1  31-Jul-2023  martin Pull up following revision(s) (requested by riastradh in ticket #264):

sys/arch/ia64/ia64/vm_machdep.c: revision 1.18
sys/arch/powerpc/powerpc/locore_subr.S: revision 1.67
sys/arch/aarch64/aarch64/locore.S: revision 1.91
sys/arch/mips/include/asm.h: revision 1.74
sys/arch/hppa/include/cpu.h: revision 1.13
sys/arch/arm/arm/armv6_start.S: revision 1.38
sys/arch/evbmips/ingenic/cpu_startup.S: revision 1.2
sys/arch/mips/mips/locore.S: revision 1.229
sys/arch/aarch64/aarch64/cpuswitch.S: revision 1.40
sys/arch/alpha/include/asm.h: revision 1.45
sys/arch/sparc64/sparc64/locore.s: revision 1.432
sys/arch/vax/vax/subr.S: revision 1.42
sys/arch/mips/mips/locore_mips3.S: revision 1.116
sys/arch/riscv/riscv/cpu_switch.S: revision 1.3
sys/arch/ia64/ia64/machdep.c: revision 1.44
sys/arch/arm/arm32/cpuswitch.S: revision 1.106
sys/arch/sparc/sparc/locore.s: revision 1.284

aarch64: Add missing barriers in cpu_switchto.
Details in comments.

Note: This is a conservative change that inserts a barrier where
there was a comment saying none is needed, which is probably correct.
The goal of this change is to systematically add barriers to be
confident in correctness; subsequent changes may remove some bariers,
as an optimization, with an explanation of why each barrier is not
needed.

PR kern/57240

alpha: Add missing barriers in cpu_switchto.
Details in comments.

arm32: Add missing barriers in cpu_switchto.
Details in comments.

hppa: Add missing barriers in cpu_switchto.
Not sure hppa has ever had working MULTIPROCESSOR, so maybe no
pullups needed?

ia64: Add missing barriers in cpu_switchto.
(ia64 has never really worked, so no pullups needed, right?)

mips: Add missing barriers in cpu_switchto.
Details in comments.

powerpc: Add missing barriers in cpu_switchto.
Details in comments.

riscv: Add missing barriers in cpu_switchto.
Details in comments.

sparc: Add missing barriers in cpu_switchto.

sparc64: Add missing barriers in cpu_switchto.
Details in comments.

vax: Note where cpu_switchto needs barriers.

Not sure vax has ever had working MULTIPROCESSOR, though, and I'm not
even sure how to spell store-before-load barriers on VAX, so no
functional change for now.
 1.75.6.1  02-Aug-2025  perseant Sync with HEAD

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