asm.h revision 1.76
1 /* $NetBSD: asm.h,v 1.76 2025/01/04 19:29:44 martin Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)machAsmDefs.h 8.1 (Berkeley) 6/10/93 35 */ 36 37 /* 38 * machAsmDefs.h -- 39 * 40 * Macros used when writing assembler programs. 41 * 42 * Copyright (C) 1989 Digital Equipment Corporation. 43 * Permission to use, copy, modify, and distribute this software and 44 * its documentation for any purpose and without fee is hereby granted, 45 * provided that the above copyright notice appears in all copies. 46 * Digital Equipment Corporation makes no representations about the 47 * suitability of this software for any purpose. It is provided "as is" 48 * without express or implied warranty. 49 * 50 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAsmDefs.h, 51 * v 1.2 89/08/15 18:28:24 rab Exp SPRITE (DECWRL) 52 */ 53 54 #ifndef _MIPS_ASM_H 55 #define _MIPS_ASM_H 56 57 #include <sys/cdefs.h> /* for API selection */ 58 #include <mips/regdef.h> 59 60 #if defined(_KERNEL_OPT) 61 #include "opt_gprof.h" 62 #include "opt_multiprocessor.h" 63 #endif 64 65 #ifdef __ASSEMBLER__ 66 #define __BIT(n) (1 << (n)) 67 #define __BITS(hi,lo) ((~((~0)<<((hi)+1)))&((~0)<<(lo))) 68 69 #define __LOWEST_SET_BIT(__mask) ((((__mask) - 1) & (__mask)) ^ (__mask)) 70 #define __SHIFTOUT(__x, __mask) (((__x) & (__mask)) / __LOWEST_SET_BIT(__mask)) 71 #define __SHIFTIN(__x, __mask) ((__x) * __LOWEST_SET_BIT(__mask)) 72 #endif /* __ASSEMBLER__ */ 73 74 #ifndef GPROF 75 #define _MIPS_ASM_MCOUNT(x) 76 #else 77 /* 78 * Define -pg profile entry code. 79 * Must always be noreorder, must never use a macro instruction. 80 */ 81 #if defined(__mips_o32) /* Old 32-bit ABI */ 82 /* 83 * The old ABI version must also decrement two less words off the 84 * stack and the final addiu to t9 must always equal the size of this 85 * _MIPS_ASM_MCOUNT. 86 */ 87 #define _MIPS_ASM_MCOUNT(x) \ 88 .set push; \ 89 .set noreorder; \ 90 .set noat; \ 91 subu sp,16; \ 92 sw t9,12(sp); \ 93 move AT,ra; \ 94 lui t9,%hi(_mcount); \ 95 addiu t9,t9,%lo(_mcount); \ 96 jalr t9; \ 97 nop; \ 98 lw t9,4(sp); \ 99 addiu sp,8; \ 100 addiu t9,40; \ 101 .set pop; 102 #elif defined(__mips_o64) /* Old 64-bit ABI */ 103 # error yeahnah 104 #else /* New (n32/n64) ABI */ 105 /* 106 * The new ABI version just needs to put the return address in AT and 107 * call _mcount(). For the no abicalls case, skip the reloc dance. 108 */ 109 #ifdef __mips_abicalls 110 #if defined(__mips_n32) /* n32 */ 111 #define _MIPS_ASM_MCOUNT(x) \ 112 .set push; \ 113 .set noreorder; \ 114 .set noat; \ 115 subu sp,16; \ 116 sw t9,8(sp); \ 117 move AT,ra; \ 118 lui t9,%hi(_mcount); \ 119 addiu t9,t9,%lo(_mcount); \ 120 jalr t9; \ 121 nop; \ 122 lw t9,8(sp); \ 123 addiu sp,16; \ 124 .set pop; 125 #else /* n64 */ 126 #define _MIPS_ASM_MCOUNT(x) \ 127 .set push; \ 128 .set noreorder; \ 129 .set noat; \ 130 dsubu sp,16; \ 131 sd gp,0(sp); \ 132 sd t9,8(sp); \ 133 move AT,ra; \ 134 lui gp,%hi(%neg(%gp_rel(x))); \ 135 daddiu gp,%lo(%neg(%gp_rel(x))); \ 136 daddu gp,gp,t9; \ 137 ld t9,%call16(_mcount)(gp); \ 138 jalr t9; \ 139 nop; \ 140 ld gp,0(sp); \ 141 ld t9,8(sp); \ 142 daddiu sp,16; \ 143 .set pop; 144 #endif 145 #else /* !__mips_abicalls */ 146 #define _MIPS_ASM_MCOUNT(x) \ 147 .set push; \ 148 .set noreorder; \ 149 .set noat; \ 150 move AT,ra; \ 151 jal _mcount; \ 152 nop; \ 153 .set pop; 154 #endif /* !__mips_abicalls */ 155 #endif /* n32/n64 */ 156 #endif /* GPROF */ 157 158 #ifdef USE_AENT 159 #define AENT(x) \ 160 .aent x, 0 161 #else 162 #define AENT(x) 163 #endif 164 165 /* 166 * WEAK_ALIAS: create a weak alias. 167 */ 168 #define WEAK_ALIAS(alias,sym) \ 169 .weak alias; \ 170 alias = sym 171 /* 172 * STRONG_ALIAS: create a strong alias. 173 */ 174 #define STRONG_ALIAS(alias,sym) \ 175 .globl alias; \ 176 alias = sym 177 178 /* 179 * WARN_REFERENCES: create a warning if the specified symbol is referenced. 180 */ 181 #define WARN_REFERENCES(sym,msg) \ 182 .pushsection __CONCAT(.gnu.warning.,sym); \ 183 .ascii msg; \ 184 .popsection 185 186 /* 187 * STATIC_LEAF_NOPROFILE 188 * No profilable local leaf routine. 189 */ 190 #define STATIC_LEAF_NOPROFILE(x) \ 191 .ent _C_LABEL(x); \ 192 _C_LABEL(x): ; \ 193 .frame sp, 0, ra 194 195 /* 196 * LEAF_NOPROFILE 197 * No profilable leaf routine. 198 */ 199 #define LEAF_NOPROFILE(x) \ 200 .globl _C_LABEL(x); \ 201 STATIC_LEAF_NOPROFILE(x) 202 203 /* 204 * STATIC_LEAF 205 * Declare a local leaf function. 206 */ 207 #define STATIC_LEAF(x) \ 208 STATIC_LEAF_NOPROFILE(x); \ 209 _MIPS_ASM_MCOUNT(x) 210 211 /* 212 * LEAF 213 * A leaf routine does 214 * - call no other function, 215 * - never use any register that callee-saved (S0-S8), and 216 * - not use any local stack storage. 217 */ 218 #define LEAF(x) \ 219 LEAF_NOPROFILE(x); \ 220 _MIPS_ASM_MCOUNT(x) 221 222 /* 223 * STATIC_XLEAF 224 * declare alternate entry to a static leaf routine 225 */ 226 #define STATIC_XLEAF(x) \ 227 AENT (_C_LABEL(x)); \ 228 _C_LABEL(x): 229 230 /* 231 * XLEAF 232 * declare alternate entry to leaf routine 233 */ 234 #define XLEAF(x) \ 235 .globl _C_LABEL(x); \ 236 STATIC_XLEAF(x) 237 238 /* 239 * STATIC_NESTED_NOPROFILE 240 * No profilable local nested routine. 241 */ 242 #define STATIC_NESTED_NOPROFILE(x, fsize, retpc) \ 243 .ent _C_LABEL(x); \ 244 .type _C_LABEL(x), @function; \ 245 _C_LABEL(x): ; \ 246 .frame sp, fsize, retpc 247 248 /* 249 * NESTED_NOPROFILE 250 * No profilable nested routine. 251 */ 252 #define NESTED_NOPROFILE(x, fsize, retpc) \ 253 .globl _C_LABEL(x); \ 254 STATIC_NESTED_NOPROFILE(x, fsize, retpc) 255 256 /* 257 * NESTED 258 * A function calls other functions and needs 259 * therefore stack space to save/restore registers. 260 */ 261 #define NESTED(x, fsize, retpc) \ 262 NESTED_NOPROFILE(x, fsize, retpc); \ 263 _MIPS_ASM_MCOUNT(x) 264 265 /* 266 * STATIC_NESTED 267 * No profilable local nested routine. 268 */ 269 #define STATIC_NESTED(x, fsize, retpc) \ 270 STATIC_NESTED_NOPROFILE(x, fsize, retpc); \ 271 _MIPS_ASM_MCOUNT(x) 272 273 /* 274 * XNESTED 275 * declare alternate entry point to nested routine. 276 */ 277 #define XNESTED(x) \ 278 .globl _C_LABEL(x); \ 279 AENT (_C_LABEL(x)); \ 280 _C_LABEL(x): 281 282 /* 283 * END 284 * Mark end of a procedure. 285 */ 286 #define END(x) \ 287 .end _C_LABEL(x); \ 288 .size _C_LABEL(x), . - _C_LABEL(x) 289 290 /* 291 * IMPORT -- import external symbol 292 */ 293 #define IMPORT(sym, size) \ 294 .extern _C_LABEL(sym),size 295 296 /* 297 * EXPORT -- export definition of symbol 298 */ 299 #define EXPORT(x) \ 300 .globl _C_LABEL(x); \ 301 _C_LABEL(x): 302 303 /* 304 * EXPORT_OBJECT -- export definition of symbol of symbol 305 * type Object, visible to ksyms(4) address search. 306 */ 307 #define EXPORT_OBJECT(x) \ 308 EXPORT(x); \ 309 .type _C_LABEL(x), @object; 310 311 /* 312 * VECTOR 313 * exception vector entrypoint 314 * XXX: regmask should be used to generate .mask 315 */ 316 #define VECTOR(x, regmask) \ 317 .ent _C_LABEL(x); \ 318 EXPORT(x); \ 319 320 #define VECTOR_END(x) \ 321 EXPORT(__CONCAT(x,_end)); \ 322 END(x); \ 323 .org _C_LABEL(x) + 0x80 324 325 /* 326 * Macros to panic and printf from assembly language. 327 */ 328 #define PANIC(msg) \ 329 PTR_LA a0, 9f; \ 330 jal _C_LABEL(panic); \ 331 nop; \ 332 MSG(msg) 333 334 #define PRINTF(msg) \ 335 PTR_LA a0, 9f; \ 336 jal _C_LABEL(printf); \ 337 nop; \ 338 MSG(msg) 339 340 #define MSG(msg) \ 341 .rdata; \ 342 9: .asciz msg; \ 343 .text 344 345 #define ASMSTR(str) \ 346 .asciz str; \ 347 .align 3 348 349 #ifdef _NETBSD_REVISIONID 350 #define RCSID(x) .pushsection ".ident","MS",@progbits,1; \ 351 .asciz "$" "NetBSD: " __FILE__ \ 352 " " _NETBSD_REVISIONID " $"; \ 353 .popsection 354 #else 355 #define RCSID(x) .pushsection ".ident","MS",@progbits,1; \ 356 .asciz x; \ 357 .popsection 358 #endif 359 360 /* 361 * XXX retain dialects XXX 362 */ 363 #define ALEAF(x) XLEAF(x) 364 #define NLEAF(x) LEAF_NOPROFILE(x) 365 #define NON_LEAF(x, fsize, retpc) NESTED(x, fsize, retpc) 366 #define NNON_LEAF(x, fsize, retpc) NESTED_NOPROFILE(x, fsize, retpc) 367 368 #if defined(__mips_o32) 369 #define SZREG 4 370 #else 371 #define SZREG 8 372 #endif 373 374 #if defined(__mips_o32) || defined(__mips_o64) 375 #define ALSK 7 /* stack alignment */ 376 #define ALMASK -7 /* stack alignment */ 377 #define SZFPREG 4 378 #define FP_L lwc1 379 #define FP_S swc1 380 #else 381 #define ALSK 15 /* stack alignment */ 382 #define ALMASK -15 /* stack alignment */ 383 #define SZFPREG 8 384 #define FP_L ldc1 385 #define FP_S sdc1 386 #endif 387 388 /* 389 * standard callframe { 390 * register_t cf_args[4]; arg0 - arg3 (only on o32 and o64) 391 * register_t cf_pad[N]; o32/64 (N=0), n32 (N=1) n64 (N=1) 392 * register_t cf_gp; global pointer (only on n32 and n64) 393 * register_t cf_sp; frame pointer 394 * register_t cf_ra; return address 395 * }; 396 */ 397 #if defined(__mips_o32) || defined(__mips_o64) 398 #define CALLFRAME_SIZ (SZREG * (4 + 2)) 399 #define CALLFRAME_S0 0 400 #elif defined(__mips_n32) || defined(__mips_n64) 401 #define CALLFRAME_SIZ (SZREG * 4) 402 #define CALLFRAME_S0 (CALLFRAME_SIZ - 4 * SZREG) 403 #endif 404 #ifndef _KERNEL 405 #define CALLFRAME_GP (CALLFRAME_SIZ - 3 * SZREG) 406 #endif 407 #define CALLFRAME_SP (CALLFRAME_SIZ - 2 * SZREG) 408 #define CALLFRAME_RA (CALLFRAME_SIZ - 1 * SZREG) 409 410 /* 411 * While it would be nice to be compatible with the SGI 412 * REG_L and REG_S macros, because they do not take parameters, it 413 * is impossible to use them with the _MIPS_SIM_ABIX32 model. 414 * 415 * These macros hide the use of mips3 instructions from the 416 * assembler to prevent the assembler from generating 64-bit style 417 * ABI calls. 418 */ 419 #ifdef __mips_o32 420 #define PTR_ADD add 421 #define PTR_ADDI addi 422 #define PTR_ADDU addu 423 #define PTR_ADDIU addiu 424 #define PTR_SUB subu 425 #define PTR_SUBI subi 426 #define PTR_SUBU subu 427 #define PTR_SUBIU subu 428 #define PTR_L lw 429 #define PTR_LA la 430 #define PTR_S sw 431 #define PTR_SLL sll 432 #define PTR_SLLV sllv 433 #define PTR_SRL srl 434 #define PTR_SRLV srlv 435 #define PTR_SRA sra 436 #define PTR_SRAV srav 437 #define PTR_LL ll 438 #define PTR_SC sc 439 #define PTR_WORD .word 440 #define PTR_SCALESHIFT 2 441 #else /* _MIPS_SZPTR == 64 */ 442 #define PTR_ADD dadd 443 #define PTR_ADDI daddi 444 #define PTR_ADDU daddu 445 #define PTR_ADDIU daddiu 446 #define PTR_SUB dsubu 447 #define PTR_SUBI dsubi 448 #define PTR_SUBU dsubu 449 #define PTR_SUBIU dsubu 450 #ifdef __mips_n32 451 #define PTR_L lw 452 #define PTR_LL ll 453 #define PTR_SC sc 454 #define PTR_S sw 455 #define PTR_SCALESHIFT 2 456 #define PTR_WORD .word 457 #else 458 #define PTR_L ld 459 #define PTR_LL lld 460 #define PTR_SC scd 461 #define PTR_S sd 462 #define PTR_SCALESHIFT 3 463 #define PTR_WORD .dword 464 #endif 465 #define PTR_LA dla 466 #define PTR_SLL dsll 467 #define PTR_SLLV dsllv 468 #define PTR_SRL dsrl 469 #define PTR_SRLV dsrlv 470 #define PTR_SRA dsra 471 #define PTR_SRAV dsrav 472 #endif /* _MIPS_SZPTR == 64 */ 473 474 #if _MIPS_SZINT == 32 475 #define INT_ADD add 476 #define INT_ADDI addi 477 #define INT_ADDU addu 478 #define INT_ADDIU addiu 479 #define INT_SUB subu 480 #define INT_SUBI subi 481 #define INT_SUBU subu 482 #define INT_SUBIU subu 483 #define INT_L lw 484 #define INT_LA la 485 #define INT_S sw 486 #define INT_SLL sll 487 #define INT_SLLV sllv 488 #define INT_SRL srl 489 #define INT_SRLV srlv 490 #define INT_SRA sra 491 #define INT_SRAV srav 492 #define INT_LL ll 493 #define INT_SC sc 494 #define INT_WORD .word 495 #define INT_SCALESHIFT 2 496 #else 497 #define INT_ADD dadd 498 #define INT_ADDI daddi 499 #define INT_ADDU daddu 500 #define INT_ADDIU daddiu 501 #define INT_SUB dsubu 502 #define INT_SUBI dsubi 503 #define INT_SUBU dsubu 504 #define INT_SUBIU dsubu 505 #define INT_L ld 506 #define INT_LA dla 507 #define INT_S sd 508 #define INT_SLL dsll 509 #define INT_SLLV dsllv 510 #define INT_SRL dsrl 511 #define INT_SRLV dsrlv 512 #define INT_SRA dsra 513 #define INT_SRAV dsrav 514 #define INT_LL lld 515 #define INT_SC scd 516 #define INT_WORD .dword 517 #define INT_SCALESHIFT 3 518 #endif 519 520 #if _MIPS_SZLONG == 32 521 #define LONG_ADD add 522 #define LONG_ADDI addi 523 #define LONG_ADDU addu 524 #define LONG_ADDIU addiu 525 #define LONG_SUB subu 526 #define LONG_SUBI subi 527 #define LONG_SUBU subu 528 #define LONG_SUBIU subu 529 #define LONG_L lw 530 #define LONG_LA la 531 #define LONG_S sw 532 #define LONG_SLL sll 533 #define LONG_SLLV sllv 534 #define LONG_SRL srl 535 #define LONG_SRLV srlv 536 #define LONG_SRA sra 537 #define LONG_SRAV srav 538 #define LONG_LL ll 539 #define LONG_SC sc 540 #define LONG_WORD .word 541 #define LONG_SCALESHIFT 2 542 #else 543 #define LONG_ADD dadd 544 #define LONG_ADDI daddi 545 #define LONG_ADDU daddu 546 #define LONG_ADDIU daddiu 547 #define LONG_SUB dsubu 548 #define LONG_SUBI dsubi 549 #define LONG_SUBU dsubu 550 #define LONG_SUBIU dsubu 551 #define LONG_L ld 552 #define LONG_LA dla 553 #define LONG_S sd 554 #define LONG_SLL dsll 555 #define LONG_SLLV dsllv 556 #define LONG_SRL dsrl 557 #define LONG_SRLV dsrlv 558 #define LONG_SRA dsra 559 #define LONG_SRAV dsrav 560 #define LONG_LL lld 561 #define LONG_SC scd 562 #define LONG_WORD .dword 563 #define LONG_SCALESHIFT 3 564 #endif 565 566 #if SZREG == 4 567 #define REG_L lw 568 #define REG_S sw 569 #define REG_LI li 570 #define REG_ADDU addu 571 #define REG_SLL sll 572 #define REG_SLLV sllv 573 #define REG_SRL srl 574 #define REG_SRLV srlv 575 #define REG_SRA sra 576 #define REG_SRAV srav 577 #define REG_LL ll 578 #define REG_SC sc 579 #define REG_SCALESHIFT 2 580 #else 581 #define REG_L ld 582 #define REG_S sd 583 #define REG_LI dli 584 #define REG_ADDU daddu 585 #define REG_SLL dsll 586 #define REG_SLLV dsllv 587 #define REG_SRL dsrl 588 #define REG_SRLV dsrlv 589 #define REG_SRA dsra 590 #define REG_SRAV dsrav 591 #define REG_LL lld 592 #define REG_SC scd 593 #define REG_SCALESHIFT 3 594 #endif 595 596 #if (MIPS1 + MIPS2) > 0 597 #define NOP_L nop 598 #else 599 #define NOP_L /* nothing */ 600 #endif 601 602 /* compiler define */ 603 #if defined(MULTIPROCESSOR) && defined(__OCTEON__) 604 /* 605 * See common/lib/libc/arch/mips/atomic/membar_ops.S for notes on 606 * Octeon memory ordering guarantees and barriers. 607 * 608 * cnMIPS also has a quirk where the store buffer can get clogged and 609 * we need to apply a plunger to it _after_ releasing a lock or else 610 * other CPUs may spin for hundreds of thousands of cycles before they 611 * see the lock is released. So we also have the quirky SYNC_PLUNGER 612 * barrier as syncw. See the note in the SYNCW instruction description 613 * on p. 2168 of Cavium OCTEON III CN78XX Hardware Reference Manual, 614 * CN78XX-HM-0.99E, September 2014: 615 * 616 * Core A (writer) 617 * 618 * SW R1, DATA# change shared DATA value 619 * LI R1, 1 620 * SYNCW# (or SYNCWS) Perform DATA store before performing FLAG store 621 * SW R2, FLAG# say that the shared DATA value is valid 622 * SYNCW# (or SYNCWS) Force the FLAG store soon (CN78XX-specific) 623 * 624 * ... 625 * 626 * The second SYNCW instruction executed by core A is not 627 * necessary for correctness, but has very important performance 628 * effects on the CN78XX. Without it, the store to FLAG may 629 * linger in core A's write buffer before it becomes visible to 630 * any other cores. (If core A is not performing many stores, 631 * this may add hundreds of thousands of cycles to the flag 632 * release time since the CN78XX core nominally retains stores to 633 * attempt to merge them before sending the store on the CMI.) 634 * Applications should include this second SYNCW instruction after 635 * flag or lock release. 636 */ 637 #define LLSCSYNC /* nothing */ 638 #define BDSYNC sync 639 #define BDSYNC_ACQ nop 640 #define SYNC_ACQ /* nothing */ 641 #define SYNC_REL sync 4 642 #define BDSYNC_PLUNGER sync 4 643 #define SYNC_PLUNGER sync 4 644 #elif defined(MULTIPROCESSOR) && (__mips >= 3 || !defined(__mips_o32)) 645 #define LLSCSYNC /* nothing */ 646 #define BDSYNC sync 647 #define BDSYNC_ACQ sync 648 #define SYNC_ACQ sync 649 #define SYNC_REL sync 650 #define BDSYNC_PLUNGER nop 651 #define SYNC_PLUNGER /* nothing */ 652 #else 653 #define LLSCSYNC /* nothing */ 654 #define BDSYNC nop 655 #define BDSYNC_ACQ nop 656 #define SYNC_ACQ /* nothing */ 657 #define SYNC_REL /* nothing */ 658 #define BDSYNC_PLUNGER nop 659 #define SYNC_PLUNGER /* nothing */ 660 #endif 661 662 /* 663 * Store-before-load barrier. Do not use this unless you know what 664 * you're doing. 665 */ 666 #ifdef MULTIPROCESSOR 667 #define SYNC_DEKKER sync 668 #else 669 #define SYNC_DEKKER /* nothing */ 670 #endif 671 672 /* 673 * Store-before-store and load-before-load barriers. These could be 674 * made weaker than release (load/store-before-store) and acquire 675 * (load-before-load/store) barriers, and newer MIPS does have 676 * instruction encodings for finer-grained barriers like this, but I 677 * dunno how to appropriately conditionalize their use or get the 678 * assembler to be happy with them, so we'll use these definitions for 679 * now. 680 */ 681 #define SYNC_PRODUCER SYNC_REL 682 #define SYNC_CONSUMER SYNC_ACQ 683 684 /* CPU dependent hook for cp0 load delays */ 685 #if defined(MIPS1) || defined(MIPS2) || defined(MIPS3) 686 #define MFC0_HAZARD sll $0,$0,1 /* super scalar nop */ 687 #else 688 #define MFC0_HAZARD /* nothing */ 689 #endif 690 691 #if _MIPS_ISA == _MIPS_ISA_MIPS1 || _MIPS_ISA == _MIPS_ISA_MIPS2 || \ 692 _MIPS_ISA == _MIPS_ISA_MIPS32 693 #define MFC0 mfc0 694 #define MTC0 mtc0 695 #endif 696 #if _MIPS_ISA == _MIPS_ISA_MIPS3 || _MIPS_ISA == _MIPS_ISA_MIPS4 || \ 697 _MIPS_ISA == _MIPS_ISA_MIPS64 698 #define MFC0 dmfc0 699 #define MTC0 dmtc0 700 #endif 701 702 #if defined(__mips_o32) || defined(__mips_o64) 703 704 #ifdef __mips_abicalls 705 #define CPRESTORE(r) .cprestore r 706 #define CPLOAD(r) .cpload r 707 #else 708 #define CPRESTORE(r) /* not needed */ 709 #define CPLOAD(r) /* not needed */ 710 #endif 711 712 #define SETUP_GP \ 713 .set push; \ 714 .set noreorder; \ 715 .cpload t9; \ 716 .set pop 717 #define SETUP_GPX(r) \ 718 .set push; \ 719 .set noreorder; \ 720 move r,ra; /* save old ra */ \ 721 bal 7f; \ 722 nop; \ 723 7: .cpload ra; \ 724 move ra,r; \ 725 .set pop 726 #define SETUP_GPX_L(r,lbl) \ 727 .set push; \ 728 .set noreorder; \ 729 move r,ra; /* save old ra */ \ 730 bal lbl; \ 731 nop; \ 732 lbl: .cpload ra; \ 733 move ra,r; \ 734 .set pop 735 #define SAVE_GP(x) .cprestore x 736 737 #define SETUP_GP64(a,b) /* n32/n64 specific */ 738 #define SETUP_GP64_R(a,b) /* n32/n64 specific */ 739 #define SETUP_GPX64(a,b) /* n32/n64 specific */ 740 #define SETUP_GPX64_L(a,b,c) /* n32/n64 specific */ 741 #define RESTORE_GP64 /* n32/n64 specific */ 742 #define USE_ALT_CP(a) /* n32/n64 specific */ 743 #endif /* __mips_o32 || __mips_o64 */ 744 745 #if defined(__mips_o32) || defined(__mips_o64) 746 #define REG_PROLOGUE .set push 747 #define REG_EPILOGUE .set pop 748 #endif 749 #if defined(__mips_n32) || defined(__mips_n64) 750 #define REG_PROLOGUE .set push ; .set mips3 751 #define REG_EPILOGUE .set pop 752 #endif 753 754 #if defined(__mips_n32) || defined(__mips_n64) 755 #define SETUP_GP /* o32 specific */ 756 #define SETUP_GPX(r) /* o32 specific */ 757 #define SETUP_GPX_L(r,lbl) /* o32 specific */ 758 #define SAVE_GP(x) /* o32 specific */ 759 #define SETUP_GP64(a,b) .cpsetup t9, a, b 760 #define SETUP_GPX64(a,b) \ 761 .set push; \ 762 move b,ra; \ 763 .set noreorder; \ 764 bal 7f; \ 765 nop; \ 766 7: .set pop; \ 767 .cpsetup ra, a, 7b; \ 768 move ra,b 769 #define SETUP_GPX64_L(a,b,c) \ 770 .set push; \ 771 move b,ra; \ 772 .set noreorder; \ 773 bal c; \ 774 nop; \ 775 c: .set pop; \ 776 .cpsetup ra, a, c; \ 777 move ra,b 778 #define RESTORE_GP64 .cpreturn 779 #define USE_ALT_CP(a) .cplocal a 780 #endif /* __mips_n32 || __mips_n64 */ 781 782 /* 783 * The DYNAMIC_STATUS_MASK option adds an additional masking operation 784 * when updating the hardware interrupt mask in the status register. 785 * 786 * This is useful for platforms that need to at run-time mask 787 * interrupts based on motherboard configuration or to handle 788 * slowly clearing interrupts. 789 * 790 * XXX this is only currently implemented for mips3. 791 */ 792 #ifdef MIPS_DYNAMIC_STATUS_MASK 793 #define DYNAMIC_STATUS_MASK(sr,scratch) \ 794 lw scratch, mips_dynamic_status_mask; \ 795 and sr, sr, scratch 796 797 #define DYNAMIC_STATUS_MASK_TOUSER(sr,scratch1) \ 798 ori sr, (MIPS_INT_MASK | MIPS_SR_INT_IE); \ 799 DYNAMIC_STATUS_MASK(sr,scratch1) 800 #else 801 #define DYNAMIC_STATUS_MASK(sr,scratch) 802 #define DYNAMIC_STATUS_MASK_TOUSER(sr,scratch1) 803 #endif 804 805 /* See lock_stubs.S. */ 806 #define LOG2_MIPS_LOCK_RAS_SIZE 8 807 #define MIPS_LOCK_RAS_SIZE 256 /* 16 bytes left over */ 808 809 #define CPUVAR(off) _C_LABEL(cpu_info_store)+__CONCAT(CPU_INFO_,off) 810 811 #endif /* _MIPS_ASM_H */ 812
Indexes created Thu Sep 25 14:09:45 GMT 2025