cache_r4k.h revision 1.10.18.1
1 /* $NetBSD: cache_r4k.h,v 1.10.18.1 2006/06/21 14:53:38 yamt Exp $ */ 2 3 /* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Cache definitions/operations for R4000-style caches. 40 */ 41 42 #define CACHE_R4K_I 0 43 #define CACHE_R4K_D 1 44 #define CACHE_R4K_SI 2 45 #define CACHE_R4K_SD 3 46 47 #define CACHEOP_R4K_INDEX_INV (0 << 2) /* I, SI */ 48 #define CACHEOP_R4K_INDEX_WB_INV (0 << 2) /* D, SD */ 49 #define CACHEOP_R4K_INDEX_LOAD_TAG (1 << 2) /* all */ 50 #define CACHEOP_R4K_INDEX_STORE_TAG (2 << 2) /* all */ 51 #define CACHEOP_R4K_CREATE_DIRTY_EXCL (3 << 2) /* D, SD */ 52 #define CACHEOP_R4K_HIT_INV (4 << 2) /* all */ 53 #define CACHEOP_R4K_HIT_WB_INV (5 << 2) /* D, SD */ 54 #define CACHEOP_R4K_FILL (5 << 2) /* I */ 55 #define CACHEOP_R4K_HIT_WB (6 << 2) /* I, D, SD */ 56 #define CACHEOP_R4K_HIT_SET_VIRTUAL (7 << 2) /* SI, SD */ 57 58 #if !defined(_LOCORE) 59 60 /* 61 * cache_r4k_op_line: 62 * 63 * Perform the specified cache operation on a single line. 64 */ 65 #define cache_op_r4k_line(va, op) \ 66 do { \ 67 __asm volatile( \ 68 ".set noreorder \n\t" \ 69 "cache %1, 0(%0) \n\t" \ 70 ".set reorder" \ 71 : \ 72 : "r" (va), "i" (op) \ 73 : "memory"); \ 74 } while (/*CONSTCOND*/0) 75 76 /* 77 * cache_r4k_op_8lines_16: 78 * 79 * Perform the specified cache operation on 8 16-byte cache lines. 80 */ 81 #define cache_r4k_op_8lines_16(va, op) \ 82 do { \ 83 __asm volatile( \ 84 ".set noreorder \n\t" \ 85 "cache %1, 0x00(%0); cache %1, 0x10(%0) \n\t" \ 86 "cache %1, 0x20(%0); cache %1, 0x30(%0) \n\t" \ 87 "cache %1, 0x40(%0); cache %1, 0x50(%0) \n\t" \ 88 "cache %1, 0x60(%0); cache %1, 0x70(%0) \n\t" \ 89 ".set reorder" \ 90 : \ 91 : "r" (va), "i" (op) \ 92 : "memory"); \ 93 } while (/*CONSTCOND*/0) 94 95 /* 96 * cache_r4k_op_8lines_32: 97 * 98 * Perform the specified cache operation on 8 32-byte cache lines. 99 */ 100 #define cache_r4k_op_8lines_32(va, op) \ 101 do { \ 102 __asm volatile( \ 103 ".set noreorder \n\t" \ 104 "cache %1, 0x00(%0); cache %1, 0x20(%0) \n\t" \ 105 "cache %1, 0x40(%0); cache %1, 0x60(%0) \n\t" \ 106 "cache %1, 0x80(%0); cache %1, 0xa0(%0) \n\t" \ 107 "cache %1, 0xc0(%0); cache %1, 0xe0(%0) \n\t" \ 108 ".set reorder" \ 109 : \ 110 : "r" (va), "i" (op) \ 111 : "memory"); \ 112 } while (/*CONSTCOND*/0) 113 114 /* 115 * cache_r4k_op_32lines_16: 116 * 117 * Perform the specified cache operation on 32 16-byte 118 * cache lines. 119 */ 120 #define cache_r4k_op_32lines_16(va, op) \ 121 do { \ 122 __asm volatile( \ 123 ".set noreorder \n\t" \ 124 "cache %1, 0x000(%0); cache %1, 0x010(%0); \n\t" \ 125 "cache %1, 0x020(%0); cache %1, 0x030(%0); \n\t" \ 126 "cache %1, 0x040(%0); cache %1, 0x050(%0); \n\t" \ 127 "cache %1, 0x060(%0); cache %1, 0x070(%0); \n\t" \ 128 "cache %1, 0x080(%0); cache %1, 0x090(%0); \n\t" \ 129 "cache %1, 0x0a0(%0); cache %1, 0x0b0(%0); \n\t" \ 130 "cache %1, 0x0c0(%0); cache %1, 0x0d0(%0); \n\t" \ 131 "cache %1, 0x0e0(%0); cache %1, 0x0f0(%0); \n\t" \ 132 "cache %1, 0x100(%0); cache %1, 0x110(%0); \n\t" \ 133 "cache %1, 0x120(%0); cache %1, 0x130(%0); \n\t" \ 134 "cache %1, 0x140(%0); cache %1, 0x150(%0); \n\t" \ 135 "cache %1, 0x160(%0); cache %1, 0x170(%0); \n\t" \ 136 "cache %1, 0x180(%0); cache %1, 0x190(%0); \n\t" \ 137 "cache %1, 0x1a0(%0); cache %1, 0x1b0(%0); \n\t" \ 138 "cache %1, 0x1c0(%0); cache %1, 0x1d0(%0); \n\t" \ 139 "cache %1, 0x1e0(%0); cache %1, 0x1f0(%0); \n\t" \ 140 ".set reorder" \ 141 : \ 142 : "r" (va), "i" (op) \ 143 : "memory"); \ 144 } while (/*CONSTCOND*/0) 145 146 /* 147 * cache_r4k_op_32lines_32: 148 * 149 * Perform the specified cache operation on 32 32-byte 150 * cache lines. 151 */ 152 #define cache_r4k_op_32lines_32(va, op) \ 153 do { \ 154 __asm volatile( \ 155 ".set noreorder \n\t" \ 156 "cache %1, 0x000(%0); cache %1, 0x020(%0); \n\t" \ 157 "cache %1, 0x040(%0); cache %1, 0x060(%0); \n\t" \ 158 "cache %1, 0x080(%0); cache %1, 0x0a0(%0); \n\t" \ 159 "cache %1, 0x0c0(%0); cache %1, 0x0e0(%0); \n\t" \ 160 "cache %1, 0x100(%0); cache %1, 0x120(%0); \n\t" \ 161 "cache %1, 0x140(%0); cache %1, 0x160(%0); \n\t" \ 162 "cache %1, 0x180(%0); cache %1, 0x1a0(%0); \n\t" \ 163 "cache %1, 0x1c0(%0); cache %1, 0x1e0(%0); \n\t" \ 164 "cache %1, 0x200(%0); cache %1, 0x220(%0); \n\t" \ 165 "cache %1, 0x240(%0); cache %1, 0x260(%0); \n\t" \ 166 "cache %1, 0x280(%0); cache %1, 0x2a0(%0); \n\t" \ 167 "cache %1, 0x2c0(%0); cache %1, 0x2e0(%0); \n\t" \ 168 "cache %1, 0x300(%0); cache %1, 0x320(%0); \n\t" \ 169 "cache %1, 0x340(%0); cache %1, 0x360(%0); \n\t" \ 170 "cache %1, 0x380(%0); cache %1, 0x3a0(%0); \n\t" \ 171 "cache %1, 0x3c0(%0); cache %1, 0x3e0(%0); \n\t" \ 172 ".set reorder" \ 173 : \ 174 : "r" (va), "i" (op) \ 175 : "memory"); \ 176 } while (/*CONSTCOND*/0) 177 178 /* 179 * cache_r4k_op_32lines_128: 180 * 181 * Perform the specified cache operation on 32 128-byte 182 * cache lines. 183 */ 184 #define cache_r4k_op_32lines_128(va, op) \ 185 do { \ 186 __asm volatile( \ 187 ".set noreorder \n\t" \ 188 "cache %1, 0x0000(%0); cache %1, 0x0080(%0); \n\t" \ 189 "cache %1, 0x0100(%0); cache %1, 0x0180(%0); \n\t" \ 190 "cache %1, 0x0200(%0); cache %1, 0x0280(%0); \n\t" \ 191 "cache %1, 0x0300(%0); cache %1, 0x0380(%0); \n\t" \ 192 "cache %1, 0x0400(%0); cache %1, 0x0480(%0); \n\t" \ 193 "cache %1, 0x0500(%0); cache %1, 0x0580(%0); \n\t" \ 194 "cache %1, 0x0600(%0); cache %1, 0x0680(%0); \n\t" \ 195 "cache %1, 0x0700(%0); cache %1, 0x0780(%0); \n\t" \ 196 "cache %1, 0x0800(%0); cache %1, 0x0880(%0); \n\t" \ 197 "cache %1, 0x0900(%0); cache %1, 0x0980(%0); \n\t" \ 198 "cache %1, 0x0a00(%0); cache %1, 0x0a80(%0); \n\t" \ 199 "cache %1, 0x0b00(%0); cache %1, 0x0b80(%0); \n\t" \ 200 "cache %1, 0x0c00(%0); cache %1, 0x0c80(%0); \n\t" \ 201 "cache %1, 0x0d00(%0); cache %1, 0x0d80(%0); \n\t" \ 202 "cache %1, 0x0e00(%0); cache %1, 0x0e80(%0); \n\t" \ 203 "cache %1, 0x0f00(%0); cache %1, 0x0f80(%0); \n\t" \ 204 ".set reorder" \ 205 : \ 206 : "r" (va), "i" (op) \ 207 : "memory"); \ 208 } while (/*CONSTCOND*/0) 209 210 /* 211 * cache_r4k_op_16lines_16_2way: 212 * 213 * Perform the specified cache operation on 16 16-byte 214 * cache lines, 2-ways. 215 */ 216 #define cache_r4k_op_16lines_16_2way(va1, va2, op) \ 217 do { \ 218 __asm volatile( \ 219 ".set noreorder \n\t" \ 220 "cache %2, 0x000(%0); cache %2, 0x000(%1); \n\t" \ 221 "cache %2, 0x010(%0); cache %2, 0x010(%1); \n\t" \ 222 "cache %2, 0x020(%0); cache %2, 0x020(%1); \n\t" \ 223 "cache %2, 0x030(%0); cache %2, 0x030(%1); \n\t" \ 224 "cache %2, 0x040(%0); cache %2, 0x040(%1); \n\t" \ 225 "cache %2, 0x050(%0); cache %2, 0x050(%1); \n\t" \ 226 "cache %2, 0x060(%0); cache %2, 0x060(%1); \n\t" \ 227 "cache %2, 0x070(%0); cache %2, 0x070(%1); \n\t" \ 228 "cache %2, 0x080(%0); cache %2, 0x080(%1); \n\t" \ 229 "cache %2, 0x090(%0); cache %2, 0x090(%1); \n\t" \ 230 "cache %2, 0x0a0(%0); cache %2, 0x0a0(%1); \n\t" \ 231 "cache %2, 0x0b0(%0); cache %2, 0x0b0(%1); \n\t" \ 232 "cache %2, 0x0c0(%0); cache %2, 0x0c0(%1); \n\t" \ 233 "cache %2, 0x0d0(%0); cache %2, 0x0d0(%1); \n\t" \ 234 "cache %2, 0x0e0(%0); cache %2, 0x0e0(%1); \n\t" \ 235 "cache %2, 0x0f0(%0); cache %2, 0x0f0(%1); \n\t" \ 236 ".set reorder" \ 237 : \ 238 : "r" (va1), "r" (va2), "i" (op) \ 239 : "memory"); \ 240 } while (/*CONSTCOND*/0) 241 242 /* 243 * cache_r4k_op_16lines_32_2way: 244 * 245 * Perform the specified cache operation on 16 32-byte 246 * cache lines, 2-ways. 247 */ 248 #define cache_r4k_op_16lines_32_2way(va1, va2, op) \ 249 do { \ 250 __asm volatile( \ 251 ".set noreorder \n\t" \ 252 "cache %2, 0x000(%0); cache %2, 0x000(%1); \n\t" \ 253 "cache %2, 0x020(%0); cache %2, 0x020(%1); \n\t" \ 254 "cache %2, 0x040(%0); cache %2, 0x040(%1); \n\t" \ 255 "cache %2, 0x060(%0); cache %2, 0x060(%1); \n\t" \ 256 "cache %2, 0x080(%0); cache %2, 0x080(%1); \n\t" \ 257 "cache %2, 0x0a0(%0); cache %2, 0x0a0(%1); \n\t" \ 258 "cache %2, 0x0c0(%0); cache %2, 0x0c0(%1); \n\t" \ 259 "cache %2, 0x0e0(%0); cache %2, 0x0e0(%1); \n\t" \ 260 "cache %2, 0x100(%0); cache %2, 0x100(%1); \n\t" \ 261 "cache %2, 0x120(%0); cache %2, 0x120(%1); \n\t" \ 262 "cache %2, 0x140(%0); cache %2, 0x140(%1); \n\t" \ 263 "cache %2, 0x160(%0); cache %2, 0x160(%1); \n\t" \ 264 "cache %2, 0x180(%0); cache %2, 0x180(%1); \n\t" \ 265 "cache %2, 0x1a0(%0); cache %2, 0x1a0(%1); \n\t" \ 266 "cache %2, 0x1c0(%0); cache %2, 0x1c0(%1); \n\t" \ 267 "cache %2, 0x1e0(%0); cache %2, 0x1e0(%1); \n\t" \ 268 ".set reorder" \ 269 : \ 270 : "r" (va1), "r" (va2), "i" (op) \ 271 : "memory"); \ 272 } while (/*CONSTCOND*/0) 273 274 /* 275 * cache_r4k_op_8lines_16_4way: 276 * 277 * Perform the specified cache operation on 8 16-byte 278 * cache lines, 4-ways. 279 */ 280 #define cache_r4k_op_8lines_16_4way(va1, va2, va3, va4, op) \ 281 do { \ 282 __asm volatile( \ 283 ".set noreorder \n\t" \ 284 "cache %4, 0x000(%0); cache %4, 0x000(%1); \n\t" \ 285 "cache %4, 0x000(%2); cache %4, 0x000(%3); \n\t" \ 286 "cache %4, 0x010(%0); cache %4, 0x010(%1); \n\t" \ 287 "cache %4, 0x010(%2); cache %4, 0x010(%3); \n\t" \ 288 "cache %4, 0x020(%0); cache %4, 0x020(%1); \n\t" \ 289 "cache %4, 0x020(%2); cache %4, 0x020(%3); \n\t" \ 290 "cache %4, 0x030(%0); cache %4, 0x030(%1); \n\t" \ 291 "cache %4, 0x030(%2); cache %4, 0x030(%3); \n\t" \ 292 "cache %4, 0x040(%0); cache %4, 0x040(%1); \n\t" \ 293 "cache %4, 0x040(%2); cache %4, 0x040(%3); \n\t" \ 294 "cache %4, 0x050(%0); cache %4, 0x050(%1); \n\t" \ 295 "cache %4, 0x050(%2); cache %4, 0x050(%3); \n\t" \ 296 "cache %4, 0x060(%0); cache %4, 0x060(%1); \n\t" \ 297 "cache %4, 0x060(%2); cache %4, 0x060(%3); \n\t" \ 298 "cache %4, 0x070(%0); cache %4, 0x070(%1); \n\t" \ 299 "cache %4, 0x070(%2); cache %4, 0x070(%3); \n\t" \ 300 ".set reorder" \ 301 : \ 302 : "r" (va1), "r" (va2), "r" (va3), "r" (va4), "i" (op) \ 303 : "memory"); \ 304 } while (/*CONSTCOND*/0) 305 306 /* 307 * cache_r4k_op_8lines_32_4way: 308 * 309 * Perform the specified cache operation on 8 32-byte 310 * cache lines, 4-ways. 311 */ 312 #define cache_r4k_op_8lines_32_4way(va1, va2, va3, va4, op) \ 313 do { \ 314 __asm volatile( \ 315 ".set noreorder \n\t" \ 316 "cache %4, 0x000(%0); cache %4, 0x000(%1); \n\t" \ 317 "cache %4, 0x000(%2); cache %4, 0x000(%3); \n\t" \ 318 "cache %4, 0x020(%0); cache %4, 0x020(%1); \n\t" \ 319 "cache %4, 0x020(%2); cache %4, 0x020(%3); \n\t" \ 320 "cache %4, 0x040(%0); cache %4, 0x040(%1); \n\t" \ 321 "cache %4, 0x040(%2); cache %4, 0x040(%3); \n\t" \ 322 "cache %4, 0x060(%0); cache %4, 0x060(%1); \n\t" \ 323 "cache %4, 0x060(%2); cache %4, 0x060(%3); \n\t" \ 324 "cache %4, 0x080(%0); cache %4, 0x080(%1); \n\t" \ 325 "cache %4, 0x080(%2); cache %4, 0x080(%3); \n\t" \ 326 "cache %4, 0x0a0(%0); cache %4, 0x0a0(%1); \n\t" \ 327 "cache %4, 0x0a0(%2); cache %4, 0x0a0(%3); \n\t" \ 328 "cache %4, 0x0c0(%0); cache %4, 0x0c0(%1); \n\t" \ 329 "cache %4, 0x0c0(%2); cache %4, 0x0c0(%3); \n\t" \ 330 "cache %4, 0x0e0(%0); cache %4, 0x0e0(%1); \n\t" \ 331 "cache %4, 0x0e0(%2); cache %4, 0x0e0(%3); \n\t" \ 332 ".set reorder" \ 333 : \ 334 : "r" (va1), "r" (va2), "r" (va3), "r" (va4), "i" (op) \ 335 : "memory"); \ 336 } while (/*CONSTCOND*/0) 337 338 void r4k_icache_sync_all_16(void); 339 void r4k_icache_sync_range_16(vaddr_t, vsize_t); 340 void r4k_icache_sync_range_index_16(vaddr_t, vsize_t); 341 342 void r4k_icache_sync_all_32(void); 343 void r4k_icache_sync_range_32(vaddr_t, vsize_t); 344 void r4k_icache_sync_range_index_32(vaddr_t, vsize_t); 345 346 void r4k_pdcache_wbinv_all_16(void); 347 void r4k_pdcache_wbinv_range_16(vaddr_t, vsize_t); 348 void r4k_pdcache_wbinv_range_index_16(vaddr_t, vsize_t); 349 350 void r4k_pdcache_inv_range_16(vaddr_t, vsize_t); 351 void r4k_pdcache_wb_range_16(vaddr_t, vsize_t); 352 353 void r4k_pdcache_wbinv_all_32(void); 354 void r4k_pdcache_wbinv_range_32(vaddr_t, vsize_t); 355 void r4k_pdcache_wbinv_range_index_32(vaddr_t, vsize_t); 356 357 void r4k_pdcache_inv_range_32(vaddr_t, vsize_t); 358 void r4k_pdcache_wb_range_32(vaddr_t, vsize_t); 359 360 void r4k_sdcache_wbinv_all_32(void); 361 void r4k_sdcache_wbinv_range_32(vaddr_t, vsize_t); 362 void r4k_sdcache_wbinv_range_index_32(vaddr_t, vsize_t); 363 364 void r4k_sdcache_inv_range_32(vaddr_t, vsize_t); 365 void r4k_sdcache_wb_range_32(vaddr_t, vsize_t); 366 367 void r4k_sdcache_wbinv_all_128(void); 368 void r4k_sdcache_wbinv_range_128(vaddr_t, vsize_t); 369 void r4k_sdcache_wbinv_range_index_128(vaddr_t, vsize_t); 370 371 void r4k_sdcache_inv_range_128(vaddr_t, vsize_t); 372 void r4k_sdcache_wb_range_128(vaddr_t, vsize_t); 373 374 void r4k_sdcache_wbinv_all_generic(void); 375 void r4k_sdcache_wbinv_range_generic(vaddr_t, vsize_t); 376 void r4k_sdcache_wbinv_range_index_generic(vaddr_t, vsize_t); 377 378 void r4k_sdcache_inv_range_generic(vaddr_t, vsize_t); 379 void r4k_sdcache_wb_range_generic(vaddr_t, vsize_t); 380 381 #endif /* !_LOCORE */ 382
Indexes created Thu Oct 02 07:10:07 GMT 2025