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History log of /src/sys/arch/mips/include/cache_r4k.h
RevisionDateAuthorComments
 1.17  26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.16  12-Jul-2016  skrll Appease gcc and asm
 1.15  12-Jul-2016  skrll Fix RCSId
 1.14  11-Jul-2016  matt Use sdcache routines.
Remove old cache support.
Switch to new cache routines.
 1.13  11-Jul-2016  skrll Trailing whitespace
 1.12  11-Jul-2016  matt Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch
 1.11  24-Dec-2005  perry branches: 1.11.96; 1.11.122; 1.11.142;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.
 1.10  08-Mar-2003  rafal branches: 1.10.18;
Add support for R5k secondary caches, from code Chris Sekiya sent me a long
time ago, with small tweaks by me. Since the R5k doesn't do VCE, the pmap
still needs to be whacked for R5kSC CPUs to work correctly, but this is a
start.
 1.9  17-Feb-2003  simonb No need to protect headers with #ifdef _KERNEL if they're never installed
in /usr/include.
 1.8  17-Nov-2002  simonb Add cache_r4k_op_8lines_{16,32} macros to perform cache ops on 8
consecutive lines.
 1.7  05-Mar-2002  simonb Add 4way 16/32-byte-line cache op primitives.
 1.6  19-Jan-2002  shin add VR4131 cache-op bug workaround code.
we can't use Hit_WriteBack_Invalidate.
 1.5  23-Dec-2001  takemura branches: 1.5.2;
Added Vr4131 support.
 1.4  23-Nov-2001  tsutsui Add 32B/l L1 D/I-cache ops for newer ARC machines.
 1.3  18-Nov-2001  thorpej Add 128b/l L2 cache ops.
 1.2  14-Nov-2001  thorpej branches: 1.2.2;
Merge the thorpej-mips-cache branch onto the trunk. This is an
overhaul of how caches are handled for NetBSD's MIPS ports.
 1.1  24-Oct-2001  thorpej branches: 1.1.2;
file cache_r4k.h was initially added on branch thorpej-mips-cache.
 1.1.2.3  13-Nov-2001  thorpej Fix 3 bad offsets in the cache_r4k_op_32lines_32() loop.
 1.1.2.2  12-Nov-2001  shin improve R4000/4400 secondary cache support.
add support for secondary cache line sizes 16, 64, 128.
 1.1.2.1  24-Oct-2001  thorpej New style cache operations for R4000/R4400-style caches.
 1.2.2.5  11-Dec-2002  thorpej Sync with HEAD.
 1.2.2.4  01-Apr-2002  nathanw Catch up to -current.
(CVS: It's not just a program. It's an adventure!)
 1.2.2.3  28-Feb-2002  nathanw Catch up to -current.
 1.2.2.2  01-Feb-2002  gmcgarry Pull-up cache ops from -current
 1.2.2.1  14-Nov-2001  gmcgarry file cache_r4k.h was added on branch nathanw_sa on 2002-02-01 04:57:44 +0000
 1.5.2.4  16-Mar-2002  jdolecek Catch up with -current.
 1.5.2.3  11-Feb-2002  jdolecek Sync w/ -current.
 1.5.2.2  10-Jan-2002  thorpej Sync kqueue branch with -current.
 1.5.2.1  23-Dec-2001  thorpej file cache_r4k.h was added on branch kqueue on 2002-01-10 19:45:59 +0000
 1.10.18.1  21-Jun-2006  yamt sync with head.
 1.11.142.1  05-Oct-2016  skrll Sync with HEAD
 1.11.122.1  03-Dec-2017  jdolecek update from HEAD
 1.11.96.3  19-Jan-2012  matt When running an N32 kernel, run it with 64-bit addresses even though the
kernel itself will only use 32-bit addresses. There are exceptions.
bus_space_handles are now register_t instead of intptr_t. This allows them
to contain XKPHYS addresses. Now bus_space can use XKPHYS addresses and
not required non-KSEG1 devices to be mapped in KSEG2 thereby leaving more
KSEG2 space for the kernel to use.

The cache range routines (but not index routines) now take a register_t
instead of vaddr_t so they can too take a XKPHYS address. This allows the
pmap to use a page's XKPHYS address to clean sync the icache thereby avoiding
massive icache invalidations.

Since "cache" instruction effects are global to all CPUs and their caches, we
can use the above to greatly simplify MP page isyncs. If using an O32 kernel
with pages outside KSEG0, index ops still need to be performed since there
isn't an a quick way of mapping the page.
 1.11.96.2  27-Dec-2011  matt Make these play nice with modules.
 1.11.96.1  24-Dec-2011  matt Change macros with embedded asm into static inline functions.
Pass in line_size to asm and gas expand to the proper offsets.

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