cache_r4k.h revision 1.13
1 /* cache_r4k.h,v 1.11.96.3 2012/01/19 08:28:48 matt Exp */ 2 3 /* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Cache definitions/operations for R4000-style caches. 40 */ 41 42 #define CACHE_R4K_I 0 43 #define CACHE_R4K_D 1 44 #define CACHE_R4K_SI 2 45 #define CACHE_R4K_SD 3 46 47 #define CACHEOP_R4K_INDEX_INV (0 << 2) /* I, SI */ 48 #define CACHEOP_R4K_INDEX_WB_INV (0 << 2) /* D, SD */ 49 #define CACHEOP_R4K_INDEX_LOAD_TAG (1 << 2) /* all */ 50 #define CACHEOP_R4K_INDEX_STORE_TAG (2 << 2) /* all */ 51 #define CACHEOP_R4K_CREATE_DIRTY_EXCL (3 << 2) /* D, SD */ 52 #define CACHEOP_R4K_HIT_INV (4 << 2) /* all */ 53 #define CACHEOP_R4K_HIT_WB_INV (5 << 2) /* D, SD */ 54 #define CACHEOP_R4K_FILL (5 << 2) /* I */ 55 #define CACHEOP_R4K_HIT_WB (6 << 2) /* I, D, SD */ 56 #define CACHEOP_R4K_HIT_SET_VIRTUAL (7 << 2) /* SI, SD */ 57 58 #if !defined(_LOCORE) 59 60 /* 61 * cache_r4k_op_line: 62 * 63 * Perform the specified cache operation on a single line. 64 */ 65 static inline void 66 cache_op_r4k_line(register_t va, u_int op) 67 { 68 __CTASSERT(__builtin_constant_p(op)); 69 __asm volatile( 70 ".set push" "\n\t" 71 ".set noreorder" "\n\t" 72 "cache %[op], 0(%[va])" "\n\t" 73 ".set pop" 74 : 75 : [op] "n" (op), [va] "r" (va) 76 : "memory"); 77 } 78 79 /* 80 * cache_r4k_op_8lines_NN: 81 * 82 * Perform the specified cache operation on 8 n-byte cache lines. 83 */ 84 static inline void 85 cache_r4k_op_8lines_NN(size_t n, register_t va, u_int op) 86 { 87 __asm volatile( 88 ".set push" "\n\t" 89 ".set noreorder" "\n\t" 90 "cache %[op], (0*%[n])(%[va])" "\n\t" 91 "cache %[op], (1*%[n])(%[va])" "\n\t" 92 "cache %[op], (2*%[n])(%[va])" "\n\t" 93 "cache %[op], (3*%[n])(%[va])" "\n\t" 94 "cache %[op], (4*%[n])(%[va])" "\n\t" 95 "cache %[op], (5*%[n])(%[va])" "\n\t" 96 "cache %[op], (6*%[n])(%[va])" "\n\t" 97 "cache %[op], (7*%[n])(%[va])" "\n\t" 98 ".set pop" 99 : 100 : [va] "r" (va), [op] "i" (op), [n] "n" (n) 101 : "memory"); 102 } 103 104 /* 105 * cache_r4k_op_8lines_16: 106 * Perform the specified cache operation on 8 16-byte cache lines. 107 * cache_r4k_op_8lines_32: 108 * Perform the specified cache operation on 8 32-byte cache lines. 109 */ 110 #define cache_r4k_op_8lines_16(va, op) \ 111 cache_r4k_op_8lines_NN(16, (va), (op)) 112 #define cache_r4k_op_8lines_32(va, op) \ 113 cache_r4k_op_8lines_NN(32, (va), (op)) 114 #define cache_r4k_op_8lines_64(va, op) \ 115 cache_r4k_op_8lines_NN(64, (va), (op)) 116 #define cache_r4k_op_8lines_128(va, op) \ 117 cache_r4k_op_8lines_NN(128, (va), (op)) 118 119 /* 120 * cache_r4k_op_32lines_NN: 121 * 122 * Perform the specified cache operation on 32 n-byte cache lines. 123 */ 124 static inline void 125 cache_r4k_op_32lines_NN(size_t n, register_t va, u_int op) 126 { 127 __CTASSERT(__builtin_constant_p(n)); 128 __CTASSERT(__builtin_constant_p(op)); 129 __asm volatile( 130 ".set push" "\n\t" 131 ".set noreorder" "\n\t" 132 "cache %[op], (0*%[n])(%[va])" "\n\t" 133 "cache %[op], (1*%[n])(%[va])" "\n\t" 134 "cache %[op], (2*%[n])(%[va])" "\n\t" 135 "cache %[op], (3*%[n])(%[va])" "\n\t" 136 "cache %[op], (4*%[n])(%[va])" "\n\t" 137 "cache %[op], (5*%[n])(%[va])" "\n\t" 138 "cache %[op], (6*%[n])(%[va])" "\n\t" 139 "cache %[op], (7*%[n])(%[va])" "\n\t" 140 "cache %[op], (8*%[n])(%[va])" "\n\t" 141 "cache %[op], (9*%[n])(%[va])" "\n\t" 142 "cache %[op], (10*%[n])(%[va])" "\n\t" 143 "cache %[op], (11*%[n])(%[va])" "\n\t" 144 "cache %[op], (12*%[n])(%[va])" "\n\t" 145 "cache %[op], (13*%[n])(%[va])" "\n\t" 146 "cache %[op], (14*%[n])(%[va])" "\n\t" 147 "cache %[op], (15*%[n])(%[va])" "\n\t" 148 "cache %[op], (16*%[n])(%[va])" "\n\t" 149 "cache %[op], (17*%[n])(%[va])" "\n\t" 150 "cache %[op], (18*%[n])(%[va])" "\n\t" 151 "cache %[op], (19*%[n])(%[va])" "\n\t" 152 "cache %[op], (20*%[n])(%[va])" "\n\t" 153 "cache %[op], (21*%[n])(%[va])" "\n\t" 154 "cache %[op], (22*%[n])(%[va])" "\n\t" 155 "cache %[op], (23*%[n])(%[va])" "\n\t" 156 "cache %[op], (24*%[n])(%[va])" "\n\t" 157 "cache %[op], (25*%[n])(%[va])" "\n\t" 158 "cache %[op], (26*%[n])(%[va])" "\n\t" 159 "cache %[op], (27*%[n])(%[va])" "\n\t" 160 "cache %[op], (28*%[n])(%[va])" "\n\t" 161 "cache %[op], (29*%[n])(%[va])" "\n\t" 162 "cache %[op], (30*%[n])(%[va])" "\n\t" 163 "cache %[op], (31*%[n])(%[va])" "\n\t" 164 ".set pop" 165 : 166 : [n] "n" ((uint8_t)n), [va] "r" (va), [op] "i" ((uint8_t)op) 167 : "memory"); 168 } 169 170 /* 171 * cache_r4k_op_32lines_16: 172 * 173 * Perform the specified cache operation on 32 16-byte cache lines. 174 */ 175 #define cache_r4k_op_32lines_16(va, op) \ 176 cache_r4k_op_32lines_NN(16, (va), (op)) 177 #define cache_r4k_op_32lines_32(va, op) \ 178 cache_r4k_op_32lines_NN(32, (va), (op)) 179 #define cache_r4k_op_32lines_64(va, op) \ 180 cache_r4k_op_32lines_NN(64, (va), (op)) 181 #define cache_r4k_op_32lines_128(va, op) \ 182 cache_r4k_op_32lines_NN(128, (va), (op)) 183 184 /* 185 * cache_r4k_op_16lines_16_2way: 186 * Perform the specified cache operation on 16 n-byte cache lines, 2-ways. 187 */ 188 static inline void 189 cache_r4k_op_16lines_NN_2way(size_t n, register_t va1, register_t va2, u_int op) 190 { 191 __asm volatile( 192 ".set push" "\n\t" 193 ".set noreorder" "\n\t" 194 "cache %[op], (0*%[n])(%[va1])" "\n\t" 195 "cache %[op], (0*%[n])(%[va2])" "\n\t" 196 "cache %[op], (1*%[n])(%[va1])" "\n\t" 197 "cache %[op], (1*%[n])(%[va2])" "\n\t" 198 "cache %[op], (2*%[n])(%[va1])" "\n\t" 199 "cache %[op], (2*%[n])(%[va2])" "\n\t" 200 "cache %[op], (3*%[n])(%[va1])" "\n\t" 201 "cache %[op], (3*%[n])(%[va2])" "\n\t" 202 "cache %[op], (4*%[n])(%[va1])" "\n\t" 203 "cache %[op], (4*%[n])(%[va2])" "\n\t" 204 "cache %[op], (5*%[n])(%[va1])" "\n\t" 205 "cache %[op], (5*%[n])(%[va2])" "\n\t" 206 "cache %[op], (6*%[n])(%[va1])" "\n\t" 207 "cache %[op], (6*%[n])(%[va2])" "\n\t" 208 "cache %[op], (7*%[n])(%[va1])" "\n\t" 209 "cache %[op], (7*%[n])(%[va2])" "\n\t" 210 "cache %[op], (8*%[n])(%[va1])" "\n\t" 211 "cache %[op], (8*%[n])(%[va2])" "\n\t" 212 "cache %[op], (9*%[n])(%[va1])" "\n\t" 213 "cache %[op], (9*%[n])(%[va2])" "\n\t" 214 "cache %[op], (10*%[n])(%[va1])" "\n\t" 215 "cache %[op], (10*%[n])(%[va2])" "\n\t" 216 "cache %[op], (11*%[n])(%[va1])" "\n\t" 217 "cache %[op], (11*%[n])(%[va2])" "\n\t" 218 "cache %[op], (12*%[n])(%[va1])" "\n\t" 219 "cache %[op], (12*%[n])(%[va2])" "\n\t" 220 "cache %[op], (13*%[n])(%[va1])" "\n\t" 221 "cache %[op], (13*%[n])(%[va2])" "\n\t" 222 "cache %[op], (14*%[n])(%[va1])" "\n\t" 223 "cache %[op], (14*%[n])(%[va2])" "\n\t" 224 "cache %[op], (15*%[n])(%[va1])" "\n\t" 225 "cache %[op], (15*%[n])(%[va2])" "\n\t" 226 ".set pop" 227 : 228 : [va1] "r" (va1), [va2] "r" (va2), [op] "i" (op), [n] "n" (n) 229 : "memory"); 230 } 231 232 /* 233 * cache_r4k_op_16lines_16_2way: 234 * Perform the specified cache operation on 16 16-byte cache lines, 2-ways. 235 * cache_r4k_op_16lines_32_2way: 236 * Perform the specified cache operation on 16 32-byte cache lines, 2-ways. 237 */ 238 #define cache_r4k_op_16lines_16_2way(va1, va2, op) \ 239 cache_r4k_op_16lines_NN_2way(16, (va1), (va2), (op)) 240 #define cache_r4k_op_16lines_32_2way(va1, va2, op) \ 241 cache_r4k_op_16lines_NN_2way(32, (va1), (va2), (op)) 242 #define cache_r4k_op_16lines_64_2way(va1, va2, op) \ 243 cache_r4k_op_16lines_NN_2way(64, (va1), (va2), (op)) 244 245 /* 246 * cache_r4k_op_8lines_NN_4way: 247 * Perform the specified cache operation on 8 n-byte cache lines, 4-ways. 248 */ 249 static inline void 250 cache_r4k_op_8lines_NN_4way(size_t n, register_t va1, register_t va2, 251 register_t va3, register_t va4, u_int op) 252 { 253 __asm volatile( 254 ".set push" "\n\t" 255 ".set noreorder" "\n\t" 256 "cache %[op], (0*%[n])(%[va1])" "\n\t" 257 "cache %[op], (0*%[n])(%[va2])" "\n\t" 258 "cache %[op], (0*%[n])(%[va3])" "\n\t" 259 "cache %[op], (0*%[n])(%[va4])" "\n\t" 260 "cache %[op], (1*%[n])(%[va1])" "\n\t" 261 "cache %[op], (1*%[n])(%[va2])" "\n\t" 262 "cache %[op], (1*%[n])(%[va3])" "\n\t" 263 "cache %[op], (1*%[n])(%[va4])" "\n\t" 264 "cache %[op], (2*%[n])(%[va1])" "\n\t" 265 "cache %[op], (2*%[n])(%[va2])" "\n\t" 266 "cache %[op], (2*%[n])(%[va3])" "\n\t" 267 "cache %[op], (2*%[n])(%[va4])" "\n\t" 268 "cache %[op], (3*%[n])(%[va1])" "\n\t" 269 "cache %[op], (3*%[n])(%[va2])" "\n\t" 270 "cache %[op], (3*%[n])(%[va3])" "\n\t" 271 "cache %[op], (3*%[n])(%[va4])" "\n\t" 272 "cache %[op], (4*%[n])(%[va1])" "\n\t" 273 "cache %[op], (4*%[n])(%[va2])" "\n\t" 274 "cache %[op], (4*%[n])(%[va3])" "\n\t" 275 "cache %[op], (4*%[n])(%[va4])" "\n\t" 276 "cache %[op], (5*%[n])(%[va1])" "\n\t" 277 "cache %[op], (5*%[n])(%[va2])" "\n\t" 278 "cache %[op], (5*%[n])(%[va3])" "\n\t" 279 "cache %[op], (5*%[n])(%[va4])" "\n\t" 280 "cache %[op], (6*%[n])(%[va1])" "\n\t" 281 "cache %[op], (6*%[n])(%[va2])" "\n\t" 282 "cache %[op], (6*%[n])(%[va3])" "\n\t" 283 "cache %[op], (6*%[n])(%[va4])" "\n\t" 284 "cache %[op], (7*%[n])(%[va1])" "\n\t" 285 "cache %[op], (7*%[n])(%[va2])" "\n\t" 286 "cache %[op], (7*%[n])(%[va3])" "\n\t" 287 "cache %[op], (7*%[n])(%[va4])" "\n\t" 288 ".set pop" 289 : 290 : [va1] "r" (va1), [va2] "r" (va2), 291 [va3] "r" (va3), [va4] "r" (va4), 292 [op] "i" (op), [n] "n" (n) 293 : "memory"); 294 } 295 /* 296 * cache_r4k_op_8lines_16_4way: 297 * Perform the specified cache operation on 8 16-byte cache lines, 4-ways. 298 * cache_r4k_op_8lines_32_4way: 299 * Perform the specified cache operation on 8 32-byte cache lines, 4-ways. 300 */ 301 #define cache_r4k_op_8lines_16_4way(va1, va2, va3, va4, op) \ 302 cache_r4k_op_8lines_NN_4way(16, (va1), (va2), (va3), (va4), (op)) 303 #define cache_r4k_op_8lines_32_4way(va1, va2, va3, va4, op) \ 304 cache_r4k_op_8lines_NN_4way(32, (va1), (va2), (va3), (va4), (op)) 305 #define cache_r4k_op_8lines_64_4way(va1, va2, va3, va4, op) \ 306 cache_r4k_op_8lines_NN_4way(64, (va1), (va2), (va3), (va4), (op)) 307 #define cache_r4k_op_8lines_128_4way(va1, va2, va3, va4, op) \ 308 cache_r4k_op_8lines_NN_4way(128, (va1), (va2), (va3), (va4), (op)) 309 310 void r4k_icache_sync_all_16(void); 311 void r4k_icache_sync_range_16(register_t, vsize_t); 312 void r4k_icache_sync_range_index_16(vaddr_t, vsize_t); 313 314 void r4k_icache_sync_all_32(void); 315 void r4k_icache_sync_range_32(register_t, vsize_t); 316 void r4k_icache_sync_range_index_32(vaddr_t, vsize_t); 317 318 void r4k_pdcache_wbinv_all_16(void); 319 void r4k_pdcache_wbinv_range_16(register_t, vsize_t); 320 void r4k_pdcache_wbinv_range_index_16(vaddr_t, vsize_t); 321 322 void r4k_pdcache_inv_range_16(register_t, vsize_t); 323 void r4k_pdcache_wb_range_16(register_t, vsize_t); 324 325 void r4k_pdcache_wbinv_all_32(void); 326 void r4k_pdcache_wbinv_range_32(register_t, vsize_t); 327 void r4k_pdcache_wbinv_range_index_32(vaddr_t, vsize_t); 328 329 void r4k_pdcache_inv_range_32(register_t, vsize_t); 330 void r4k_pdcache_wb_range_32(register_t, vsize_t); 331 332 void r4k_sdcache_wbinv_all_32(void); 333 void r4k_sdcache_wbinv_range_32(register_t, vsize_t); 334 void r4k_sdcache_wbinv_range_index_32(vaddr_t, vsize_t); 335 336 void r4k_sdcache_inv_range_32(register_t, vsize_t); 337 void r4k_sdcache_wb_range_32(register_t, vsize_t); 338 339 void r4k_sdcache_wbinv_all_128(void); 340 void r4k_sdcache_wbinv_range_128(register_t, vsize_t); 341 void r4k_sdcache_wbinv_range_index_128(vaddr_t, vsize_t); 342 343 void r4k_sdcache_inv_range_128(register_t, vsize_t); 344 void r4k_sdcache_wb_range_128(register_t, vsize_t); 345 346 void r4k_sdcache_wbinv_all_generic(void); 347 void r4k_sdcache_wbinv_range_generic(register_t, vsize_t); 348 void r4k_sdcache_wbinv_range_index_generic(vaddr_t, vsize_t); 349 350 void r4k_sdcache_inv_range_generic(register_t, vsize_t); 351 void r4k_sdcache_wb_range_generic(register_t, vsize_t); 352 353 /* cache_r4k_pcache16.S */ 354 355 void cache_r4k_icache_index_inv_16(vaddr_t, vsize_t); 356 void cache_r4k_icache_hit_inv_16(register_t, vsize_t); 357 void cache_r4k_pdcache_index_wb_inv_16(vaddr_t, vsize_t); 358 void cache_r4k_pdcache_hit_inv_16(register_t, vsize_t); 359 void cache_r4k_pdcache_hit_wb_inv_16(register_t, vsize_t); 360 void cache_r4k_pdcache_hit_wb_16(register_t, vsize_t); 361 362 /* cache_r4k_pcache32.S */ 363 364 void cache_r4k_icache_index_inv_32(vaddr_t, vsize_t); 365 void cache_r4k_icache_hit_inv_32(register_t, vsize_t); 366 void cache_r4k_pdcache_index_wb_inv_32(vaddr_t, vsize_t); 367 void cache_r4k_pdcache_hit_inv_32(register_t, vsize_t); 368 void cache_r4k_pdcache_hit_wb_inv_32(register_t, vsize_t); 369 void cache_r4k_pdcache_hit_wb_32(register_t, vsize_t); 370 371 /* cache_r4k_pcache64.S */ 372 373 void cache_r4k_icache_index_inv_64(vaddr_t, vsize_t); 374 void cache_r4k_icache_hit_inv_64(register_t, vsize_t); 375 void cache_r4k_pdcache_index_wb_inv_64(vaddr_t, vsize_t); 376 void cache_r4k_pdcache_hit_inv_64(register_t, vsize_t); 377 void cache_r4k_pdcache_hit_wb_inv_64(register_t, vsize_t); 378 void cache_r4k_pdcache_hit_wb_64(register_t, vsize_t); 379 380 /* cache_r4k_pcache128.S */ 381 382 void cache_r4k_icache_index_inv_128(vaddr_t, vsize_t); 383 void cache_r4k_icache_hit_inv_128(register_t, vsize_t); 384 void cache_r4k_pdcache_index_wb_inv_128(vaddr_t, vsize_t); 385 void cache_r4k_pdcache_hit_inv_128(register_t, vsize_t); 386 void cache_r4k_pdcache_hit_wb_inv_128(register_t, vsize_t); 387 void cache_r4k_pdcache_hit_wb_128(register_t, vsize_t); 388 void cache_r4k_sdcache_index_wb_inv_128(vaddr_t, vsize_t); 389 void cache_r4k_sdcache_hit_inv_128(register_t, vsize_t); 390 void cache_r4k_sdcache_hit_wb_inv_128(register_t, vsize_t); 391 void cache_r4k_sdcache_hit_wb_128(register_t, vsize_t); 392 393 #endif /* !_LOCORE */ 394
Indexes created Thu Oct 02 01:09:59 GMT 2025