locore.h revision 1.100
1 /* $NetBSD: locore.h,v 1.100 2016/07/11 16:15:35 matt Exp $ */ 2 3 /* 4 * This file should not be included by MI code!!! 5 */ 6 7 /* 8 * Copyright 1996 The Board of Trustees of The Leland Stanford 9 * Junior University. All Rights Reserved. 10 * 11 * Permission to use, copy, modify, and distribute this 12 * software and its documentation for any purpose and without 13 * fee is hereby granted, provided that the above copyright 14 * notice appear in all copies. Stanford University 15 * makes no representations about the suitability of this 16 * software for any purpose. It is provided "as is" without 17 * express or implied warranty. 18 */ 19 20 /* 21 * Jump table for MIPS CPU locore functions that are implemented 22 * differently on different generations, or instruction-level 23 * architecture (ISA) level, the Mips family. 24 * 25 * We currently provide support for MIPS I and MIPS III. 26 */ 27 28 #ifndef _MIPS_LOCORE_H 29 #define _MIPS_LOCORE_H 30 31 #if !defined(_LKM) && defined(_KERNEL_OPT) 32 #include "opt_cputype.h" 33 #endif 34 35 #include <sys/cpu.h> 36 37 #include <mips/mutex.h> 38 #include <mips/cpuregs.h> 39 #include <mips/reg.h> 40 41 #ifndef __BSD_PTENTRY_T__ 42 #define __BSD_PTENTRY_T__ 43 typedef uint32_t pt_entry_t; 44 #define PRIxPTE PRIx32 45 #endif 46 47 #include <uvm/pmap/tlb.h> 48 49 #ifdef _KERNEL 50 51 #if defined(_MODULAR) || defined(_LKM) || defined(_STANDALONE) 52 /* Assume all CPU architectures are valid for LKM's and standlone progs */ 53 #if !defined(__mips_n32) && !defined(__mips_n64) 54 #define MIPS1 1 55 #endif 56 #define MIPS3 1 57 #define MIPS4 1 58 #if !defined(__mips_n32) && !defined(__mips_n64) 59 #define MIPS32 1 60 #define MIPS32R2 1 61 #endif 62 #define MIPS64 1 63 #define MIPS64R2 1 64 #endif /* _MODULAR || _LKM || _STANDALONE */ 65 66 #if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) == 0 67 #error at least one of MIPS1, MIPS3, MIPS4, MIPS32, MIPS32R2, MIPS64, or MIPS64R2 must be specified 68 #endif 69 70 /* Shortcut for MIPS3 or above defined */ 71 #if defined(MIPS3) || defined(MIPS4) \ 72 || defined(MIPS32) || defined(MIPS32R2) \ 73 || defined(MIPS64) || defined(MIPS64R2) 74 75 #define MIPS3_PLUS 1 76 #if !defined(MIPS32) && !defined(MIPS32R2) 77 #define MIPS3_64BIT 1 78 #endif 79 #if !defined(MIPS3) && !defined(MIPS4) 80 #define MIPSNN 1 81 #endif 82 #if defined(MIPS32R2) || defined(MIPS64R2) 83 #define MIPSNNR2 1 84 #endif 85 #else 86 #undef MIPS3_PLUS 87 #endif 88 89 #if !defined(MIPS3_PLUS) && (ENABLE_MIPS_8KB_PAGE + ENABLE_MIPS_16KB_PAGE) > 0 90 #error MIPS1 does not support non-4KB page sizes. 91 #endif 92 93 /* XXX simonb 94 * Should the following be in a cpu_info type structure? 95 * And how many of these are per-cpu vs. per-system? (Ie, 96 * we can assume that all cpus have the same mmu-type, but 97 * maybe not that all cpus run at the same clock speed. 98 * Some SGI's apparently support R12k and R14k in the same 99 * box.) 100 */ 101 struct mips_options { 102 const struct pridtab *mips_cpu; 103 104 u_int mips_cpu_arch; 105 u_int mips_cpu_mhz; /* CPU speed in MHz, estimated by mc_cpuspeed(). */ 106 u_int mips_cpu_flags; 107 u_int mips_num_tlb_entries; 108 mips_prid_t mips_cpu_id; 109 mips_prid_t mips_fpu_id; 110 bool mips_has_r4k_mmu; 111 bool mips_has_llsc; 112 u_int mips3_pg_shift; 113 u_int mips3_pg_cached; 114 u_int mips3_cca_devmem; 115 #ifdef MIPS3_PLUS 116 #ifndef __mips_o32 117 uint64_t mips3_xkphys_cached; 118 #endif 119 uint64_t mips3_tlb_vpn_mask; 120 uint64_t mips3_tlb_pfn_mask; 121 uint32_t mips3_tlb_pg_mask; 122 #endif 123 }; 124 125 /* 126 * Macros to find the CPU architecture we're on at run-time, 127 * or if possible, at compile-time. 128 */ 129 130 #define CPU_ARCH_MIPSx 0 /* XXX unknown */ 131 #define CPU_ARCH_MIPS1 (1 << 0) 132 #define CPU_ARCH_MIPS2 (1 << 1) 133 #define CPU_ARCH_MIPS3 (1 << 2) 134 #define CPU_ARCH_MIPS4 (1 << 3) 135 #define CPU_ARCH_MIPS5 (1 << 4) 136 #define CPU_ARCH_MIPS32 (1 << 5) 137 #define CPU_ARCH_MIPS64 (1 << 6) 138 #define CPU_ARCH_MIPS32R2 (1 << 7) 139 #define CPU_ARCH_MIPS64R2 (1 << 8) 140 141 #define CPU_MIPS_R4K_MMU 0x0001 142 #define CPU_MIPS_NO_LLSC 0x0002 143 #define CPU_MIPS_CAUSE_IV 0x0004 144 #define CPU_MIPS_HAVE_SPECIAL_CCA 0x0008 /* Defaults to '3' if not set. */ 145 #define CPU_MIPS_CACHED_CCA_MASK 0x0070 146 #define CPU_MIPS_CACHED_CCA_SHIFT 4 147 #define CPU_MIPS_DOUBLE_COUNT 0x0080 /* 1 cp0 count == 2 clock cycles */ 148 #define CPU_MIPS_USE_WAIT 0x0100 /* Use "wait"-based cpu_idle() */ 149 #define CPU_MIPS_NO_WAIT 0x0200 /* Inverse of previous, for mips32/64 */ 150 #define CPU_MIPS_D_CACHE_COHERENT 0x0400 /* D-cache is fully coherent */ 151 #define CPU_MIPS_I_D_CACHE_COHERENT 0x0800 /* I-cache funcs don't need to flush the D-cache */ 152 #define CPU_MIPS_NO_LLADDR 0x1000 153 #define CPU_MIPS_HAVE_MxCR 0x2000 /* have mfcr, mtcr insns */ 154 #define CPU_MIPS_LOONGSON2 0x4000 155 #define MIPS_NOT_SUPP 0x8000 156 #define CPU_MIPS_HAVE_DSP 0x10000 157 158 #endif /* !_LOCORE */ 159 160 #if ((MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) == 1) || defined(_LOCORE) 161 162 #if defined(MIPS1) 163 164 # define CPUISMIPS3 0 165 # define CPUIS64BITS 0 166 # define CPUISMIPS32 0 167 # define CPUISMIPS32R2 0 168 # define CPUISMIPS64 0 169 # define CPUISMIPS64R2 0 170 # define CPUISMIPSNN 0 171 # define CPUISMIPSNNR2 0 172 # define MIPS_HAS_R4K_MMU 0 173 # define MIPS_HAS_CLOCK 0 174 # define MIPS_HAS_LLSC 0 175 # define MIPS_HAS_LLADDR 0 176 # define MIPS_HAS_DSP 0 177 # define MIPS_HAS_LMMI 0 178 179 #elif defined(MIPS3) || defined(MIPS4) 180 181 # define CPUISMIPS3 1 182 # define CPUIS64BITS 1 183 # define CPUISMIPS32 0 184 # define CPUISMIPS32R2 0 185 # define CPUISMIPS64 0 186 # define CPUISMIPS64R2 0 187 # define CPUISMIPSNN 0 188 # define CPUISMIPSNNR2 0 189 # define MIPS_HAS_R4K_MMU 1 190 # define MIPS_HAS_CLOCK 1 191 # if defined(_LOCORE) 192 # if !defined(MIPS3_4100) 193 # define MIPS_HAS_LLSC 1 194 # else 195 # define MIPS_HAS_LLSC 0 196 # endif 197 # else /* _LOCORE */ 198 # define MIPS_HAS_LLSC (mips_options.mips_has_llsc) 199 # endif /* _LOCORE */ 200 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 201 # define MIPS_HAS_DSP 0 202 # if defined(MIPS3_LOONGSON2) 203 # define MIPS_HAS_LMMI ((mips_options.mips_cpu_flags & CPU_MIPS_LOONGSON2) != 0) 204 # else 205 # define MIPS_HAS_LMMI 0 206 # endif 207 #elif defined(MIPS32) 208 209 # define CPUISMIPS3 1 210 # define CPUIS64BITS 0 211 # define CPUISMIPS32 1 212 # define CPUISMIPS32R2 0 213 # define CPUISMIPS64 0 214 # define CPUISMIPS64R2 0 215 # define CPUISMIPSNN 1 216 # define CPUISMIPSNNR2 0 217 # define MIPS_HAS_R4K_MMU 1 218 # define MIPS_HAS_CLOCK 1 219 # define MIPS_HAS_LLSC 1 220 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 221 # define MIPS_HAS_DSP 0 222 # define MIPS_HAS_LMMI 0 223 224 #elif defined(MIPS32R2) 225 226 # define CPUISMIPS3 1 227 # define CPUIS64BITS 0 228 # define CPUISMIPS32 0 229 # define CPUISMIPS32R2 1 230 # define CPUISMIPS64 0 231 # define CPUISMIPS64R2 0 232 # define CPUISMIPSNN 1 233 # define CPUISMIPSNNR2 1 234 # define MIPS_HAS_R4K_MMU 1 235 # define MIPS_HAS_CLOCK 1 236 # define MIPS_HAS_LLSC 1 237 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 238 # define MIPS_HAS_DSP (mips_options.mips_cpu_flags & CPU_MIPS_HAVE_DSP) 239 # define MIPS_HAS_LMMI 0 240 241 #elif defined(MIPS64) 242 243 # define CPUISMIPS3 1 244 # define CPUIS64BITS 1 245 # define CPUISMIPS32 0 246 # define CPUISMIPS32R2 0 247 # define CPUISMIPS64 1 248 # define CPUISMIPS64R2 0 249 # define CPUISMIPSNN 1 250 # define CPUISMIPSNNR2 0 251 # define MIPS_HAS_R4K_MMU 1 252 # define MIPS_HAS_CLOCK 1 253 # define MIPS_HAS_LLSC 1 254 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 255 # define MIPS_HAS_DSP 0 256 # define MIPS_HAS_LMMI 0 257 258 #elif defined(MIPS64R2) 259 260 # define CPUISMIPS3 1 261 # define CPUIS64BITS 1 262 # define CPUISMIPS32 0 263 # define CPUISMIPS32R2 0 264 # define CPUISMIPS64 0 265 # define CPUISMIPS64R2 1 266 # define CPUISMIPSNN 1 267 # define CPUISMIPSNNR2 1 268 # define MIPS_HAS_R4K_MMU 1 269 # define MIPS_HAS_CLOCK 1 270 # define MIPS_HAS_LLSC 1 271 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 272 # define MIPS_HAS_DSP (mips_options.mips_cpu_flags & CPU_MIPS_HAVE_DSP) 273 # define MIPS_HAS_LMMI 0 274 275 #endif 276 277 #else /* run-time test */ 278 279 #ifdef MIPS1 280 #define MIPS_HAS_R4K_MMU (mips_options.mips_has_r4k_mmu) 281 #define MIPS_HAS_LLSC (mips_options.mips_has_llsc) 282 #else 283 #define MIPS_HAS_R4K_MMU 1 284 #if !defined(MIPS3_4100) 285 #define MIPS_HAS_LLSC 1 286 #else 287 #define MIPS_HAS_LLSC (mips_options.mips_has_llsc) 288 #endif 289 #endif 290 #define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 291 #define MIPS_HAS_DSP (mips_options.mips_cpu_flags & CPU_MIPS_HAVE_DSP) 292 293 /* This test is ... rather bogus */ 294 #define CPUISMIPS3 ((mips_options.mips_cpu_arch & \ 295 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 296 297 /* And these aren't much better while the previous test exists as is... */ 298 #define CPUISMIPS4 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS4) != 0) 299 #define CPUISMIPS5 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS5) != 0) 300 #define CPUISMIPS32 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS32) != 0) 301 #define CPUISMIPS32R2 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS32R2) != 0) 302 #define CPUISMIPS64 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS64) != 0) 303 #define CPUISMIPS64R2 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS64R2) != 0) 304 #define CPUISMIPSNN ((mips_options.mips_cpu_arch & (CPU_ARCH_MIPS32 | CPU_ARCH_MIPS32R2 | CPU_ARCH_MIPS64 | CPU_ARCH_MIPS64R2)) != 0) 305 #define CPUIS64BITS ((mips_options.mips_cpu_arch & \ 306 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS64 | CPU_ARCH_MIPS64R2)) != 0) 307 308 #define MIPS_HAS_CLOCK (mips_options.mips_cpu_arch >= CPU_ARCH_MIPS3) 309 310 #endif /* run-time test */ 311 312 struct tlbmask; 313 struct trapframe; 314 315 void trap(uint32_t, uint32_t, vaddr_t, vaddr_t, struct trapframe *); 316 void ast(void); 317 318 void mips_fpu_trap(vaddr_t, struct trapframe *); 319 void mips_fpu_intr(vaddr_t, struct trapframe *); 320 321 vaddr_t mips_emul_branch(struct trapframe *, vaddr_t, uint32_t, bool); 322 void mips_emul_inst(uint32_t, uint32_t, vaddr_t, struct trapframe *); 323 324 void mips_emul_fp(uint32_t, struct trapframe *, uint32_t); 325 void mips_emul_branchdelayslot(uint32_t, struct trapframe *, uint32_t); 326 327 void mips_emul_lwc0(uint32_t, struct trapframe *, uint32_t); 328 void mips_emul_swc0(uint32_t, struct trapframe *, uint32_t); 329 void mips_emul_special(uint32_t, struct trapframe *, uint32_t); 330 void mips_emul_special3(uint32_t, struct trapframe *, uint32_t); 331 332 void mips_emul_lwc1(uint32_t, struct trapframe *, uint32_t); 333 void mips_emul_swc1(uint32_t, struct trapframe *, uint32_t); 334 void mips_emul_ldc1(uint32_t, struct trapframe *, uint32_t); 335 void mips_emul_sdc1(uint32_t, struct trapframe *, uint32_t); 336 337 void mips_emul_lb(uint32_t, struct trapframe *, uint32_t); 338 void mips_emul_lbu(uint32_t, struct trapframe *, uint32_t); 339 void mips_emul_lh(uint32_t, struct trapframe *, uint32_t); 340 void mips_emul_lhu(uint32_t, struct trapframe *, uint32_t); 341 void mips_emul_lw(uint32_t, struct trapframe *, uint32_t); 342 void mips_emul_lwl(uint32_t, struct trapframe *, uint32_t); 343 void mips_emul_lwr(uint32_t, struct trapframe *, uint32_t); 344 #if defined(__mips_n32) || defined(__mips_n64) || defined(__mips_o64) 345 void mips_emul_lwu(uint32_t, struct trapframe *, uint32_t); 346 void mips_emul_ld(uint32_t, struct trapframe *, uint32_t); 347 void mips_emul_ldl(uint32_t, struct trapframe *, uint32_t); 348 void mips_emul_ldr(uint32_t, struct trapframe *, uint32_t); 349 #endif 350 void mips_emul_sb(uint32_t, struct trapframe *, uint32_t); 351 void mips_emul_sh(uint32_t, struct trapframe *, uint32_t); 352 void mips_emul_sw(uint32_t, struct trapframe *, uint32_t); 353 void mips_emul_swl(uint32_t, struct trapframe *, uint32_t); 354 void mips_emul_swr(uint32_t, struct trapframe *, uint32_t); 355 #if defined(__mips_n32) || defined(__mips_n64) || defined(__mips_o64) 356 void mips_emul_sd(uint32_t, struct trapframe *, uint32_t); 357 void mips_emul_sdl(uint32_t, struct trapframe *, uint32_t); 358 void mips_emul_sdr(uint32_t, struct trapframe *, uint32_t); 359 #endif 360 361 uint32_t mips_cp0_cause_read(void); 362 void mips_cp0_cause_write(uint32_t); 363 uint32_t mips_cp0_status_read(void); 364 void mips_cp0_status_write(uint32_t); 365 366 void softint_process(uint32_t); 367 void softint_fast_dispatch(struct lwp *, int); 368 369 /* 370 * Convert an address to an offset used in a MIPS jump instruction. The offset 371 * contains the low 28 bits (allowing a jump to anywhere within the same 256MB 372 * segment of address space) of the address but since mips instructions are 373 * always on a 4 byte boundary the low 2 bits are always zero so the 28 bits 374 * get shifted right by 2 bits leaving us with a 26 bit result. To make the 375 * offset, we shift left to clear the upper four bits and then right by 6. 376 */ 377 #define fixup_addr2offset(x) ((((uint32_t)(uintptr_t)(x)) << 4) >> 6) 378 typedef bool (*mips_fixup_callback_t)(int32_t, uint32_t [2], void *); 379 struct mips_jump_fixup_info { 380 uint32_t jfi_stub; 381 uint32_t jfi_real; 382 }; 383 384 void fixup_splcalls(void); /* splstubs.c */ 385 bool mips_fixup_exceptions(mips_fixup_callback_t, void *); 386 bool mips_fixup_zero_relative(int32_t, uint32_t [2], void *); 387 intptr_t 388 mips_fixup_addr(const uint32_t *); 389 void mips_fixup_stubs(uint32_t *, uint32_t *); 390 391 /* 392 * Define these stubs... 393 */ 394 void mips_cpu_switch_resume(struct lwp *); 395 void wbflush(void); 396 397 #ifdef MIPS1 398 void mips1_tlb_invalidate_all(void); 399 400 uint32_t tx3900_cp0_config_read(void); 401 #endif 402 403 #ifdef MIPS3_PLUS 404 uint32_t mips3_cp0_compare_read(void); 405 void mips3_cp0_compare_write(uint32_t); 406 407 uint32_t mips3_cp0_config_read(void); 408 void mips3_cp0_config_write(uint32_t); 409 410 #ifdef MIPSNN 411 uint32_t mipsNN_cp0_config1_read(void); 412 void mipsNN_cp0_config1_write(uint32_t); 413 uint32_t mipsNN_cp0_config2_read(void); 414 uint32_t mipsNN_cp0_config3_read(void); 415 uint32_t mipsNN_cp0_config4_read(void); 416 uint32_t mipsNN_cp0_config5_read(void); 417 uint32_t mipsNN_cp0_config6_read(void); 418 uint32_t mipsNN_cp0_config7_read(void); 419 420 intptr_t mipsNN_cp0_watchlo_read(u_int); 421 void mipsNN_cp0_watchlo_write(u_int, intptr_t); 422 uint32_t mipsNN_cp0_watchhi_read(u_int); 423 void mipsNN_cp0_watchhi_write(u_int, uint32_t); 424 425 int32_t mipsNN_cp0_ebase_read(void); 426 void mipsNN_cp0_ebase_write(int32_t); 427 428 #ifdef MIPSNNR2 429 void mipsNN_cp0_hwrena_write(uint32_t); 430 void mipsNN_cp0_userlocal_write(void *); 431 #endif 432 #endif /* MIPSNN */ 433 434 uint32_t mips3_cp0_count_read(void); 435 void mips3_cp0_count_write(uint32_t); 436 437 uint32_t mips3_cp0_wired_read(void); 438 void mips3_cp0_wired_write(uint32_t); 439 void mips3_cp0_pg_mask_write(uint32_t); 440 441 #endif /* MIPS3_PLUS */ 442 443 /* 64-bit address space accessor for n32, n64 ABI */ 444 /* 32-bit address space accessor for o32 ABI */ 445 static inline uint8_t mips_lbu(register_t addr) __unused; 446 static inline void mips_sb(register_t addr, uint8_t val) __unused; 447 static inline uint16_t mips_lhu(register_t addr) __unused; 448 static inline void mips_sh(register_t addr, uint16_t val) __unused; 449 static inline uint32_t mips_lwu(register_t addr) __unused; 450 static inline void mips_sw(register_t addr, uint32_t val) __unused; 451 #ifdef MIPS3_64BIT 452 #if defined(__mips_o32) 453 uint64_t mips3_ld(register_t addr); 454 void mips3_sd(register_t addr, uint64_t val); 455 #else 456 static inline uint64_t mips3_ld(register_t addr) __unused; 457 static inline void mips3_sd(register_t addr, uint64_t val) __unused; 458 #endif 459 #endif 460 461 static inline uint8_t 462 mips_lbu(register_t addr) 463 { 464 uint8_t rv; 465 #if defined(__mips_n32) 466 __asm volatile("lbu\t%0, 0(%1)" : "=r"(rv) : "d"(addr)); 467 #else 468 rv = *(const volatile uint8_t *)addr; 469 #endif 470 return rv; 471 } 472 473 static inline uint16_t 474 mips_lhu(register_t addr) 475 { 476 uint16_t rv; 477 #if defined(__mips_n32) 478 __asm volatile("lhu\t%0, 0(%1)" : "=r"(rv) : "d"(addr)); 479 #else 480 rv = *(const volatile uint16_t *)addr; 481 #endif 482 return rv; 483 } 484 485 static inline uint32_t 486 mips_lwu(register_t addr) 487 { 488 uint32_t rv; 489 #if defined(__mips_n32) 490 __asm volatile("lwu\t%0, 0(%1)" : "=r"(rv) : "d"(addr)); 491 #else 492 rv = *(const volatile uint32_t *)addr; 493 #endif 494 return (rv); 495 } 496 497 #if defined(MIPS3_64BIT) && !defined(__mips_o32) 498 static inline uint64_t 499 mips3_ld(register_t addr) 500 { 501 uint64_t rv; 502 #if defined(__mips_n32) 503 __asm volatile("ld\t%0, 0(%1)" : "=r"(rv) : "d"(addr)); 504 #elif defined(_LP64) 505 rv = *(const volatile uint64_t *)addr; 506 #else 507 #error unknown ABI 508 #endif 509 return (rv); 510 } 511 #endif /* MIPS3_64BIT && !__mips_o32 */ 512 513 static inline void 514 mips_sb(register_t addr, uint8_t val) 515 { 516 #if defined(__mips_n32) 517 __asm volatile("sb\t%1, 0(%0)" :: "d"(addr), "r"(val)); 518 #else 519 *(volatile uint8_t *)addr = val; 520 #endif 521 } 522 523 static inline void 524 mips_sh(register_t addr, uint16_t val) 525 { 526 #if defined(__mips_n32) 527 __asm volatile("sh\t%1, 0(%0)" :: "d"(addr), "r"(val)); 528 #else 529 *(volatile uint16_t *)addr = val; 530 #endif 531 } 532 533 static inline void 534 mips_sw(register_t addr, uint32_t val) 535 { 536 #if defined(__mips_n32) 537 __asm volatile("sw\t%1, 0(%0)" :: "d"(addr), "r"(val)); 538 #else 539 *(volatile uint32_t *)addr = val; 540 #endif 541 } 542 543 #if defined(MIPS3_64BIT) && !defined(__mips_o32) 544 static inline void 545 mips3_sd(register_t addr, uint64_t val) 546 { 547 #if defined(__mips_n32) 548 __asm volatile("sd\t%1, 0(%0)" :: "d"(addr), "r"(val)); 549 #else 550 *(volatile uint64_t *)addr = val; 551 #endif 552 } 553 #endif /* MIPS3_64BIT && !__mips_o32 */ 554 555 /* 556 * A vector with an entry for each mips-ISA-level dependent 557 * locore function, and macros which jump through it. 558 */ 559 typedef struct { 560 void (*ljv_cpu_switch_resume)(struct lwp *); 561 intptr_t ljv_lwp_trampoline; 562 void (*ljv_wbflush)(void); 563 tlb_asid_t (*ljv_tlb_get_asid)(void); 564 void (*ljv_tlb_set_asid)(tlb_asid_t pid); 565 void (*ljv_tlb_invalidate_asids)(tlb_asid_t, tlb_asid_t); 566 void (*ljv_tlb_invalidate_addr)(vaddr_t, tlb_asid_t); 567 void (*ljv_tlb_invalidate_globals)(void); 568 void (*ljv_tlb_invalidate_all)(void); 569 u_int (*ljv_tlb_record_asids)(u_long *, tlb_asid_t); 570 int (*ljv_tlb_update_addr)(vaddr_t, tlb_asid_t, pt_entry_t, bool); 571 void (*ljv_tlb_read_entry)(size_t, struct tlbmask *); 572 void (*ljv_tlb_write_entry)(size_t, const struct tlbmask *); 573 } mips_locore_jumpvec_t; 574 575 typedef struct { 576 u_int (*lav_atomic_cas_uint)(volatile u_int *, u_int, u_int); 577 u_long (*lav_atomic_cas_ulong)(volatile u_long *, u_long, u_long); 578 int (*lav_ucas_uint)(volatile u_int *, u_int, u_int, u_int *); 579 int (*lav_ucas_ulong)(volatile u_long *, u_long, u_long, u_long *); 580 void (*lav_mutex_enter)(kmutex_t *); 581 void (*lav_mutex_exit)(kmutex_t *); 582 void (*lav_mutex_spin_enter)(kmutex_t *); 583 void (*lav_mutex_spin_exit)(kmutex_t *); 584 } mips_locore_atomicvec_t; 585 586 void mips_set_wbflush(void (*)(void)); 587 void mips_wait_idle(void); 588 589 void stacktrace(void); 590 void logstacktrace(void); 591 592 struct cpu_info; 593 struct splsw; 594 595 struct locoresw { 596 void (*lsw_wbflush)(void); 597 void (*lsw_cpu_idle)(void); 598 int (*lsw_send_ipi)(struct cpu_info *, int); 599 void (*lsw_cpu_offline_md)(void); 600 void (*lsw_cpu_init)(struct cpu_info *); 601 void (*lsw_cpu_run)(struct cpu_info *); 602 int (*lsw_bus_error)(unsigned int); 603 }; 604 605 struct mips_vmfreelist { 606 paddr_t fl_start; 607 paddr_t fl_end; 608 int fl_freelist; 609 }; 610 611 struct cpu_info * 612 cpu_info_alloc(struct pmap_tlb_info *, cpuid_t, cpuid_t, cpuid_t, 613 cpuid_t); 614 void cpu_attach_common(device_t, struct cpu_info *); 615 void cpu_startup_common(void); 616 617 #ifdef MULTIPROCESSOR 618 void cpu_hatch(struct cpu_info *ci); 619 void cpu_trampoline(void); 620 void cpu_halt(void); 621 void cpu_halt_others(void); 622 void cpu_pause(struct reg *); 623 void cpu_pause_others(void); 624 void cpu_resume(cpuid_t); 625 void cpu_resume_others(void); 626 bool cpu_is_paused(cpuid_t); 627 void cpu_debug_dump(void); 628 629 extern kcpuset_t *cpus_running; 630 extern kcpuset_t *cpus_hatched; 631 extern kcpuset_t *cpus_paused; 632 extern kcpuset_t *cpus_resumed; 633 extern kcpuset_t *cpus_halted; 634 #endif 635 636 /* copy.S */ 637 int32_t kfetch_32(volatile uint32_t *, uint32_t); 638 int8_t ufetch_int8(void *); 639 int16_t ufetch_int16(void *); 640 int32_t ufetch_int32(void *); 641 uint8_t ufetch_uint8(void *); 642 uint16_t ufetch_uint16(void *); 643 uint32_t ufetch_uint32(void *); 644 int8_t ufetch_int8_intrsafe(void *); 645 int16_t ufetch_int16_intrsafe(void *); 646 int32_t ufetch_int32_intrsafe(void *); 647 uint8_t ufetch_uint8_intrsafe(void *); 648 uint16_t ufetch_uint16_intrsafe(void *); 649 uint32_t ufetch_uint32_intrsafe(void *); 650 #ifdef _LP64 651 int64_t ufetch_int64(void *); 652 uint64_t ufetch_uint64(void *); 653 int64_t ufetch_int64_intrsafe(void *); 654 uint64_t ufetch_uint64_intrsafe(void *); 655 #endif 656 char ufetch_char(void *); 657 short ufetch_short(void *); 658 int ufetch_int(void *); 659 long ufetch_long(void *); 660 char ufetch_char_intrsafe(void *); 661 short ufetch_short_intrsafe(void *); 662 int ufetch_int_intrsafe(void *); 663 long ufetch_long_intrsafe(void *); 664 665 u_char ufetch_uchar(void *); 666 u_short ufetch_ushort(void *); 667 u_int ufetch_uint(void *); 668 u_long ufetch_ulong(void *); 669 u_char ufetch_uchar_intrsafe(void *); 670 u_short ufetch_ushort_intrsafe(void *); 671 u_int ufetch_uint_intrsafe(void *); 672 u_long ufetch_ulong_intrsafe(void *); 673 void *ufetch_ptr(void *); 674 675 int ustore_int8(void *, int8_t); 676 int ustore_int16(void *, int16_t); 677 int ustore_int32(void *, int32_t); 678 int ustore_uint8(void *, uint8_t); 679 int ustore_uint16(void *, uint16_t); 680 int ustore_uint32(void *, uint32_t); 681 int ustore_int8_intrsafe(void *, int8_t); 682 int ustore_int16_intrsafe(void *, int16_t); 683 int ustore_int32_intrsafe(void *, int32_t); 684 int ustore_uint8_intrsafe(void *, uint8_t); 685 int ustore_uint16_intrsafe(void *, uint16_t); 686 int ustore_uint32_intrsafe(void *, uint32_t); 687 #ifdef _LP64 688 int ustore_int64(void *, int64_t); 689 int ustore_uint64(void *, uint64_t); 690 int ustore_int64_intrsafe(void *, int64_t); 691 int ustore_uint64_intrsafe(void *, uint64_t); 692 #endif 693 int ustore_char(void *, char); 694 int ustore_char_intrsafe(void *, char); 695 int ustore_short(void *, short); 696 int ustore_short_intrsafe(void *, short); 697 int ustore_int(void *, int); 698 int ustore_int_intrsafe(void *, int); 699 int ustore_long(void *, long); 700 int ustore_long_intrsafe(void *, long); 701 int ustore_uchar(void *, u_char); 702 int ustore_uchar_intrsafe(void *, u_char); 703 int ustore_ushort(void *, u_short); 704 int ustore_ushort_intrsafe(void *, u_short); 705 int ustore_uint(void *, u_int); 706 int ustore_uint_intrsafe(void *, u_int); 707 int ustore_ulong(void *, u_long); 708 int ustore_ulong_intrsafe(void *, u_long); 709 int ustore_ptr(void *, void *); 710 int ustore_ptr_intrsafe(void *, void *); 711 712 int ustore_uint32_isync(void *, uint32_t); 713 714 /* trap.c */ 715 void netintr(void); 716 int kdbpeek(vaddr_t); 717 718 /* mips_dsp.c */ 719 void dsp_init(void); 720 void dsp_discard(void); 721 void dsp_load(void); 722 void dsp_save(void); 723 bool dsp_used_p(void); 724 extern const pcu_ops_t mips_dsp_ops; 725 726 /* mips_fpu.c */ 727 void fpu_init(void); 728 void fpu_discard(void); 729 void fpu_load(void); 730 void fpu_save(void); 731 bool fpu_used_p(void); 732 extern const pcu_ops_t mips_fpu_ops; 733 734 /* mips_machdep.c */ 735 void dumpsys(void); 736 int savectx(struct pcb *); 737 void cpu_identify(device_t); 738 739 /* locore*.S */ 740 int badaddr(void *, size_t); 741 int badaddr64(uint64_t, size_t); 742 743 /* vm_machdep.c */ 744 int ioaccess(vaddr_t, paddr_t, vsize_t); 745 int iounaccess(vaddr_t, vsize_t); 746 747 /* 748 * The "active" locore-function vector, and 749 */ 750 extern const mips_locore_atomicvec_t mips_llsc_locore_atomicvec; 751 752 extern mips_locore_atomicvec_t mips_locore_atomicvec; 753 extern mips_locore_jumpvec_t mips_locore_jumpvec; 754 extern struct locoresw mips_locoresw; 755 756 extern int mips_poolpage_vmfreelist; /* freelist to allocate poolpages */ 757 extern struct mips_options mips_options; 758 759 struct splsw; 760 struct mips_vmfreelist; 761 struct phys_ram_seg; 762 763 void mips64r2_vector_init(const struct splsw *); 764 void mips_vector_init(const struct splsw *, bool); 765 void mips_init_msgbuf(void); 766 void mips_init_lwp0_uarea(void); 767 void mips_page_physload(vaddr_t, vaddr_t, 768 const struct phys_ram_seg *, size_t, 769 const struct mips_vmfreelist *, size_t); 770 771 772 /* 773 * CPU identification, from PRID register. 774 */ 775 #define MIPS_PRID_REV(x) (((x) >> 0) & 0x00ff) 776 #define MIPS_PRID_IMPL(x) (((x) >> 8) & 0x00ff) 777 778 /* pre-MIPS32/64 */ 779 #define MIPS_PRID_RSVD(x) (((x) >> 16) & 0xffff) 780 #define MIPS_PRID_REV_MIN(x) ((MIPS_PRID_REV(x) >> 0) & 0x0f) 781 #define MIPS_PRID_REV_MAJ(x) ((MIPS_PRID_REV(x) >> 4) & 0x0f) 782 783 /* MIPS32/64 */ 784 #define MIPS_PRID_CID(x) (((x) >> 16) & 0x00ff) /* Company ID */ 785 #define MIPS_PRID_CID_PREHISTORIC 0x00 /* Not MIPS32/64 */ 786 #define MIPS_PRID_CID_MTI 0x01 /* MIPS Technologies, Inc. */ 787 #define MIPS_PRID_CID_BROADCOM 0x02 /* Broadcom */ 788 #define MIPS_PRID_CID_ALCHEMY 0x03 /* Alchemy Semiconductor */ 789 #define MIPS_PRID_CID_SIBYTE 0x04 /* SiByte */ 790 #define MIPS_PRID_CID_SANDCRAFT 0x05 /* SandCraft */ 791 #define MIPS_PRID_CID_PHILIPS 0x06 /* Philips */ 792 #define MIPS_PRID_CID_TOSHIBA 0x07 /* Toshiba */ 793 #define MIPS_PRID_CID_MICROSOFT 0x07 /* Microsoft also, sigh */ 794 #define MIPS_PRID_CID_LSI 0x08 /* LSI */ 795 /* 0x09 unannounced */ 796 /* 0x0a unannounced */ 797 #define MIPS_PRID_CID_LEXRA 0x0b /* Lexra */ 798 #define MIPS_PRID_CID_RMI 0x0c /* RMI / NetLogic */ 799 #define MIPS_PRID_CID_CAVIUM 0x0d /* Cavium */ 800 #define MIPS_PRID_CID_INGENIC 0xe1 801 #define MIPS_PRID_COPTS(x) (((x) >> 24) & 0x00ff) /* Company Options */ 802 803 #ifdef _KERNEL 804 /* 805 * Global variables used to communicate CPU type, and parameters 806 * such as cache size, from locore to higher-level code (e.g., pmap). 807 */ 808 void mips_pagecopy(register_t dst, register_t src); 809 void mips_pagezero(register_t dst); 810 811 #ifdef __HAVE_MIPS_MACHDEP_CACHE_CONFIG 812 void mips_machdep_cache_config(void); 813 #endif 814 815 /* 816 * trapframe argument passed to trap() 817 */ 818 819 #if 0 820 #define TF_AST 0 /* really zero */ 821 #define TF_V0 _R_V0 822 #define TF_V1 _R_V1 823 #define TF_A0 _R_A0 824 #define TF_A1 _R_A1 825 #define TF_A2 _R_A2 826 #define TF_A3 _R_A3 827 #define TF_T0 _R_T0 828 #define TF_T1 _R_T1 829 #define TF_T2 _R_T2 830 #define TF_T3 _R_T3 831 832 #if defined(__mips_n32) || defined(__mips_n64) 833 #define TF_A4 _R_A4 834 #define TF_A5 _R_A5 835 #define TF_A6 _R_A6 836 #define TF_A7 _R_A7 837 #else 838 #define TF_T4 _R_T4 839 #define TF_T5 _R_T5 840 #define TF_T6 _R_T6 841 #define TF_T7 _R_T7 842 #endif /* __mips_n32 || __mips_n64 */ 843 844 #define TF_TA0 _R_TA0 845 #define TF_TA1 _R_TA1 846 #define TF_TA2 _R_TA2 847 #define TF_TA3 _R_TA3 848 849 #define TF_T8 _R_T8 850 #define TF_T9 _R_T9 851 852 #define TF_RA _R_RA 853 #define TF_SR _R_SR 854 #define TF_MULLO _R_MULLO 855 #define TF_MULHI _R_MULLO 856 #define TF_EPC _R_PC /* may be changed by trap() call */ 857 858 #define TF_NREGS (sizeof(struct reg) / sizeof(mips_reg_t)) 859 #endif 860 861 struct trapframe { 862 struct reg tf_registers; 863 #define tf_regs tf_registers.r_regs 864 uint32_t tf_ppl; /* previous priority level */ 865 mips_reg_t tf_pad; /* for 8 byte aligned */ 866 }; 867 868 CTASSERT(sizeof(struct trapframe) % (4*sizeof(mips_reg_t)) == 0); 869 870 /* 871 * Stack frame for kernel traps. four args passed in registers. 872 * A trapframe is pointed to by the 5th arg, and a dummy sixth argument 873 * is used to avoid alignment problems 874 */ 875 876 struct kernframe { 877 #if defined(__mips_o32) || defined(__mips_o64) 878 register_t cf_args[4 + 1]; 879 #if defined(__mips_o32) 880 register_t cf_pad; /* (for 8 byte alignment) */ 881 #endif 882 #endif 883 #if defined(__mips_n32) || defined(__mips_n64) 884 register_t cf_pad[2]; /* for 16 byte alignment */ 885 #endif 886 register_t cf_sp; 887 register_t cf_ra; 888 struct trapframe cf_frame; 889 }; 890 891 CTASSERT(sizeof(struct kernframe) % (2*sizeof(mips_reg_t)) == 0); 892 893 /* 894 * PRocessor IDentity TABle 895 */ 896 897 struct pridtab { 898 int cpu_cid; 899 int cpu_pid; 900 int cpu_rev; /* -1 == wildcard */ 901 int cpu_copts; /* -1 == wildcard */ 902 int cpu_isa; /* -1 == probed (mips32/mips64) */ 903 int cpu_ntlb; /* -1 == unknown, 0 == probed */ 904 int cpu_flags; 905 u_int cpu_cp0flags; /* presence of some cp0 regs */ 906 u_int cpu_cidflags; /* company-specific flags */ 907 const char *cpu_name; 908 }; 909 910 /* 911 * bitfield defines for cpu_cp0flags 912 */ 913 #define MIPS_CP0FL_USE __BIT(0) /* use these flags */ 914 #define MIPS_CP0FL_ECC __BIT(1) 915 #define MIPS_CP0FL_CACHE_ERR __BIT(2) 916 #define MIPS_CP0FL_EIRR __BIT(3) 917 #define MIPS_CP0FL_EIMR __BIT(4) 918 #define MIPS_CP0FL_EBASE __BIT(5) 919 #define MIPS_CP0FL_CONFIG __BIT(6) 920 #define MIPS_CP0FL_CONFIG1 __BIT(7) 921 #define MIPS_CP0FL_CONFIG2 __BIT(8) 922 #define MIPS_CP0FL_CONFIG3 __BIT(9) 923 #define MIPS_CP0FL_CONFIG4 __BIT(10) 924 #define MIPS_CP0FL_CONFIG5 __BIT(11) 925 #define MIPS_CP0FL_CONFIG6 __BIT(12) 926 #define MIPS_CP0FL_CONFIG7 __BIT(13) 927 #define MIPS_CP0FL_USERLOCAL __BIT(14) 928 #define MIPS_CP0FL_HWRENA __BIT(15) 929 930 /* 931 * cpu_cidflags defines, by company 932 */ 933 /* 934 * RMI company-specific cpu_cidflags 935 */ 936 #define MIPS_CIDFL_RMI_TYPE __BITS(2,0) 937 # define CIDFL_RMI_TYPE_XLR 0 938 # define CIDFL_RMI_TYPE_XLS 1 939 # define CIDFL_RMI_TYPE_XLP 2 940 #define MIPS_CIDFL_RMI_THREADS_MASK __BITS(6,3) 941 # define MIPS_CIDFL_RMI_THREADS_SHIFT 3 942 #define MIPS_CIDFL_RMI_CORES_MASK __BITS(10,7) 943 # define MIPS_CIDFL_RMI_CORES_SHIFT 7 944 # define LOG2_1 0 945 # define LOG2_2 1 946 # define LOG2_4 2 947 # define LOG2_8 3 948 # define MIPS_CIDFL_RMI_CPUS(ncores, nthreads) \ 949 ((LOG2_ ## ncores << MIPS_CIDFL_RMI_CORES_SHIFT) \ 950 |(LOG2_ ## nthreads << MIPS_CIDFL_RMI_THREADS_SHIFT)) 951 # define MIPS_CIDFL_RMI_NTHREADS(cidfl) \ 952 (1 << (((cidfl) & MIPS_CIDFL_RMI_THREADS_MASK) \ 953 >> MIPS_CIDFL_RMI_THREADS_SHIFT)) 954 # define MIPS_CIDFL_RMI_NCORES(cidfl) \ 955 (1 << (((cidfl) & MIPS_CIDFL_RMI_CORES_MASK) \ 956 >> MIPS_CIDFL_RMI_CORES_SHIFT)) 957 #define MIPS_CIDFL_RMI_L2SZ_MASK __BITS(14,11) 958 # define MIPS_CIDFL_RMI_L2SZ_SHIFT 11 959 # define RMI_L2SZ_256KB 0 960 # define RMI_L2SZ_512KB 1 961 # define RMI_L2SZ_1MB 2 962 # define RMI_L2SZ_2MB 3 963 # define RMI_L2SZ_4MB 4 964 # define MIPS_CIDFL_RMI_L2(l2sz) \ 965 (RMI_L2SZ_ ## l2sz << MIPS_CIDFL_RMI_L2SZ_SHIFT) 966 # define MIPS_CIDFL_RMI_L2SZ(cidfl) \ 967 ((256*1024) << (((cidfl) & MIPS_CIDFL_RMI_L2SZ_MASK) \ 968 >> MIPS_CIDFL_RMI_L2SZ_SHIFT)) 969 970 #endif /* _KERNEL */ 971 972 #endif /* _MIPS_LOCORE_H */ 973
Indexes created Mon Sep 29 21:09:56 GMT 2025