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History log of /src/sys/arch/mips/include/locore.h
RevisionDateAuthorComments
 1.119  27-May-2021  simonb Rename the unhelpfully named mips_emul_lwc0() and mips_emul_swc0() to
mips_emul_ll() and mips_emul_sc(); make these static to mips_emul.c.
 1.118  12-May-2021  simonb Whitespace nit.
 1.117  02-Mar-2021  skrll branches: 1.117.4; 1.117.6;
Ensure the "memory" clobber is on inline assembly store operations

No binary change of note with this change in MALTA32
 1.116  22-Aug-2020  simonb branches: 1.116.2;
Invert the MIPS-I non-4kB page size check. The previous check doesn't
fail if both MIPS1 and MIPS3_PLUS are defined. Explictly check against
MIPS1.
 1.115  17-Aug-2020  mrg port crash(8) to mips. (most of the kernel side.)

- expose parts of _KERNEL to _KMEMUSER as well
- hide more things for _KERNEL
- avoid DB_MACHINE_COMMANDS in crash(8)
- XXX add mips_label_t for !_KERNEL and use it in the pcb to
avoid conflicting with the ddb/crash one
- enable dumppcb

some changes to make stack trace fail instead of SEGV and
the userland changes to crash itself not part of this change.
 1.114  15-Aug-2020  mrg move stacktrace_subr() from trap.c into new mips_stacktrace.c so
it can be shared between ddb, other mips kernel components (see
locore), and an upcoming crash(8) port.

remove second copy of kdbpeek() (hidden by old DDB_TRACE
option, but they're functionally equivalent.)

tested on octeon.

ok simonb@
 1.113  31-Jul-2020  simonb Fix a tyop. Thankfully this #define was unused.
 1.112  31-Jul-2020  simonb CP0 Config6 and Config7 aren't probeable. Adjust comments for these two.
 1.111  27-Jul-2020  skrll Fix typo _MODULAR -> _MODULE. Hopefully this fixes the builds.
 1.110  26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.109  23-Jul-2020  skrll unifdef -U_LKM
 1.108  23-Jul-2020  skrll Trailing whitespace
 1.107  14-Jun-2020  simonb Retire MIPS_CP0FL_USERLOCAL and MIPS_CP0FL_HWRENA and the flawed
logic that tried to deal with a MIPS processor that supports the ULR
CP0 register. Probe correctly and save probed info somewhere we can
actually use it. Avoids problems where libc expects ULR set to a
value but the CPU definition in the CPU table didn't have the right
combination of magic flags and thus never set ULR in the first place.
 1.106  13-Jun-2020  simonb Note some hard-coded capabilties that can be probed.

XXX: Fix this and CPU table in mips/mips_machdep.c one day...
 1.105  24-May-2020  simonb Add mipsNN_cp0_rdhwr_cpunum() which returns the current CPU number
read from the CPUNum hardware register on MIPS{32,64}R2.
 1.104  06-Apr-2019  thorpej Overhaul the API used to fetch and store individual memory cells in
userspace. The old fetch(9) and store(9) APIs (fubyte(), fuword(),
subyte(), suword(), etc.) are retired and replaced with new ufetch(9)
and ustore(9) APIs that can return proper error codes, etc. and are
implemented consistently across all platforms. The interrupt-safe
variants are no longer supported (and several of the existing attempts
at fuswintr(), etc. were buggy and not actually interrupt-safe).

Also augmement the ucas(9) API, making it consistently available on
all plaforms, supporting uniprocessor and multiprocessor systems, even
those that do not have CAS or LL/SC primitives.

Welcome to NetBSD 8.99.37.
 1.103  08-Feb-2018  bouyer branches: 1.103.4;
Allow kdbpeek() to return failure. If it does, stop the stack trace.
Prevents an infinite loop in ddb if something goes wrong.
 1.102  16-Mar-2017  chs allow pcu_save() and pcu_discard() to be called on other threads,
ptrace needs to use it that way.
 1.101  13-Oct-2016  macallan branches: 1.101.2;
sprinkle #ifndef __ASSEMBLER__ to make this file usable from .S - mostly for
macros like MIPS3_PLUS
 1.100  11-Jul-2016  matt branches: 1.100.2;
Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch
 1.99  09-Jun-2015  matt Fix mips_fixup_zero_relative to have a third argument (ignored).
When reading COP0 EBASE, verify that the fixed bits have the right value.
 1.98  01-Jun-2015  matt Rework cavium support in preparation for MULTIPROCESSOR support
 1.97  02-May-2015  matt mips_{l,s}d_a64 only valid for !O32
 1.96  01-May-2015  christos change #error to KASSERT
 1.95  29-Apr-2015  hikaru Initial import of Cavium Octeon and Octeon Plus SoC and
specifically Ubiquiti Networks EdgeRouter LITE support.
Currently the ethernet and uart are worked.
This support was contributed by Internet Initiative Japan Inc.
 1.94  22-Nov-2014  macallan branches: 1.94.2;
deal with Ingenic XBurst CPUs
 1.93  19-Feb-2012  rmind branches: 1.93.2;
Remove COMPAT_SA / KERN_SA. Welcome to 6.99.3!
Approved by core@.
 1.92  17-Aug-2011  matt branches: 1.92.2; 1.92.6;
Redo mips_fixup so that it can handle indirect loads and deal with loongson2
extra instructions.
 1.91  01-Jul-2011  dyoung Don't #include "opt_cputype.h" unless _KERNEL_OPT is #defined.
 1.90  29-Apr-2011  matt ras atomicvec is no more.
 1.89  14-Apr-2011  matt Fix printing of watch{lo,hi} and make mipsNN_watchlo_* use intptr_t so that
sign extention happens.
 1.88  14-Apr-2011  cliff - add lsw_cpu_run function pointer to struct locoresw
 1.87  12-Apr-2011  matt Add prototypes for mipsNN_cp0_watch{lo,hi}_{read,write}
 1.86  06-Apr-2011  matt Add a tiny bit of whitespace.
 1.85  15-Mar-2011  matt Add separate support for MIPS32R2 and MIPS64R2.
Use EHB/SSNOP and jr.hb ra as appropriate (COP0_SYNC now uses them).
Add support for COP_0_HWRENA and COP_0_USERLOCAL (use by rdhwr $3,$29
instruction for TLS support).
Add mips3+ reserved instruction handler to emulate rdhwr is many fewer
instructions.
 1.84  03-Mar-2011  matt Change MIPS_CP0FL_CONFIG*
Add MIPS_CP0FL_HWRENA and USERLOCAL
 1.83  20-Feb-2011  matt Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU
 1.82  26-Jan-2011  pooka Add support for the Extensible MIPS ("eMIPS") platform. The
NetBSD/emips port runs on Xilinx and Beecube FPGA systems and the
Giano system simulator.

eMIPS is a platform developed at Microsoft Research for researching
reconfigurable computing. eMIPS allows dynamic loading and scheduling
of application-specific circuits for the purpose of accelerating
computations based on the current workload.

NetBSD eMIPS support for NetBSD 4.x was written at Microsoft Research
by Alessandro Forin and Neil Pittman. Microsoft Corporation has
donated full copyright to The NetBSD Foundation.

Platform support for eMIPS is the first part of Microsoft's
contribution. The second part includes the hardware accelerator
framework and will be proposed on tech-kern soon.
 1.81  27-Feb-2010  snj branches: 1.81.2; 1.81.4; 1.81.6;
Fix a couple old typos in comments.
 1.80  14-Dec-2009  matt branches: 1.80.2;
Merge from matt-nb5-mips64
Merge mips-specific arch files.
 1.79  30-May-2009  martin Do not use the same trampoline for cpu_lwp_fork and cpu_setfunc - only
the former needs to call lwp_startup().
 1.78  17-Oct-2007  garbled branches: 1.78.20; 1.78.30; 1.78.36;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.
 1.77  17-Jun-2007  tsutsui branches: 1.77.10;
Move declaretions of _spl*() and _{clr,set}softintr() functions
(which are in mips/locore.S) into <mips/locore.h>
from various MD files.
 1.76  17-May-2007  yamt merge yamt-idlelwp branch. asked by core@. some ports still needs work.

from doc/BRANCHES:

idle lwp, and some changes depending on it.

1. separate context switching and thread scheduling.
(cf. gmcgarry_ctxsw)
2. implement idle lwp.
3. clean up related MD/MI interfaces.
4. make scheduler(s) modular.
 1.75  04-Mar-2007  christos branches: 1.75.2; 1.75.4; 1.75.10;
Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.
 1.74  16-Feb-2006  perry branches: 1.74.20;
Change "inline" back to "__inline" in .h files -- C99 is still too
new, and some apps compile things in C89 mode. C89 keywords stay.

As per core@.
 1.73  24-Dec-2005  perry branches: 1.73.2; 1.73.4; 1.73.6;
__asm__ -> __asm
__const__ -> const
__inline__ -> inline
__volatile__ -> volatile
 1.72  11-Dec-2005  christos merge ktrace-lwp.
 1.71  05-Nov-2005  tsutsui Add MI mips3 wired map functions based on patch in port-mips/31915
from Garrett D'Amore of Tadpole Computer Inc.
Please refer discussion filed in the PR for details.
 1.70  30-Oct-2005  tsutsui Use #define<space> for consistency.
 1.69  08-Sep-2005  tsutsui branches: 1.69.2;
Add mips3_cp0_pg_mask_write() to initialize pagemask register.
 1.68  13-Feb-2004  wiz branches: 1.68.6; 1.68.14; 1.68.16;
Uppercase CPU, plural is CPUs.
 1.67  29-Oct-2003  simonb Add some more MIPS vendor IDs.
 1.66  05-Oct-2003  tsutsui No need to include opt_mips_cache.h here.
 1.65  04-Nov-2002  thorpej branches: 1.65.6;
Use named indices for RA, SR, MULLO, MULHI, and EPC in the
trapframe.
 1.64  04-Nov-2002  thorpej Define named constants for the trapframe register idices (they
are different from the normal register numbers). Use these names
in genassym.cf. (Wow, how ever did that test kernel boot before...)
 1.63  03-Jun-2002  simonb Add prototypes for the 64-bit pagezero functions.
Bracket some function prototypes with #ifdef/#endif.
 1.62  01-Jun-2002  simonb Use CPU_MIPS_USE_WAIT and CPU_MIPS_NO_WAIT in the CPU table, and use
the generic name "mips_wait_idle" for the old function that had both
rm52xx_idle and mipsNN_idle entry points.
 1.61  13-May-2002  simonb branches: 1.61.2;
Add a comment after an #endif to match up with an #ifdef.
 1.60  11-Mar-2002  uch make this compile and work with MIPS3_5900.
 1.59  05-Mar-2002  simonb Add support for MIPS32 and MIPS64 architectures:
- Add mips32 and mips64 locore function prototypes.
- Add mips3_lw_a64() and mips3_sw_a64() for access data at any
64bit address (from Broadcom Corp).
- Add Broadcom and Sandcraft CPU company ids.
 1.58  14-Nov-2001  thorpej branches: 1.58.2;
Merge the thorpej-mips-cache branch onto the trunk. This is an
overhaul of how caches are handled for NetBSD's MIPS ports.
 1.57  16-Oct-2001  uch branches: 1.57.2;
R5900 support.
COP0_SYNC
In R5900 mtc0, tlbr, tlbp, tlbwi, tlbwr must be followed by sync.p.
if defined MIPS3_5900, COP0_SYNC is defined as sync.p. else nothing.
IPL_ICU_MASK
mask interrupt directly ICU instead of SR.IM.
I've added this feature to support software interrupt for R5900.
and this option may be useful for platform which has cascaded ICU.
 1.56  18-Aug-2001  simonb Reorder some function prototypes more logically.
 1.55  15-Aug-2001  simonb Add Alchemy and SiByte company IDs (from oss.sgi.com).
 1.54  15-Aug-2001  simonb Remove parameter names from function prototypes.
 1.53  11-Jun-2001  thorpej branches: 1.53.2;
Always indirect through the "locoresw" to get the cache ops, since
there are just far too many combinations to handle with magic
#ifdefs in any sane way. Also, add a HitFlushDCache op to the
"locoresw", and fill it in as appropriate (it's NULL on MIPS-I,
so watch out).

These changes ensure that my R4600 Indy (with 2-way cache) gets
the correct cache ops when the kernel is built with only MIPS3
support, resulting in a kernel that is significantly more stable.
 1.52  31-Oct-2000  jeffs branches: 1.52.2;
Add mips_pagecopy/zero assembly loops for use by pmap_copy/zero_page*()
to allow the almost-64-bit compilation use ld/sd.
 1.51  31-Oct-2000  jeffs Add mips_indexof() macro to make code for checking the cache index
easier to read.
 1.50  09-Oct-2000  nisimura mips1_ConfigCache() has gone.
 1.49  05-Oct-2000  cgd clean up and consistency for CP0 Count, Compare, Wired, and Config
access function names and prototypes.
 1.48  05-Oct-2000  cgd nuke mips3_clearBEV(). There's really no point in coding a
special-purpose assembly routine for things like this.
 1.47  05-Oct-2000  cgd tweak cpu_arch. Eliminate all direct checks of it (making them
use the macro CPUISMIPS3 -- which is badly misnamed), and set it
from #defines named CPU_ARCH_N (where N is 1..5, 32, 64).
 1.46  04-Oct-2000  cgd rename mips_read_causereg -> mips_cp0_cause_read. nuke prototype
for mips_read_statusreg (which was apparently never implemented).
Provide prototypes and implementations for mips_cp0_cause_write,
mips_cp0_status_read, and mips_cp0_status_write. (Writing can, of
course, be quite dangerous.)
 1.45  03-Oct-2000  cgd add some additional info re: MIPS32 PRID encoding, derived from
the ``MIPS32 4K Processor Core Family Software User's Manual
Revision 01.07 June 19, 2000", available on the web from:
http://www.mips.com/declassified/Declassified_2000/MD00016-2B-4K-SUM-01.07.pdf
 1.44  02-Oct-2000  cgd provide mips3_ld() and mips3_sd(), functions which provide safe wrappers
for mips3 (and later) 'ld' and 'sd' instructions. These currently
only are properly implemented for the _MIPS_BSD_API_LP32 and
_MIPS_BSD_API_LP32_64CLEAN 'API's. They're pretty messy, but when you
need them, you really need them.
 1.43  16-Sep-2000  nisimura Introduce new MIPS1 direct mapped cache capacity detection logics.
 1.42  16-Sep-2000  chuck IDT32364's Config register uses a different base for IC/DC (instruction
and data cache sizes). R4000 uses 2^(12+IC) and 2^(12+DC). IDT32364
uses 2^(9+IC) and 2^(9+DC).

abstract around the problem by making the base a parameter to the
MIPS3_CONFIG_CACHE_SIZE macro. we pass the base down from mips_vector_init
to mips3_vector_init and to mips3_ConfigCache (where it is used).

XXX: someone with an MIPS3_4100 should switch to this and get rid
of the ugly ifdefs in cpuregs.h
 1.41  13-Sep-2000  chuck kill mips3_write_xcontext_upper
 1.40  27-Jul-2000  cgd convert PRID handling to use macros on an int, not bit-fields.
there's no reason to use bit-fields, and they just complexity to
the header.
 1.39  20-Jul-2000  jeffs Make pmap_prefer() use a global setting based on cache size
instead of assuming 64KB. This allows best fit and will
support bigger caches.
 1.38  29-Jun-2000  cgd un-__P, clean up spacing a little bit, put fwd struct decl(s) near top
rather than embedded. no functional changes.
 1.37  26-Jun-2000  nisimura Abandon {mips1,mips3}_TBRPL()s which have little gain. They were
expected to be better than MachTLBUpdate(). After all, TLBUpdate()
is rather harmful and should be replaced with TBIS().
 1.36  20-Jun-2000  soda branches: 1.36.2;
3rd argument of TBRPL() is not paddr_t but PTE.
XXX - mips3_TBRPL seems to be never called.
 1.35  20-Jun-2000  soren Add mips3_write_config().
 1.34  06-Jun-2000  soren Rename RM5200 cache ops to mips3_*_2way in anticipation of using them
for other CPUs with 2-way set associative L1 caches as well.
 1.33  23-May-2000  soren branches: 1.33.2;
MachForceCacheUpdate and cacheflush_bug have never been used in NetBSD,
so remove references them, and do a little other cleanup.
 1.32  21-May-2000  soren Include opt_cputype.h.
 1.31  10-May-2000  nisimura Have mips_locoresw[] of 3 entry pointer array for different
implementation of locore routines between MIPS1 and MIPS3. It's
independent from mips_locore_jumpvec_t which is for cache/TLB
manipulating routines peculiar to processor designs. mips_locore_jumpvec_t
will be replaced with "processor closures" encapsulating implementation
parameters (cpuinfo) and pointers to conventaion routines (cpuops),
eventually.
 1.30  12-Apr-2000  nisimura - Implement mips3_TBIAP().
- Remove obsoluted routines in locore_mips3.S
- addiu -> addu, andi -> and, ori -> or.
 1.29  28-Mar-2000  simonb Don't `extern' function declarations. While we're there, remove trailing
blank lines and white space.
 1.28  27-Mar-2000  nisimura Have TBIA/TBIAP an argument refering to a global variable instead
of a compile time constant.
 1.27  27-Mar-2000  nisimura - Rename some of TLB ops to have handy abbrivations hired from VAX and
ALPHA; mips1_TBIA, mips1_TBIAP, mips1_TBIS.
- Make sure TBIA and TBIAP ops to have an argument for the size of TLB
which varies across even for MIPS1 implementations.
- Nuke the unused cpu_isa field from processor personality list.

- XXX XXX XXX
it's less-than-optimal and likely a mistake to have TLBUpdate().
It's costy to try to invalidate a single TLB entry whenver a certain
PTE is going to be modified by traversing the entire TLB looking
for the modified PTE because the PTE in question is not in TLB in
most cases. ASID bump could do the invalidation smartly. Solution
is planned for now.
 1.26  23-Mar-2000  soren Make MIPS1+MIPS3 compile again.
 1.25  19-Mar-2000  soren Updated RM5231 cache code from Jeff Smith and Ethan Solomita at Geocast.
Many thanks.
 1.24  28-Jan-2000  takemura CPU specific idle hook and VR idle routine.
 1.23  09-Jan-2000  simonb Prototype stacktrace() and logstacktrace().
 1.22  12-Nov-1999  nisimura Make sure wbflush symbol treated as a C function call.
 1.21  25-Sep-1999  shin branches: 1.21.2; 1.21.4; 1.21.8;
Changes for NetBSD/hpcmips.

Support VR4100.
Support 16KB page.
Support CPU without FPU.

Fix virtual alias problem(physio() case).

[new options]

options MIPS3_4100 /* VR4100 core */
options MIPS_16K_PAGE /* enable kernel support for 16k pages */
options SOFTFLOAT /* No FPU; avoid touching FPU registers */
 1.20  24-Apr-1999  simonb Nuke register and remove trailling white space.
 1.19  27-Feb-1999  jonathan branches: 1.19.4;
Define C structures (struct kernframe, struct trapframe)
for kernel-to-user trapframe. Use C structs in genassym.cf.
 1.18  15-Jan-1999  castor * Add prototype for mips1_clean_tlb
* Add the correct version of locore_mips1.S [ See previous revision for
description of changes ]
* Use defopt'ed MIPS3_L2CACHE_ABSENT in mips_machdep.c and pmap.c
to avoid generating extraneous code.
* GC pmap_set_referenced in pmap.c
 1.17  15-Jan-1999  castor Protect defopt against -D_LKM
 1.16  14-Jan-1999  castor * Create mips_reg_t data type to allow register size to be
decoupled from long or int or long long. Define macros in asm.h to facilitate
choosing these on a port by port basis.

* Create <machine/pubassym.h> mechanism to allow jmp_buf structure size
to be calculated at system build time.

* Define _MIPS_BSD_SIM macro which specifies what calling style is appropritae
for the architecture. For 64-bit oriented systems set the Status Register
to allow 64-bit instructions.

* Remove UADDR related macros because kernel U structure is now mapped
normally.
* Separate cpu.h into cpu.h and cpuarch.h to keep things neat.
* Add support for QED 52xx processors
 1.15  06-Jan-1999  nisimura - Complete vm_offset_t purge for mips processor.
- bzero() -> memset() and bcopy() -> memcpy().
- Garbage collection in trap.c and db_interface.c.
 1.14  11-Sep-1998  jonathan branches: 1.14.2;
Changes to sys/arch/mips from ARC port, from Noriyuki Soda <soda@sra.co.jp>.
Adds (most) support for ARC platform to port-independent mips code.

Some changes (e.g., clean up of overlapping CPU/FPU ids) inspired by
comparison to the OpenBSD 2.1 codebase of Soda's ARC port.

Open issues:
* Still no support for r4600 or mipsIV CPUs with two-way L1 cache.
Code derived from Per Fogelstrom's OpenBSD source doesn't work
on mips3 pmaxes with L2 cache.

* Still some port-specific #ifdefs, for interrupt enable and
pmax L2 cache-size. Needs more thought, but overlaps with
work-in-progress by Tohru and Tsubai on spl()s and related stuff.
 1.13  23-Apr-1998  jonathan Commit change missed during Decsystem 5100 chagnes:

prototype declearation for method to override wbflush() callback
vector with model-specific code. Used on DEC r2000a machines with
writebuffers which indicate writebuffer drain via cp0 usability bit.
 1.12  22-Jun-1997  jonathan Fix typo mips3_mips_switch_exit.
 1.11  22-Jun-1997  jonathan Final changes for configuring MIPS1 and MIPS3 in a single kernel.

* cpuregs.h:
rename remaining VMMACH_xxx TLB macros to MIPS_TLB_xxx.
Add compile-time MIPS3-only, compile-time MIPS1-only, and
runtime (both) definitions for number of TLB ASIDs (tlb pids)
and shift count to extract a TLB pid.

* locore.h:
Delete unused vector slot for indexed TLB writes.
mips1 and mips3 TLBs are different enough that we have
to break them out at the caller anyway.

* Add compile-time MIPS3-only andcompile-time MIPS1-only
macros to call locore functions directly by name.
Use the existing method table only if

* mips/mips_machdep.c, mips/trap.c, mips/pmap.c, pmax/machdep.c:
Use MIPS3_ or MIPS1_ specific names for TLB pids in
mips3 and mips1 specific code paths (e.g., creating the kernel stack
for process 0).

Add `options MIPS3' to pmax/conf/GENERIC.
 1.10  21-Jun-1997  mhitch MachHitFlushDCache is gone.
 1.9  19-Jun-1997  mhitch More merged mips1/mips3 support:
Remove cpu-specific routines from locore.S and add them to locore_r2000.S
and locore_r4000.S. Add entries in locore jump vector table for switch_exit()
and the cpu_switch() context resume.
Add offsets into the jump vector to genassym.cf for use in locore.S.
 1.8  16-Jun-1997  jonathan Changes for configuring both MIPS1 and MIPS3, from a merge of
similar design and code by Jason Thorpe and Jonathan Stone.

NOTE: the kernel-stack-switching code and cacheflush() calls in
locore.S still use #ifdef MIPS3 and need more work.

mips/include/cpu.h:
Add CPUISMIPS3 for run-time tests of what CPU architecture level
we're running on.

mips/include/locore.h:
Add declarations of locore cache-size variables for ref/def toolchain.

mips/include/mips1_pte.h:
mips1 TLB bit definitions.

mips/include/mips3_pte.h:
mips3 TLB bit definitions.

mips/include/pte.h:
define accesor macros for TLB bits (e.g., mips_pg_m_bit(),
that expand to CPU constants if only one CPU arch is configured,
or to inline functions if both MIPS1 and MIPS3 are configured.

mips/mips/locore_r2000.S:
Use MIPS1_PG_xxx constants inside mips1-specific code.

mips/mips/locore_r4000.S:
Use MIPS3_PG_xxx constants inside mips3-specific code.

mips/mips/locore.S:
Use MIPS1_PG_xxx constants inside mips3-specific code.
Use MIPS1_PG_xxx constants inside mips1-specific code.
(Needs more work!)

mips/mips/{pmap.c,vm_machdep.c,trap.c}, pmax/pmax/machdep.c:
Use MIPS3_PG_xxx constants inside mips3-specific functions,
and MIPS1_PG_XXX inside mips1-specific code.
Otherwise, use mips_pg_XXX_bit() macros where they apply,
and use "if (CPUISMIPS3) { ... } else {... }" where they don't.

mips/mips/mips_machdep.c:
Import Michael Hitch's fixes from the pmax locore-init code
into mips_vector_init().

pmax/pmax/machdep.c:
Use generic mips_vector_init() locore vector-init function.
 1.7  16-Jun-1997  jonathan Garbage-collect redundant declarations:
mips/include/locore.h:
Add prototypes for HitFlushDCache() functions. Moe cpu_prid definition here.
mips/include/cpu.h:
remove cpu_prid definition.
pmax/pmax/machdep.c:
remove local protoypes of HitFlushDCache() functions.
mips/mips/vm_machdep.c, mips/mips/vm_machdep.c::
remove local protoypes of HitFlushDCache() functions.
 1.6  16-Jun-1997  jonathan Yet more merging:
* Move declaration of locore communcation variables (CPU family,
cache sizes, etc) to mips/include/locore.h. Delete from
pmax/include/cpu.h and older versions from pica/include/cpu.h.

* Move definitions of CLKF_BASEPRI, CLKF_USERMODE to mips/include/cpu.
* Delete duplicate definitions in pica/include/cpu.h, pmax/include/cpu.h.
 1.5  15-Jun-1997  mhitch DECstation MIPS3 support: wbflush() is cpu-dependent, need declaration from
machine/locore.h.
From Toru Nishimura: _FORKBRAINDAMAGE is gone, user process entered through
proc_trampoline() [also cpu-dependent].
 1.4  25-May-1997  jonathan lint: prototype blkclr __P((caddr_t val, int size)). Used in pmap code.
 1.3  13-Oct-1996  jonathan Rename mips CPU-family locore prefixes for case-consistency:
mips_r2000_, mips_R2000_ -> mips1_
mips_r4000_, mips_R4000_ -> mips3_
(which are also, for mnemonic reasons, consistent with gcc flag usage,
rather than using mipsI_ and mipsIII_).
 1.2  20-May-1996  jonathan * Move the declarations of mips locore functions from the pmax tree
to the mips tree.
* Add declarations of functions used by vm_machdep.c.
* Add declarations of functions printed by name in stack tracebacks.
* Add declarations of functions used by the model-independnet mips machdep.c
code.
 1.1  19-May-1996  jonathan Define the conventional pmax locore entry-point names to be calls through
an vector (struct) of function pointers. Add prototype declarations for
each vector entry.
Add declarations for the r2000 (MIPS-I) and r4000 (MIPS-III) locore
versions of the relevant functions.
 1.14.2.1  19-Nov-1998  nisimura - Forgot to commit many files for vm_offset_t purge last Monday.
 1.19.4.1  21-Jun-1999  thorpej Sync w/ -current.
 1.21.8.1  27-Dec-1999  wrstuden Pull up to last week's -current.
 1.21.4.1  15-Nov-1999  fvdl Sync with -current
 1.21.2.2  22-Nov-2000  bouyer Sync with HEAD.
 1.21.2.1  20-Nov-2000  bouyer Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.
 1.33.2.1  22-Jun-2000  minoura Sync w/ netbsd-1-5-base.
 1.36.2.3  22-Jun-2000  soren Apply lost section from previous pull-up.
 1.36.2.2  22-Jun-2000  soren Pull-up from trunk: correct _TBRPL() prototype and remove from pmap.c.
 1.36.2.1  20-Jun-2000  soren file locore.h was added on branch netbsd-1-5 on 2000-06-22 05:11:20 +0000
 1.52.2.1  21-Jun-2001  nathanw Catch up to -current.
 1.53.2.4  23-Jun-2002  jdolecek catch up with -current on kqueue branch
 1.53.2.3  16-Mar-2002  jdolecek Catch up with -current.
 1.53.2.2  10-Jan-2002  thorpej Sync kqueue branch with -current.
 1.53.2.1  25-Aug-2001  thorpej Merge Aug 24 -current into the kqueue branch.
 1.57.2.1  24-Oct-2001  thorpej Update for the new cache code. Some careful code review is needed
here, esp. by people who have done recent MIPS pmap hacking.
 1.58.2.4  11-Nov-2002  nathanw Catch up to -current
 1.58.2.3  20-Jun-2002  nathanw Catch up to -current.
 1.58.2.2  01-Apr-2002  nathanw Catch up to -current.
(CVS: It's not just a program. It's an adventure!)
 1.58.2.1  14-Nov-2001  nathanw file locore.h was added on branch nathanw_sa on 2002-04-01 07:40:58 +0000
 1.61.2.1  14-Jul-2002  gehenna catch up with -current.
 1.65.6.4  10-Nov-2005  skrll Sync with HEAD. Here we go again...
 1.65.6.3  21-Sep-2004  skrll Fix the sync with head I botched.
 1.65.6.2  18-Sep-2004  skrll Sync with HEAD.
 1.65.6.1  03-Aug-2004  skrll Sync with HEAD
 1.68.16.2  03-Sep-2007  yamt sync with head.
 1.68.16.1  21-Jun-2006  yamt sync with head.
 1.68.14.1  11-Sep-2005  tron Pull up following revision(s) (requested by tsutsui in ticket #758):
sys/arch/mips/include/locore.h: revision 1.69
sys/arch/mips/mips/locore_mips3.S: revision 1.87
Add mips3_cp0_pg_mask_write() to initialize pagemask register.
 1.68.6.1  13-Sep-2005  riz Pull up following revision(s) (requested by tsutsui in ticket #5829):
sys/arch/mips/include/locore.h: revision 1.69
sys/arch/mips/mips/locore_mips3.S: revision 1.87
Add mips3_cp0_pg_mask_write() to initialize pagemask register.
 1.69.2.1  02-Nov-2005  yamt sync with head.
 1.73.6.1  22-Apr-2006  simonb Sync with head.
 1.73.4.1  09-Sep-2006  rpaulo sync with head
 1.73.2.1  18-Feb-2006  yamt sync with head.
 1.74.20.2  18-Apr-2007  ad - Further adaptations to MIPS for the yamt-idlelwp branch.
- Make curlwp a register variable on MIPS.
 1.74.20.1  12-Mar-2007  rmind Sync with HEAD.
 1.75.10.2  26-Jun-2007  garbled Sync with HEAD.
 1.75.10.1  22-May-2007  matt Update to HEAD.
 1.75.4.1  11-Jul-2007  mjf Sync with head.
 1.75.2.2  15-Jul-2007  ad Sync with head.
 1.75.2.1  27-May-2007  ad Sync with head.
 1.77.10.1  06-Nov-2007  matt sync with HEAD
 1.78.36.1  09-Jun-2009  snj branches: 1.78.36.1.2;
Pull up following revision(s) (requested by martin in ticket #799):
sys/arch/mips/include/locore.h: revision 1.79
sys/arch/mips/mips/locore_mips1.S: revision 1.65
sys/arch/mips/mips/mipsX_subr.S: revision 1.28
sys/arch/mips/mips/mips_machdep.c: revision 1.211
sys/arch/mips/mips/vm_machdep.c: revision 1.123
Do not use the same trampoline for cpu_lwp_fork and cpu_setfunc - only
the former needs to call lwp_startup().
 1.78.36.1.2.36  09-Jul-2012  matt Add mips_cpu_switchto prototype.
 1.78.36.1.2.35  14-Feb-2012  matt Fix various LP64 thinkos.
 1.78.36.1.2.34  13-Feb-2012  matt Add mm_md_direct_mapped_virt (inverse of mm_md_direct_mapped_phys). Add a
third argument, vsize_t *, which, if not NULL, returns the amount of virtual
space left in that direct mapped segment.
Get rid most of the individual direct_mapped assert and use the above
routines instead.
Improve kernel core dump code.
 1.78.36.1.2.33  13-Feb-2012  matt Fix emulation to not panic when it encounters something it doesn't like.
(so running crashme won't crash the system).
Centralize the trapsignal processing so we can print out the trap info if
so desired.
Add a machdep.printfataltraps sysctl knob.
 1.78.36.1.2.32  09-Feb-2012  matt Update mips_fixup.c to version from -HEAD.
Move cpu_switchto to locore jumpvec and create a stub for it.
 1.78.36.1.2.31  23-Dec-2011  matt add more mipsNN_cp0_config{3,4,5,6,7}_{read,write}.
Add mips3_cp0_random_read().
Add L3 encoding for RMI.
 1.78.36.1.2.30  26-May-2011  matt Add MIPS64_RMIXL (XLR/XLS) and MIPS64R2_RMIXL (XLP). This allows the kernel
to treat this special which is needed for MP support. When accessing the TLB,
always lock the TLB before hand. If in the miss handlers, the TLB is already
locked let trap deal with the exeception.
 1.78.36.1.2.29  29-Apr-2011  matt Major merge to/from current.
Adds MIPS32/MIPS64 R2 support (24k, 74k, etc.) including COP0_USERLOCAL
Adds support for emulation of rdhwr $3,$29 instruction.
Major cleanup of SMP code. (stable on multi-core / single thread per core)
llsc locking code only used in MP capable kernels.
 1.78.36.1.2.28  29-Dec-2010  matt Add wbflush to jumpvec while leaving it in locoresw. This allows to
overwrite wbflush in locoresw but still be able to call it via jumpvec.
 1.78.36.1.2.27  29-Dec-2010  matt Janitorial work.
Move emulation prototypes here and get rid of StudLyCaps.
Remove kludgery for lwp/setfunc trampoline and just grab them of the damn
structure.
Make mips_locore_jumpvec contain the routines that don't get reassigned
and move wbflush to mips_locoresw since it does get overridden.
 1.78.36.1.2.26  22-Dec-2010  matt Rework how fixups are processed. Inside of generating a table, we just
scan kernel text for jumps to locations between (__stub_start, __stub_end]
and if found, we actually decode the instructions in the stub to find out
where the stub would eventually jump to and then patch the original jump
to jump directly to it bypassing the stub. This is slightly slower than
the previous method but it's a simplier and new stubs get automagically
handled.
 1.78.36.1.2.25  10-Jun-2010  cliff - add lsw_bus_error to struct locoresw, provides hook to call
for chip-specific bus error handling/decode from e.g. trap()
 1.78.36.1.2.24  11-May-2010  matt Use assembly since deref a 64bit value as a pointer does not make a
32bit compiler happy.
 1.78.36.1.2.23  11-May-2010  matt Need to turn KX for N32 kernels with mips3_lw_a64 and mips3_sw_a64
 1.78.36.1.2.22  21-Mar-2010  cliff mips_vector_init now takes an argument to specify splsw.
NULL specifies use the default 'std_splsw'
 1.78.36.1.2.21  01-Mar-2010  matt Add a chip-dependent hook to locorew which cpu_hatch will call to do some
initialization that can only be done while running on the local CPU.
 1.78.36.1.2.20  01-Mar-2010  matt Add secondary processor spinup support (cpu_trampoline is in locore_mips3.S).
Nuke lse_boot_secondary_processors (not needed).
Move cpu_info_store to cpu_subr.C
 1.78.36.1.2.19  01-Mar-2010  matt Rework fixups support a bit (add a convience macro, require fixups to be
sorted).
 1.78.36.1.2.18  28-Feb-2010  matt Split FPU support into separate file and keep internals private to that file.
Make it MPSAFE. Change interface to be very similar to what's used on other
architectures.
Add l_md.md_fpcpu to mdlwp (needed for MPSAFE)
Move pridtab from <mips/cpu.h> to <mips/locore.h>
Add initial common IPI dispatcher.
Split cpu_* routines from mips_machdep.c into cpu_subr.c
Add cpu_startup_common which has the code replicated in half-dozen
plus machdep.c files.
 1.78.36.1.2.17  28-Feb-2010  matt Add code which can change a direct jump to stub with an indirect call to
a direct jump to the actual routine.
 1.78.36.1.2.16  27-Feb-2010  matt Add mipsXX_tlb_enter which modifies/sets a specific TLB entry with a new
mapping (useful for wired TLB entries).
Add mips_fixup_exceptions which will walk through the exception vectors
and allows the fixup of any cpu_info references to be changed to a more
MP-friendly incarnation.
Define a common fixup method to use a wired TLB entry at -PAGE_SIZE allowing
direct loads using a negative based from the zero register.
Change varible pmap_tlb_info t pmap_tlb0_info.
 1.78.36.1.2.15  25-Feb-2010  matt Add mipsXX_tlb_record_asids - records what ASIDs have valid TLB entries in
the TLB.
Move some mips3 specific routines from locore.S to locore_mips3.S
 1.78.36.1.2.14  23-Feb-2010  matt Make sure <mips/locore.h> is not included by MI code.
Add send_ipi and cpu_offline_md hooks to locoresw.
Add MP support to pmap (pvlist locking, tlb locking).
Add TLB shootdown support (see comment at the top of mips/pmap_tlb.c).
Add mipsXX_tlb_invalidate_globals routine
 1.78.36.1.2.13  15-Feb-2010  matt Completely redo how interrupts and SPL are handled in NetBSD/mips.
[XXX locore_mips1.S still needs to adapted.]

Nested interrupts now work. Except for MIPS_SOFT_MASK and MIPS_SR_INT_IE,
how interrupts work is completely abstracted. spl is handled through the
mips_splsw table. Direct manipulation of the status register is no longer
done (except for MIPS_SR_INT_IE). A new <mips/intr.h> contains the common
IPL/IST/spl* definitions for all ports.

Interrupt delivery is completely different. Clock interrupts may interrupt
device interrupts. ci_idepth is now handled by the caller of cpu_intr as
are softints (both can be optimized/simplified in the case of interrupts of
usermode code). cpu_intr has new arguments and now get called at IPL_HIGH
with MIPS_SR_INT_IE set and its logic is:

void
cpu_intr(int ppl, vaddr_t pc, uint32_t status)
{
int ipl;
uint32_t pending;
while (ppl < (ipl = splintr(&pending))) {
splx(ipl); /* enable interrupts */
<handle pending interrupts>
(void)splhigh(); /* disable interrupts */
}
}

mipsX_subr.S has been reworked. All user handlers (user_intr, systemcall,
user_gen_exception) now use common return to usermode code in lwp_trampoline.
ast() has changed to void ast(void) since the previous pc argument was never
used.

The playstation IPL_ICU_MASK support has been nuked.
MIPS_DYNAMIC_STATUS_MASK may soon be nuked soon.

A bunch of debugging code was left conditionalized by PARANOIA. If this
code detects a bug, it will enter an infinite loop. It is expected that
the kernel will be debugged in a simulator or with a hardware debugger so
that the state at that point can be analyzed.
 1.78.36.1.2.12  05-Feb-2010  matt Add __HAVE_FAST_SOFTINTS support.
Add routine to remap an uarea via a direct-mapped address. This avoids
TLB machinations when swtching to/from the softint thread. This can only
be done for lwp which won't exit.
 1.78.36.1.2.11  01-Feb-2010  matt Merge frame into trapframe. While this costs a bit more stack space on
kernel exceptions, the resulting simplifications are worth it. This is
a step to fast softints and kernel preemption.

trapframe now includes a struct reg instead of a separate array of registers.
 1.78.36.1.2.10  20-Jan-2010  cyber Correct argument to assembly dsrl32 $Lx -> %Lx
 1.78.36.1.2.9  20-Jan-2010  matt Revamp things a bit. Move of the globals mips uses into either cpu_info,
mips_options, or mips_cache_info. Make MALT64 be able to boot MULTIPROCESSOR.
(some pmap MP work).
 1.78.36.1.2.8  15-Jan-2010  matt Get rid of most of the studly caps.
First to MULTIPROCESSOR support for pmap: move some pmap globals to cpu_info.
Define per-cpu ASID number spaces.
Remove some mips1/!mips1 difference in db_interface.c
Add mips32/64 knowledge to stacktrace.
 1.78.36.1.2.7  30-Dec-2009  matt Please segtab lookups into separate file.
Add mips_add_physload
Add mips_init_lwp0_uarea
cleanup lwp0/cpu_info_store initialization.
 1.78.36.1.2.6  13-Dec-2009  matt TLBUpdate (all forms) takes vaddr_t, uint32_t
 1.78.36.1.2.5  23-Nov-2009  matt mips3_ld/mips3_sd need to be passed a volatile uint64_t *
 1.78.36.1.2.4  05-Sep-2009  matt Change padding in kern_frame so it has quad-word (16 bytes) alignment.
Then when allocated on a stack, the stack keeps 16 byte alignment.
 1.78.36.1.2.3  30-Aug-2009  matt Add RMI company id.
Add some RMI processor ids.
Add CP0 EBASE defintion.
 1.78.36.1.2.2  21-Aug-2009  matt Define locoresw struct and use it.
Make tf_pad mips_reg_t since a register is stored in it.
remove argument save area from kernframe on NewABI.
 1.78.36.1.2.1  16-Aug-2009  matt Kill use of _MIPS_BSD_ABI - switch to __mips_<abi>
Use device_t where appropriate.
Remove magic numbers.
 1.78.30.1  09-Jun-2009  snj Pull up following revision(s) (requested by martin in ticket #799):
sys/arch/mips/include/locore.h: revision 1.79
sys/arch/mips/mips/locore_mips1.S: revision 1.65
sys/arch/mips/mips/mipsX_subr.S: revision 1.28
sys/arch/mips/mips/mips_machdep.c: revision 1.211
sys/arch/mips/mips/vm_machdep.c: revision 1.123
Do not use the same trampoline for cpu_lwp_fork and cpu_setfunc - only
the former needs to call lwp_startup().
 1.78.20.2  11-Mar-2010  yamt sync with head
 1.78.20.1  20-Jun-2009  yamt sync with head
 1.80.2.1  30-Apr-2010  uebayasi Sync with HEAD.
 1.81.6.2  05-Mar-2011  bouyer Sync with HEAD
 1.81.6.1  08-Feb-2011  bouyer Sync with HEAD
 1.81.4.1  06-Jun-2011  jruoho Sync with HEAD.
 1.81.2.3  31-May-2011  rmind sync with head
 1.81.2.2  21-Apr-2011  rmind sync with head
 1.81.2.1  05-Mar-2011  rmind sync with head
 1.92.6.1  24-Feb-2012  mrg sync to -current.
 1.92.2.1  17-Apr-2012  yamt sync with head
 1.93.2.1  03-Dec-2017  jdolecek update from HEAD
 1.94.2.5  28-Aug-2017  skrll Sync with HEAD
 1.94.2.4  05-Dec-2016  skrll Sync with HEAD
 1.94.2.3  05-Oct-2016  skrll Sync with HEAD
 1.94.2.2  22-Sep-2015  skrll Sync with HEAD
 1.94.2.1  06-Jun-2015  skrll Sync with HEAD
 1.100.2.2  20-Mar-2017  pgoyette Sync with HEAD
 1.100.2.1  04-Nov-2016  pgoyette Sync with HEAD
 1.101.2.1  21-Apr-2017  bouyer Sync with HEAD
 1.103.4.1  10-Jun-2019  christos Sync with HEAD
 1.116.2.1  03-Apr-2021  thorpej Sync with HEAD.
 1.117.6.1  31-May-2021  cjep sync with head
 1.117.4.2  17-Jun-2021  thorpej Sync w/ HEAD.
 1.117.4.1  13-May-2021  thorpej Sync with HEAD.

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