locore.h revision 1.105
1 /* $NetBSD: locore.h,v 1.105 2020/05/24 07:15:24 simonb Exp $ */ 2 3 /* 4 * This file should not be included by MI code!!! 5 */ 6 7 /* 8 * Copyright 1996 The Board of Trustees of The Leland Stanford 9 * Junior University. All Rights Reserved. 10 * 11 * Permission to use, copy, modify, and distribute this 12 * software and its documentation for any purpose and without 13 * fee is hereby granted, provided that the above copyright 14 * notice appear in all copies. Stanford University 15 * makes no representations about the suitability of this 16 * software for any purpose. It is provided "as is" without 17 * express or implied warranty. 18 */ 19 20 /* 21 * Jump table for MIPS CPU locore functions that are implemented 22 * differently on different generations, or instruction-level 23 * architecture (ISA) level, the Mips family. 24 * 25 * We currently provide support for MIPS I and MIPS III. 26 */ 27 28 #ifndef _MIPS_LOCORE_H 29 #define _MIPS_LOCORE_H 30 31 #if !defined(_LKM) && defined(_KERNEL_OPT) 32 #include "opt_cputype.h" 33 #endif 34 35 #ifndef __ASSEMBLER__ 36 37 #include <sys/cpu.h> 38 39 #include <mips/mutex.h> 40 #include <mips/cpuregs.h> 41 #include <mips/reg.h> 42 43 #ifndef __BSD_PTENTRY_T__ 44 #define __BSD_PTENTRY_T__ 45 typedef uint32_t pt_entry_t; 46 #define PRIxPTE PRIx32 47 #endif 48 49 #include <uvm/pmap/tlb.h> 50 #endif /* !__ASSEMBLER__ */ 51 52 #ifdef _KERNEL 53 54 #if defined(_MODULAR) || defined(_LKM) || defined(_STANDALONE) 55 /* Assume all CPU architectures are valid for LKM's and standlone progs */ 56 #if !defined(__mips_n32) && !defined(__mips_n64) 57 #define MIPS1 1 58 #endif 59 #define MIPS3 1 60 #define MIPS4 1 61 #if !defined(__mips_n32) && !defined(__mips_n64) 62 #define MIPS32 1 63 #define MIPS32R2 1 64 #endif 65 #define MIPS64 1 66 #define MIPS64R2 1 67 #endif /* _MODULAR || _LKM || _STANDALONE */ 68 69 #if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) == 0 70 #error at least one of MIPS1, MIPS3, MIPS4, MIPS32, MIPS32R2, MIPS64, or MIPS64R2 must be specified 71 #endif 72 73 /* Shortcut for MIPS3 or above defined */ 74 #if defined(MIPS3) || defined(MIPS4) \ 75 || defined(MIPS32) || defined(MIPS32R2) \ 76 || defined(MIPS64) || defined(MIPS64R2) 77 78 #define MIPS3_PLUS 1 79 #if !defined(MIPS32) && !defined(MIPS32R2) 80 #define MIPS3_64BIT 1 81 #endif 82 #if !defined(MIPS3) && !defined(MIPS4) 83 #define MIPSNN 1 84 #endif 85 #if defined(MIPS32R2) || defined(MIPS64R2) 86 #define MIPSNNR2 1 87 #endif 88 #else 89 #undef MIPS3_PLUS 90 #endif 91 92 #if !defined(MIPS3_PLUS) && (ENABLE_MIPS_8KB_PAGE + ENABLE_MIPS_16KB_PAGE) > 0 93 #error MIPS1 does not support non-4KB page sizes. 94 #endif 95 96 /* XXX some .S files look for MIPS3_PLUS */ 97 #ifndef __ASSEMBLER__ 98 99 /* XXX simonb 100 * Should the following be in a cpu_info type structure? 101 * And how many of these are per-cpu vs. per-system? (Ie, 102 * we can assume that all cpus have the same mmu-type, but 103 * maybe not that all cpus run at the same clock speed. 104 * Some SGI's apparently support R12k and R14k in the same 105 * box.) 106 */ 107 struct mips_options { 108 const struct pridtab *mips_cpu; 109 110 u_int mips_cpu_arch; 111 u_int mips_cpu_mhz; /* CPU speed in MHz, estimated by mc_cpuspeed(). */ 112 u_int mips_cpu_flags; 113 u_int mips_num_tlb_entries; 114 mips_prid_t mips_cpu_id; 115 mips_prid_t mips_fpu_id; 116 bool mips_has_r4k_mmu; 117 bool mips_has_llsc; 118 u_int mips3_pg_shift; 119 u_int mips3_pg_cached; 120 u_int mips3_cca_devmem; 121 #ifdef MIPS3_PLUS 122 #ifndef __mips_o32 123 uint64_t mips3_xkphys_cached; 124 #endif 125 uint64_t mips3_tlb_vpn_mask; 126 uint64_t mips3_tlb_pfn_mask; 127 uint32_t mips3_tlb_pg_mask; 128 #endif 129 }; 130 131 #endif /* !__ASSEMBLER__ */ 132 133 /* 134 * Macros to find the CPU architecture we're on at run-time, 135 * or if possible, at compile-time. 136 */ 137 138 #define CPU_ARCH_MIPSx 0 /* XXX unknown */ 139 #define CPU_ARCH_MIPS1 (1 << 0) 140 #define CPU_ARCH_MIPS2 (1 << 1) 141 #define CPU_ARCH_MIPS3 (1 << 2) 142 #define CPU_ARCH_MIPS4 (1 << 3) 143 #define CPU_ARCH_MIPS5 (1 << 4) 144 #define CPU_ARCH_MIPS32 (1 << 5) 145 #define CPU_ARCH_MIPS64 (1 << 6) 146 #define CPU_ARCH_MIPS32R2 (1 << 7) 147 #define CPU_ARCH_MIPS64R2 (1 << 8) 148 149 #define CPU_MIPS_R4K_MMU 0x0001 150 #define CPU_MIPS_NO_LLSC 0x0002 151 #define CPU_MIPS_CAUSE_IV 0x0004 152 #define CPU_MIPS_HAVE_SPECIAL_CCA 0x0008 /* Defaults to '3' if not set. */ 153 #define CPU_MIPS_CACHED_CCA_MASK 0x0070 154 #define CPU_MIPS_CACHED_CCA_SHIFT 4 155 #define CPU_MIPS_DOUBLE_COUNT 0x0080 /* 1 cp0 count == 2 clock cycles */ 156 #define CPU_MIPS_USE_WAIT 0x0100 /* Use "wait"-based cpu_idle() */ 157 #define CPU_MIPS_NO_WAIT 0x0200 /* Inverse of previous, for mips32/64 */ 158 #define CPU_MIPS_D_CACHE_COHERENT 0x0400 /* D-cache is fully coherent */ 159 #define CPU_MIPS_I_D_CACHE_COHERENT 0x0800 /* I-cache funcs don't need to flush the D-cache */ 160 #define CPU_MIPS_NO_LLADDR 0x1000 161 #define CPU_MIPS_HAVE_MxCR 0x2000 /* have mfcr, mtcr insns */ 162 #define CPU_MIPS_LOONGSON2 0x4000 163 #define MIPS_NOT_SUPP 0x8000 164 #define CPU_MIPS_HAVE_DSP 0x10000 165 166 #endif /* !_LOCORE */ 167 168 #if ((MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) == 1) || defined(_LOCORE) 169 170 #if defined(MIPS1) 171 172 # define CPUISMIPS3 0 173 # define CPUIS64BITS 0 174 # define CPUISMIPS32 0 175 # define CPUISMIPS32R2 0 176 # define CPUISMIPS64 0 177 # define CPUISMIPS64R2 0 178 # define CPUISMIPSNN 0 179 # define CPUISMIPSNNR2 0 180 # define MIPS_HAS_R4K_MMU 0 181 # define MIPS_HAS_CLOCK 0 182 # define MIPS_HAS_LLSC 0 183 # define MIPS_HAS_LLADDR 0 184 # define MIPS_HAS_DSP 0 185 # define MIPS_HAS_LMMI 0 186 187 #elif defined(MIPS3) || defined(MIPS4) 188 189 # define CPUISMIPS3 1 190 # define CPUIS64BITS 1 191 # define CPUISMIPS32 0 192 # define CPUISMIPS32R2 0 193 # define CPUISMIPS64 0 194 # define CPUISMIPS64R2 0 195 # define CPUISMIPSNN 0 196 # define CPUISMIPSNNR2 0 197 # define MIPS_HAS_R4K_MMU 1 198 # define MIPS_HAS_CLOCK 1 199 # if defined(_LOCORE) 200 # if !defined(MIPS3_4100) 201 # define MIPS_HAS_LLSC 1 202 # else 203 # define MIPS_HAS_LLSC 0 204 # endif 205 # else /* _LOCORE */ 206 # define MIPS_HAS_LLSC (mips_options.mips_has_llsc) 207 # endif /* _LOCORE */ 208 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 209 # define MIPS_HAS_DSP 0 210 # if defined(MIPS3_LOONGSON2) 211 # define MIPS_HAS_LMMI ((mips_options.mips_cpu_flags & CPU_MIPS_LOONGSON2) != 0) 212 # else 213 # define MIPS_HAS_LMMI 0 214 # endif 215 #elif defined(MIPS32) 216 217 # define CPUISMIPS3 1 218 # define CPUIS64BITS 0 219 # define CPUISMIPS32 1 220 # define CPUISMIPS32R2 0 221 # define CPUISMIPS64 0 222 # define CPUISMIPS64R2 0 223 # define CPUISMIPSNN 1 224 # define CPUISMIPSNNR2 0 225 # define MIPS_HAS_R4K_MMU 1 226 # define MIPS_HAS_CLOCK 1 227 # define MIPS_HAS_LLSC 1 228 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 229 # define MIPS_HAS_DSP 0 230 # define MIPS_HAS_LMMI 0 231 232 #elif defined(MIPS32R2) 233 234 # define CPUISMIPS3 1 235 # define CPUIS64BITS 0 236 # define CPUISMIPS32 0 237 # define CPUISMIPS32R2 1 238 # define CPUISMIPS64 0 239 # define CPUISMIPS64R2 0 240 # define CPUISMIPSNN 1 241 # define CPUISMIPSNNR2 1 242 # define MIPS_HAS_R4K_MMU 1 243 # define MIPS_HAS_CLOCK 1 244 # define MIPS_HAS_LLSC 1 245 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 246 # define MIPS_HAS_DSP (mips_options.mips_cpu_flags & CPU_MIPS_HAVE_DSP) 247 # define MIPS_HAS_LMMI 0 248 249 #elif defined(MIPS64) 250 251 # define CPUISMIPS3 1 252 # define CPUIS64BITS 1 253 # define CPUISMIPS32 0 254 # define CPUISMIPS32R2 0 255 # define CPUISMIPS64 1 256 # define CPUISMIPS64R2 0 257 # define CPUISMIPSNN 1 258 # define CPUISMIPSNNR2 0 259 # define MIPS_HAS_R4K_MMU 1 260 # define MIPS_HAS_CLOCK 1 261 # define MIPS_HAS_LLSC 1 262 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 263 # define MIPS_HAS_DSP 0 264 # define MIPS_HAS_LMMI 0 265 266 #elif defined(MIPS64R2) 267 268 # define CPUISMIPS3 1 269 # define CPUIS64BITS 1 270 # define CPUISMIPS32 0 271 # define CPUISMIPS32R2 0 272 # define CPUISMIPS64 0 273 # define CPUISMIPS64R2 1 274 # define CPUISMIPSNN 1 275 # define CPUISMIPSNNR2 1 276 # define MIPS_HAS_R4K_MMU 1 277 # define MIPS_HAS_CLOCK 1 278 # define MIPS_HAS_LLSC 1 279 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 280 # define MIPS_HAS_DSP (mips_options.mips_cpu_flags & CPU_MIPS_HAVE_DSP) 281 # define MIPS_HAS_LMMI 0 282 283 #endif 284 285 #else /* run-time test */ 286 287 #ifdef MIPS1 288 #define MIPS_HAS_R4K_MMU (mips_options.mips_has_r4k_mmu) 289 #define MIPS_HAS_LLSC (mips_options.mips_has_llsc) 290 #else 291 #define MIPS_HAS_R4K_MMU 1 292 #if !defined(MIPS3_4100) 293 #define MIPS_HAS_LLSC 1 294 #else 295 #define MIPS_HAS_LLSC (mips_options.mips_has_llsc) 296 #endif 297 #endif 298 #define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 299 #define MIPS_HAS_DSP (mips_options.mips_cpu_flags & CPU_MIPS_HAVE_DSP) 300 301 /* This test is ... rather bogus */ 302 #define CPUISMIPS3 ((mips_options.mips_cpu_arch & \ 303 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 304 305 /* And these aren't much better while the previous test exists as is... */ 306 #define CPUISMIPS4 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS4) != 0) 307 #define CPUISMIPS5 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS5) != 0) 308 #define CPUISMIPS32 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS32) != 0) 309 #define CPUISMIPS32R2 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS32R2) != 0) 310 #define CPUISMIPS64 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS64) != 0) 311 #define CPUISMIPS64R2 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS64R2) != 0) 312 #define CPUISMIPSNN ((mips_options.mips_cpu_arch & (CPU_ARCH_MIPS32 | CPU_ARCH_MIPS32R2 | CPU_ARCH_MIPS64 | CPU_ARCH_MIPS64R2)) != 0) 313 #define CPUIS64BITS ((mips_options.mips_cpu_arch & \ 314 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS64 | CPU_ARCH_MIPS64R2)) != 0) 315 316 #define MIPS_HAS_CLOCK (mips_options.mips_cpu_arch >= CPU_ARCH_MIPS3) 317 318 #endif /* run-time test */ 319 320 #ifndef __ASSEMBLER__ 321 322 struct tlbmask; 323 struct trapframe; 324 325 void trap(uint32_t, uint32_t, vaddr_t, vaddr_t, struct trapframe *); 326 void ast(void); 327 328 void mips_fpu_trap(vaddr_t, struct trapframe *); 329 void mips_fpu_intr(vaddr_t, struct trapframe *); 330 331 vaddr_t mips_emul_branch(struct trapframe *, vaddr_t, uint32_t, bool); 332 void mips_emul_inst(uint32_t, uint32_t, vaddr_t, struct trapframe *); 333 334 void mips_emul_fp(uint32_t, struct trapframe *, uint32_t); 335 void mips_emul_branchdelayslot(uint32_t, struct trapframe *, uint32_t); 336 337 void mips_emul_lwc0(uint32_t, struct trapframe *, uint32_t); 338 void mips_emul_swc0(uint32_t, struct trapframe *, uint32_t); 339 void mips_emul_special(uint32_t, struct trapframe *, uint32_t); 340 void mips_emul_special3(uint32_t, struct trapframe *, uint32_t); 341 342 void mips_emul_lwc1(uint32_t, struct trapframe *, uint32_t); 343 void mips_emul_swc1(uint32_t, struct trapframe *, uint32_t); 344 void mips_emul_ldc1(uint32_t, struct trapframe *, uint32_t); 345 void mips_emul_sdc1(uint32_t, struct trapframe *, uint32_t); 346 347 void mips_emul_lb(uint32_t, struct trapframe *, uint32_t); 348 void mips_emul_lbu(uint32_t, struct trapframe *, uint32_t); 349 void mips_emul_lh(uint32_t, struct trapframe *, uint32_t); 350 void mips_emul_lhu(uint32_t, struct trapframe *, uint32_t); 351 void mips_emul_lw(uint32_t, struct trapframe *, uint32_t); 352 void mips_emul_lwl(uint32_t, struct trapframe *, uint32_t); 353 void mips_emul_lwr(uint32_t, struct trapframe *, uint32_t); 354 #if defined(__mips_n32) || defined(__mips_n64) || defined(__mips_o64) 355 void mips_emul_lwu(uint32_t, struct trapframe *, uint32_t); 356 void mips_emul_ld(uint32_t, struct trapframe *, uint32_t); 357 void mips_emul_ldl(uint32_t, struct trapframe *, uint32_t); 358 void mips_emul_ldr(uint32_t, struct trapframe *, uint32_t); 359 #endif 360 void mips_emul_sb(uint32_t, struct trapframe *, uint32_t); 361 void mips_emul_sh(uint32_t, struct trapframe *, uint32_t); 362 void mips_emul_sw(uint32_t, struct trapframe *, uint32_t); 363 void mips_emul_swl(uint32_t, struct trapframe *, uint32_t); 364 void mips_emul_swr(uint32_t, struct trapframe *, uint32_t); 365 #if defined(__mips_n32) || defined(__mips_n64) || defined(__mips_o64) 366 void mips_emul_sd(uint32_t, struct trapframe *, uint32_t); 367 void mips_emul_sdl(uint32_t, struct trapframe *, uint32_t); 368 void mips_emul_sdr(uint32_t, struct trapframe *, uint32_t); 369 #endif 370 371 uint32_t mips_cp0_cause_read(void); 372 void mips_cp0_cause_write(uint32_t); 373 uint32_t mips_cp0_status_read(void); 374 void mips_cp0_status_write(uint32_t); 375 376 void softint_process(uint32_t); 377 void softint_fast_dispatch(struct lwp *, int); 378 379 /* 380 * Convert an address to an offset used in a MIPS jump instruction. The offset 381 * contains the low 28 bits (allowing a jump to anywhere within the same 256MB 382 * segment of address space) of the address but since mips instructions are 383 * always on a 4 byte boundary the low 2 bits are always zero so the 28 bits 384 * get shifted right by 2 bits leaving us with a 26 bit result. To make the 385 * offset, we shift left to clear the upper four bits and then right by 6. 386 */ 387 #define fixup_addr2offset(x) ((((uint32_t)(uintptr_t)(x)) << 4) >> 6) 388 typedef bool (*mips_fixup_callback_t)(int32_t, uint32_t [2], void *); 389 struct mips_jump_fixup_info { 390 uint32_t jfi_stub; 391 uint32_t jfi_real; 392 }; 393 394 void fixup_splcalls(void); /* splstubs.c */ 395 bool mips_fixup_exceptions(mips_fixup_callback_t, void *); 396 bool mips_fixup_zero_relative(int32_t, uint32_t [2], void *); 397 intptr_t 398 mips_fixup_addr(const uint32_t *); 399 void mips_fixup_stubs(uint32_t *, uint32_t *); 400 401 /* 402 * Define these stubs... 403 */ 404 void mips_cpu_switch_resume(struct lwp *); 405 void wbflush(void); 406 407 #ifdef MIPS1 408 void mips1_tlb_invalidate_all(void); 409 410 uint32_t tx3900_cp0_config_read(void); 411 #endif 412 413 #ifdef MIPS3_PLUS 414 uint32_t mips3_cp0_compare_read(void); 415 void mips3_cp0_compare_write(uint32_t); 416 417 uint32_t mips3_cp0_config_read(void); 418 void mips3_cp0_config_write(uint32_t); 419 420 #ifdef MIPSNN 421 uint32_t mipsNN_cp0_config1_read(void); 422 void mipsNN_cp0_config1_write(uint32_t); 423 uint32_t mipsNN_cp0_config2_read(void); 424 uint32_t mipsNN_cp0_config3_read(void); 425 uint32_t mipsNN_cp0_config4_read(void); 426 uint32_t mipsNN_cp0_config5_read(void); 427 uint32_t mipsNN_cp0_config6_read(void); 428 uint32_t mipsNN_cp0_config7_read(void); 429 430 intptr_t mipsNN_cp0_watchlo_read(u_int); 431 void mipsNN_cp0_watchlo_write(u_int, intptr_t); 432 uint32_t mipsNN_cp0_watchhi_read(u_int); 433 void mipsNN_cp0_watchhi_write(u_int, uint32_t); 434 435 int32_t mipsNN_cp0_ebase_read(void); 436 void mipsNN_cp0_ebase_write(int32_t); 437 438 uint32_t mipsNN_cp0_rdhwr_cpunum(void); 439 440 #ifdef MIPSNNR2 441 void mipsNN_cp0_hwrena_write(uint32_t); 442 void mipsNN_cp0_userlocal_write(void *); 443 #endif 444 #endif /* MIPSNN */ 445 446 uint32_t mips3_cp0_count_read(void); 447 void mips3_cp0_count_write(uint32_t); 448 449 uint32_t mips3_cp0_wired_read(void); 450 void mips3_cp0_wired_write(uint32_t); 451 void mips3_cp0_pg_mask_write(uint32_t); 452 453 #endif /* MIPS3_PLUS */ 454 455 /* 64-bit address space accessor for n32, n64 ABI */ 456 /* 32-bit address space accessor for o32 ABI */ 457 static inline uint8_t mips_lbu(register_t addr) __unused; 458 static inline void mips_sb(register_t addr, uint8_t val) __unused; 459 static inline uint16_t mips_lhu(register_t addr) __unused; 460 static inline void mips_sh(register_t addr, uint16_t val) __unused; 461 static inline uint32_t mips_lwu(register_t addr) __unused; 462 static inline void mips_sw(register_t addr, uint32_t val) __unused; 463 #ifdef MIPS3_64BIT 464 #if defined(__mips_o32) 465 uint64_t mips3_ld(register_t addr); 466 void mips3_sd(register_t addr, uint64_t val); 467 #else 468 static inline uint64_t mips3_ld(register_t addr) __unused; 469 static inline void mips3_sd(register_t addr, uint64_t val) __unused; 470 #endif 471 #endif 472 473 static inline uint8_t 474 mips_lbu(register_t addr) 475 { 476 uint8_t rv; 477 #if defined(__mips_n32) 478 __asm volatile("lbu\t%0, 0(%1)" : "=r"(rv) : "d"(addr)); 479 #else 480 rv = *(const volatile uint8_t *)addr; 481 #endif 482 return rv; 483 } 484 485 static inline uint16_t 486 mips_lhu(register_t addr) 487 { 488 uint16_t rv; 489 #if defined(__mips_n32) 490 __asm volatile("lhu\t%0, 0(%1)" : "=r"(rv) : "d"(addr)); 491 #else 492 rv = *(const volatile uint16_t *)addr; 493 #endif 494 return rv; 495 } 496 497 static inline uint32_t 498 mips_lwu(register_t addr) 499 { 500 uint32_t rv; 501 #if defined(__mips_n32) 502 __asm volatile("lwu\t%0, 0(%1)" : "=r"(rv) : "d"(addr)); 503 #else 504 rv = *(const volatile uint32_t *)addr; 505 #endif 506 return (rv); 507 } 508 509 #if defined(MIPS3_64BIT) && !defined(__mips_o32) 510 static inline uint64_t 511 mips3_ld(register_t addr) 512 { 513 uint64_t rv; 514 #if defined(__mips_n32) 515 __asm volatile("ld\t%0, 0(%1)" : "=r"(rv) : "d"(addr)); 516 #elif defined(_LP64) 517 rv = *(const volatile uint64_t *)addr; 518 #else 519 #error unknown ABI 520 #endif 521 return (rv); 522 } 523 #endif /* MIPS3_64BIT && !__mips_o32 */ 524 525 static inline void 526 mips_sb(register_t addr, uint8_t val) 527 { 528 #if defined(__mips_n32) 529 __asm volatile("sb\t%1, 0(%0)" :: "d"(addr), "r"(val)); 530 #else 531 *(volatile uint8_t *)addr = val; 532 #endif 533 } 534 535 static inline void 536 mips_sh(register_t addr, uint16_t val) 537 { 538 #if defined(__mips_n32) 539 __asm volatile("sh\t%1, 0(%0)" :: "d"(addr), "r"(val)); 540 #else 541 *(volatile uint16_t *)addr = val; 542 #endif 543 } 544 545 static inline void 546 mips_sw(register_t addr, uint32_t val) 547 { 548 #if defined(__mips_n32) 549 __asm volatile("sw\t%1, 0(%0)" :: "d"(addr), "r"(val)); 550 #else 551 *(volatile uint32_t *)addr = val; 552 #endif 553 } 554 555 #if defined(MIPS3_64BIT) && !defined(__mips_o32) 556 static inline void 557 mips3_sd(register_t addr, uint64_t val) 558 { 559 #if defined(__mips_n32) 560 __asm volatile("sd\t%1, 0(%0)" :: "d"(addr), "r"(val)); 561 #else 562 *(volatile uint64_t *)addr = val; 563 #endif 564 } 565 #endif /* MIPS3_64BIT && !__mips_o32 */ 566 567 /* 568 * A vector with an entry for each mips-ISA-level dependent 569 * locore function, and macros which jump through it. 570 */ 571 typedef struct { 572 void (*ljv_cpu_switch_resume)(struct lwp *); 573 intptr_t ljv_lwp_trampoline; 574 void (*ljv_wbflush)(void); 575 tlb_asid_t (*ljv_tlb_get_asid)(void); 576 void (*ljv_tlb_set_asid)(tlb_asid_t pid); 577 void (*ljv_tlb_invalidate_asids)(tlb_asid_t, tlb_asid_t); 578 void (*ljv_tlb_invalidate_addr)(vaddr_t, tlb_asid_t); 579 void (*ljv_tlb_invalidate_globals)(void); 580 void (*ljv_tlb_invalidate_all)(void); 581 u_int (*ljv_tlb_record_asids)(u_long *, tlb_asid_t); 582 int (*ljv_tlb_update_addr)(vaddr_t, tlb_asid_t, pt_entry_t, bool); 583 void (*ljv_tlb_read_entry)(size_t, struct tlbmask *); 584 void (*ljv_tlb_write_entry)(size_t, const struct tlbmask *); 585 } mips_locore_jumpvec_t; 586 587 typedef struct { 588 u_int (*lav_atomic_cas_uint)(volatile u_int *, u_int, u_int); 589 u_long (*lav_atomic_cas_ulong)(volatile u_long *, u_long, u_long); 590 int (*lav_ucas_32)(volatile uint32_t *, uint32_t, uint32_t, 591 uint32_t *); 592 int (*lav_ucas_64)(volatile uint64_t *, uint64_t, uint64_t, 593 uint64_t *); 594 void (*lav_mutex_enter)(kmutex_t *); 595 void (*lav_mutex_exit)(kmutex_t *); 596 void (*lav_mutex_spin_enter)(kmutex_t *); 597 void (*lav_mutex_spin_exit)(kmutex_t *); 598 } mips_locore_atomicvec_t; 599 600 void mips_set_wbflush(void (*)(void)); 601 void mips_wait_idle(void); 602 603 void stacktrace(void); 604 void logstacktrace(void); 605 606 struct cpu_info; 607 struct splsw; 608 609 struct locoresw { 610 void (*lsw_wbflush)(void); 611 void (*lsw_cpu_idle)(void); 612 int (*lsw_send_ipi)(struct cpu_info *, int); 613 void (*lsw_cpu_offline_md)(void); 614 void (*lsw_cpu_init)(struct cpu_info *); 615 void (*lsw_cpu_run)(struct cpu_info *); 616 int (*lsw_bus_error)(unsigned int); 617 }; 618 619 struct mips_vmfreelist { 620 paddr_t fl_start; 621 paddr_t fl_end; 622 int fl_freelist; 623 }; 624 625 struct cpu_info * 626 cpu_info_alloc(struct pmap_tlb_info *, cpuid_t, cpuid_t, cpuid_t, 627 cpuid_t); 628 void cpu_attach_common(device_t, struct cpu_info *); 629 void cpu_startup_common(void); 630 631 #ifdef MULTIPROCESSOR 632 void cpu_hatch(struct cpu_info *ci); 633 void cpu_trampoline(void); 634 void cpu_halt(void); 635 void cpu_halt_others(void); 636 void cpu_pause(struct reg *); 637 void cpu_pause_others(void); 638 void cpu_resume(cpuid_t); 639 void cpu_resume_others(void); 640 bool cpu_is_paused(cpuid_t); 641 void cpu_debug_dump(void); 642 643 extern kcpuset_t *cpus_running; 644 extern kcpuset_t *cpus_hatched; 645 extern kcpuset_t *cpus_paused; 646 extern kcpuset_t *cpus_resumed; 647 extern kcpuset_t *cpus_halted; 648 #endif 649 650 /* copy.S */ 651 uint32_t mips_ufetch32(const void *); 652 int mips_ustore32_isync(void *, uint32_t); 653 654 int32_t kfetch_32(volatile uint32_t *, uint32_t); 655 656 /* trap.c */ 657 void netintr(void); 658 bool kdbpeek(vaddr_t, int *); 659 660 /* mips_dsp.c */ 661 void dsp_init(void); 662 void dsp_discard(lwp_t *); 663 void dsp_load(void); 664 void dsp_save(lwp_t *); 665 bool dsp_used_p(const lwp_t *); 666 extern const pcu_ops_t mips_dsp_ops; 667 668 /* mips_fpu.c */ 669 void fpu_init(void); 670 void fpu_discard(lwp_t *); 671 void fpu_load(void); 672 void fpu_save(lwp_t *); 673 bool fpu_used_p(const lwp_t *); 674 extern const pcu_ops_t mips_fpu_ops; 675 676 /* mips_machdep.c */ 677 void dumpsys(void); 678 int savectx(struct pcb *); 679 void cpu_identify(device_t); 680 681 /* locore*.S */ 682 int badaddr(void *, size_t); 683 int badaddr64(uint64_t, size_t); 684 685 /* vm_machdep.c */ 686 int ioaccess(vaddr_t, paddr_t, vsize_t); 687 int iounaccess(vaddr_t, vsize_t); 688 689 /* 690 * The "active" locore-function vector, and 691 */ 692 extern const mips_locore_atomicvec_t mips_llsc_locore_atomicvec; 693 694 extern mips_locore_atomicvec_t mips_locore_atomicvec; 695 extern mips_locore_jumpvec_t mips_locore_jumpvec; 696 extern struct locoresw mips_locoresw; 697 698 extern int mips_poolpage_vmfreelist; /* freelist to allocate poolpages */ 699 extern struct mips_options mips_options; 700 701 struct splsw; 702 struct mips_vmfreelist; 703 struct phys_ram_seg; 704 705 void mips64r2_vector_init(const struct splsw *); 706 void mips_vector_init(const struct splsw *, bool); 707 void mips_init_msgbuf(void); 708 void mips_init_lwp0_uarea(void); 709 void mips_page_physload(vaddr_t, vaddr_t, 710 const struct phys_ram_seg *, size_t, 711 const struct mips_vmfreelist *, size_t); 712 713 714 /* 715 * CPU identification, from PRID register. 716 */ 717 #define MIPS_PRID_REV(x) (((x) >> 0) & 0x00ff) 718 #define MIPS_PRID_IMPL(x) (((x) >> 8) & 0x00ff) 719 720 /* pre-MIPS32/64 */ 721 #define MIPS_PRID_RSVD(x) (((x) >> 16) & 0xffff) 722 #define MIPS_PRID_REV_MIN(x) ((MIPS_PRID_REV(x) >> 0) & 0x0f) 723 #define MIPS_PRID_REV_MAJ(x) ((MIPS_PRID_REV(x) >> 4) & 0x0f) 724 725 /* MIPS32/64 */ 726 #define MIPS_PRID_CID(x) (((x) >> 16) & 0x00ff) /* Company ID */ 727 #define MIPS_PRID_CID_PREHISTORIC 0x00 /* Not MIPS32/64 */ 728 #define MIPS_PRID_CID_MTI 0x01 /* MIPS Technologies, Inc. */ 729 #define MIPS_PRID_CID_BROADCOM 0x02 /* Broadcom */ 730 #define MIPS_PRID_CID_ALCHEMY 0x03 /* Alchemy Semiconductor */ 731 #define MIPS_PRID_CID_SIBYTE 0x04 /* SiByte */ 732 #define MIPS_PRID_CID_SANDCRAFT 0x05 /* SandCraft */ 733 #define MIPS_PRID_CID_PHILIPS 0x06 /* Philips */ 734 #define MIPS_PRID_CID_TOSHIBA 0x07 /* Toshiba */ 735 #define MIPS_PRID_CID_MICROSOFT 0x07 /* Microsoft also, sigh */ 736 #define MIPS_PRID_CID_LSI 0x08 /* LSI */ 737 /* 0x09 unannounced */ 738 /* 0x0a unannounced */ 739 #define MIPS_PRID_CID_LEXRA 0x0b /* Lexra */ 740 #define MIPS_PRID_CID_RMI 0x0c /* RMI / NetLogic */ 741 #define MIPS_PRID_CID_CAVIUM 0x0d /* Cavium */ 742 #define MIPS_PRID_CID_INGENIC 0xe1 743 #define MIPS_PRID_COPTS(x) (((x) >> 24) & 0x00ff) /* Company Options */ 744 745 #ifdef _KERNEL 746 /* 747 * Global variables used to communicate CPU type, and parameters 748 * such as cache size, from locore to higher-level code (e.g., pmap). 749 */ 750 void mips_pagecopy(register_t dst, register_t src); 751 void mips_pagezero(register_t dst); 752 753 #ifdef __HAVE_MIPS_MACHDEP_CACHE_CONFIG 754 void mips_machdep_cache_config(void); 755 #endif 756 757 /* 758 * trapframe argument passed to trap() 759 */ 760 761 #if 0 762 #define TF_AST 0 /* really zero */ 763 #define TF_V0 _R_V0 764 #define TF_V1 _R_V1 765 #define TF_A0 _R_A0 766 #define TF_A1 _R_A1 767 #define TF_A2 _R_A2 768 #define TF_A3 _R_A3 769 #define TF_T0 _R_T0 770 #define TF_T1 _R_T1 771 #define TF_T2 _R_T2 772 #define TF_T3 _R_T3 773 774 #if defined(__mips_n32) || defined(__mips_n64) 775 #define TF_A4 _R_A4 776 #define TF_A5 _R_A5 777 #define TF_A6 _R_A6 778 #define TF_A7 _R_A7 779 #else 780 #define TF_T4 _R_T4 781 #define TF_T5 _R_T5 782 #define TF_T6 _R_T6 783 #define TF_T7 _R_T7 784 #endif /* __mips_n32 || __mips_n64 */ 785 786 #define TF_TA0 _R_TA0 787 #define TF_TA1 _R_TA1 788 #define TF_TA2 _R_TA2 789 #define TF_TA3 _R_TA3 790 791 #define TF_T8 _R_T8 792 #define TF_T9 _R_T9 793 794 #define TF_RA _R_RA 795 #define TF_SR _R_SR 796 #define TF_MULLO _R_MULLO 797 #define TF_MULHI _R_MULLO 798 #define TF_EPC _R_PC /* may be changed by trap() call */ 799 800 #define TF_NREGS (sizeof(struct reg) / sizeof(mips_reg_t)) 801 #endif 802 803 struct trapframe { 804 struct reg tf_registers; 805 #define tf_regs tf_registers.r_regs 806 uint32_t tf_ppl; /* previous priority level */ 807 mips_reg_t tf_pad; /* for 8 byte aligned */ 808 }; 809 810 CTASSERT(sizeof(struct trapframe) % (4*sizeof(mips_reg_t)) == 0); 811 812 /* 813 * Stack frame for kernel traps. four args passed in registers. 814 * A trapframe is pointed to by the 5th arg, and a dummy sixth argument 815 * is used to avoid alignment problems 816 */ 817 818 struct kernframe { 819 #if defined(__mips_o32) || defined(__mips_o64) 820 register_t cf_args[4 + 1]; 821 #if defined(__mips_o32) 822 register_t cf_pad; /* (for 8 byte alignment) */ 823 #endif 824 #endif 825 #if defined(__mips_n32) || defined(__mips_n64) 826 register_t cf_pad[2]; /* for 16 byte alignment */ 827 #endif 828 register_t cf_sp; 829 register_t cf_ra; 830 struct trapframe cf_frame; 831 }; 832 833 CTASSERT(sizeof(struct kernframe) % (2*sizeof(mips_reg_t)) == 0); 834 835 /* 836 * PRocessor IDentity TABle 837 */ 838 839 struct pridtab { 840 int cpu_cid; 841 int cpu_pid; 842 int cpu_rev; /* -1 == wildcard */ 843 int cpu_copts; /* -1 == wildcard */ 844 int cpu_isa; /* -1 == probed (mips32/mips64) */ 845 int cpu_ntlb; /* -1 == unknown, 0 == probed */ 846 int cpu_flags; 847 u_int cpu_cp0flags; /* presence of some cp0 regs */ 848 u_int cpu_cidflags; /* company-specific flags */ 849 const char *cpu_name; 850 }; 851 852 /* 853 * bitfield defines for cpu_cp0flags 854 */ 855 #define MIPS_CP0FL_USE __BIT(0) /* use these flags */ 856 #define MIPS_CP0FL_ECC __BIT(1) 857 #define MIPS_CP0FL_CACHE_ERR __BIT(2) 858 #define MIPS_CP0FL_EIRR __BIT(3) 859 #define MIPS_CP0FL_EIMR __BIT(4) 860 #define MIPS_CP0FL_EBASE __BIT(5) 861 #define MIPS_CP0FL_CONFIG __BIT(6) 862 #define MIPS_CP0FL_CONFIG1 __BIT(7) 863 #define MIPS_CP0FL_CONFIG2 __BIT(8) 864 #define MIPS_CP0FL_CONFIG3 __BIT(9) 865 #define MIPS_CP0FL_CONFIG4 __BIT(10) 866 #define MIPS_CP0FL_CONFIG5 __BIT(11) 867 #define MIPS_CP0FL_CONFIG6 __BIT(12) 868 #define MIPS_CP0FL_CONFIG7 __BIT(13) 869 #define MIPS_CP0FL_USERLOCAL __BIT(14) 870 #define MIPS_CP0FL_HWRENA __BIT(15) 871 872 /* 873 * cpu_cidflags defines, by company 874 */ 875 /* 876 * RMI company-specific cpu_cidflags 877 */ 878 #define MIPS_CIDFL_RMI_TYPE __BITS(2,0) 879 # define CIDFL_RMI_TYPE_XLR 0 880 # define CIDFL_RMI_TYPE_XLS 1 881 # define CIDFL_RMI_TYPE_XLP 2 882 #define MIPS_CIDFL_RMI_THREADS_MASK __BITS(6,3) 883 # define MIPS_CIDFL_RMI_THREADS_SHIFT 3 884 #define MIPS_CIDFL_RMI_CORES_MASK __BITS(10,7) 885 # define MIPS_CIDFL_RMI_CORES_SHIFT 7 886 # define LOG2_1 0 887 # define LOG2_2 1 888 # define LOG2_4 2 889 # define LOG2_8 3 890 # define MIPS_CIDFL_RMI_CPUS(ncores, nthreads) \ 891 ((LOG2_ ## ncores << MIPS_CIDFL_RMI_CORES_SHIFT) \ 892 |(LOG2_ ## nthreads << MIPS_CIDFL_RMI_THREADS_SHIFT)) 893 # define MIPS_CIDFL_RMI_NTHREADS(cidfl) \ 894 (1 << (((cidfl) & MIPS_CIDFL_RMI_THREADS_MASK) \ 895 >> MIPS_CIDFL_RMI_THREADS_SHIFT)) 896 # define MIPS_CIDFL_RMI_NCORES(cidfl) \ 897 (1 << (((cidfl) & MIPS_CIDFL_RMI_CORES_MASK) \ 898 >> MIPS_CIDFL_RMI_CORES_SHIFT)) 899 #define MIPS_CIDFL_RMI_L2SZ_MASK __BITS(14,11) 900 # define MIPS_CIDFL_RMI_L2SZ_SHIFT 11 901 # define RMI_L2SZ_256KB 0 902 # define RMI_L2SZ_512KB 1 903 # define RMI_L2SZ_1MB 2 904 # define RMI_L2SZ_2MB 3 905 # define RMI_L2SZ_4MB 4 906 # define MIPS_CIDFL_RMI_L2(l2sz) \ 907 (RMI_L2SZ_ ## l2sz << MIPS_CIDFL_RMI_L2SZ_SHIFT) 908 # define MIPS_CIDFL_RMI_L2SZ(cidfl) \ 909 ((256*1024) << (((cidfl) & MIPS_CIDFL_RMI_L2SZ_MASK) \ 910 >> MIPS_CIDFL_RMI_L2SZ_SHIFT)) 911 #endif /* !__ASSEMBLER__ */ 912 #endif /* _KERNEL */ 913 914 #endif /* _MIPS_LOCORE_H */ 915
Indexes created Tue Sep 30 06:09:59 GMT 2025