locore.h revision 1.12
1 /* $NetBSD: locore.h,v 1.12 1997/06/22 04:30:01 jonathan Exp $ */ 2 3 /* 4 * Copyright 1996 The Board of Trustees of The Leland Stanford 5 * Junior University. All Rights Reserved. 6 * 7 * Permission to use, copy, modify, and distribute this 8 * software and its documentation for any purpose and without 9 * fee is hereby granted, provided that the above copyright 10 * notice appear in all copies. Stanford University 11 * makes no representations about the suitability of this 12 * software for any purpose. It is provided "as is" without 13 * express or implied warranty. 14 */ 15 16 /* 17 * Jump table for MIPS cpu locore functions that are implemented 18 * differently on different generations, or instruction-level 19 * archtecture (ISA) level, the Mips family. 20 * The following functions must be provided for each mips ISA level: 21 * 22 * 23 * MachConfigCache 24 * MachFlushCache 25 * MachFlushDCache 26 * MachFlushICache 27 * MachForceCacheUpdate 28 * MachSetPID 29 * MachTLBFlush 30 * MachTLBFlushAddr __P() 31 * MachTLBUpdate (u_int, (pt_entry_t?) u_int); 32 * wbflush 33 * proc_trampoline() 34 * switch_exit() 35 * cpu_switch_resume() 36 * 37 * We currently provide support for: 38 * 39 * r2000 and r3000 (mips ISA-I) 40 * r4000 and r4400 in 32-bit mode (mips ISA-III?) 41 */ 42 43 #ifndef _MIPS_LOCORE_H 44 #define _MIPS_LOCORE_H 45 46 /* 47 * locore service routine for exeception vectors. Used outside locore 48 * only to print them by name in stack tracebacks 49 */ 50 51 extern void mips1_ConfigCache __P((void)); 52 extern void mips1_FlushCache __P((void)); 53 extern void mips1_FlushDCache __P((vm_offset_t addr, vm_offset_t len)); 54 extern void mips1_FlushICache __P((vm_offset_t addr, vm_offset_t len)); 55 extern void mips1_ForceCacheUpdate __P((void)); 56 extern void mips1_SetPID __P((int pid)); 57 extern void mips1_TLBFlush __P((void)); 58 extern void mips1_TLBFlushAddr __P( /* XXX Really pte highpart ? */ 59 (vm_offset_t addr)); 60 extern int mips1_TLBUpdate __P((u_int, /*pt_entry_t*/ u_int)); 61 extern void mips1_TLBWriteIndexed __P((u_int index, u_int high, 62 u_int low)); 63 extern void mips1_wbflush __P((void)); 64 extern void mips1_proc_trampoline __P((void)); 65 extern void mips1_switch_exit __P((struct proc *)); 66 extern void mips1_cpu_switch_resume __P((void)); 67 68 extern void mips3_ConfigCache __P((void)); 69 extern void mips3_FlushCache __P((void)); 70 extern void mips3_FlushDCache __P((vm_offset_t addr, vm_offset_t len)); 71 extern void mips3_FlushICache __P((vm_offset_t addr, vm_offset_t len)); 72 extern void mips3_ForceCacheUpdate __P((void)); 73 extern void mips3_HitFlushDCache __P((vm_offset_t, int)); 74 extern void mips3_SetPID __P((int pid)); 75 extern void mips3_TLBFlush __P((void)); 76 extern void mips3_TLBFlushAddr __P( /* XXX Really pte highpart ? */ 77 (vm_offset_t addr)); 78 extern int mips3_TLBUpdate __P((u_int, /*pt_entry_t*/ u_int)); 79 extern void mips3_TLBWriteIndexedVPS __P((u_int index, void *tlb)); 80 extern void mips3_TLBWriteIndexed __P((u_int index, u_int high, 81 u_int lo0, u_int lo1)); 82 extern void mips3_wbflush __P((void)); 83 extern void mips3_proc_trampoline __P((void)); 84 extern void mips3_switch_exit __P((struct proc *)); 85 extern void mips3_cpu_switch_resume __P((void)); 86 87 extern void mips3_SetWIRED __P((int)); 88 89 90 /* 91 * A vector with an entry for each mips-ISA-level dependent 92 * locore function, and macros which jump through it. 93 * XXX the macro names are chosen to be compatible with the old 94 * Sprite coding-convention names used in 4.4bsd/pmax. 95 */ 96 typedef struct { 97 void (*configCache) __P((void)); 98 void (*flushCache) __P((void)); 99 void (*flushDCache) __P((vm_offset_t addr, vm_offset_t len)); 100 void (*flushICache) __P((vm_offset_t addr, vm_offset_t len)); 101 void (*forceCacheUpdate) __P((void)); 102 void (*setTLBpid) __P((int pid)); 103 void (*tlbFlush) __P((void)); 104 void (*tlbFlushAddr) __P((vm_offset_t)); /* XXX Really pte highpart ? */ 105 int (*tlbUpdate) __P((u_int highreg, u_int lowreg)); 106 void (*wbflush) __P((void)); 107 void (*proc_trampoline) __P((void)); 108 void (*mips_switch_exit) __P((struct proc *)); 109 void (*cpu_switch_resume) __P((void)); 110 } mips_locore_jumpvec_t; 111 112 113 /* 114 * The "active" locore-fuction vector, and 115 116 */ 117 extern mips_locore_jumpvec_t mips_locore_jumpvec; 118 extern mips_locore_jumpvec_t r2000_locore_vec; 119 extern mips_locore_jumpvec_t r4000_locore_vec; 120 121 #if defined(MIPS3) && !defined (MIPS1) 122 #define MachConfigCache mips3_ConfigCache 123 #define MachFlushCache mips3_FlushCache 124 #define MachFlushDCache mips3_FlushDCache 125 #define MachFlushICache mips3_FlushICache 126 #define MachForceCacheUpdate mips3_ForceCacheUpdate 127 #define MachSetPID mips3_SetPID 128 #define MachTLBFlush mips3_TLBFlush 129 #define MachTLBFlushAddr mips3_TLBFlushAddr 130 #define MachTLBUpdate mips3_TLBUpdate 131 #define wbflush mips3_wbflush 132 #define proc_trampoline mips3_proc_trampoline 133 #define switch_exit mips3_switch_exit 134 #endif 135 136 #if !defined(MIPS3) && defined (MIPS1) 137 #define MachConfigCache mips1_ConfigCache 138 #define MachFlushCache mips1_FlushCache 139 #define MachFlushDCache mips1_FlushDCache 140 #define MachFlushICache mips1_FlushICache 141 #define MachForceCacheUpdate mips1_ForceCacheUpdate 142 #define MachSetPID mips1_SetPID 143 #define MachTLBFlush mips1_TLBFlush 144 #define MachTLBFlushAddr mips1_TLBFlushAddr 145 #define MachTLBUpdate mips1_TLBUpdate 146 #define wbflush mips1_wbflush 147 #define proc_trampoline mips1_proc_trampoline 148 #define switch_exit mips1_switch_exit 149 #endif 150 151 152 153 #if defined(MIPS3) && defined (MIPS1) 154 #define MachConfigCache (*(mips_locore_jumpvec.configCache)) 155 #define MachFlushCache (*(mips_locore_jumpvec.flushCache)) 156 #define MachFlushDCache (*(mips_locore_jumpvec.flushDCache)) 157 #define MachFlushICache (*(mips_locore_jumpvec.flushICache)) 158 #define MachForceCacheUpdate (*(mips_locore_jumpvec.forceCacheUpdate)) 159 #define MachSetPID (*(mips_locore_jumpvec.setTLBpid)) 160 #define MachTLBFlush (*(mips_locore_jumpvec.tlbFlush)) 161 #define MachTLBFlushAddr (*(mips_locore_jumpvec.tlbFlushAddr)) 162 #define MachTLBUpdate (*(mips_locore_jumpvec.tlbUpdate)) 163 #define wbflush (*(mips_locore_jumpvec.wbflush)) 164 #define proc_trampoline (mips_locore_jumpvec.proc_trampoline) 165 #define switch_exit (*(mips_locore_jumpvec.mips_switch_exit)) 166 #endif 167 168 /* cpu_switch_resume not called directly */ 169 170 171 /* 172 * CPU identification, from PRID register. 173 */ 174 union cpuprid { 175 int cpuprid; 176 struct { 177 #if BYTE_ORDER == BIG_ENDIAN 178 u_int pad1:16; /* reserved */ 179 u_int cp_imp:8; /* implementation identifier */ 180 u_int cp_majrev:4; /* major revision identifier */ 181 u_int cp_minrev:4; /* minor revision identifier */ 182 #else 183 u_int cp_minrev:4; /* minor revision identifier */ 184 u_int cp_majrev:4; /* major revision identifier */ 185 u_int cp_imp:8; /* implementation identifier */ 186 u_int pad1:16; /* reserved */ 187 #endif 188 } cpu; 189 }; 190 191 192 #ifdef _KERNEL 193 194 /* 195 * Global variables used to communicate CPU type, and parameters 196 * such as cache size, from locore to higher-level code (e.g., pmap). 197 */ 198 extern union cpuprid cpu_id; 199 extern union cpuprid fpu_id; 200 extern int cpu_arch; 201 extern u_int mips_L1DataCacheSize; 202 extern u_int mips_L1InstCacheSize; 203 extern u_int mips_L1DataCacheLSize; 204 extern u_int mips_L1InstCacheLSize; 205 extern u_int mips_L2CacheSize; 206 extern u_int mips_L2CacheLSize; 207 extern u_int mips_CacheAliasMask; 208 extern struct intr_tab intr_tab[]; 209 #endif 210 211 #endif /* _MIPS_LOCORE_H */ 212
Indexes created Mon Sep 29 21:09:56 GMT 2025