locore.h revision 1.14
1 /* $NetBSD: locore.h,v 1.14 1998/09/11 16:46:31 jonathan Exp $ */ 2 3 /* 4 * Copyright 1996 The Board of Trustees of The Leland Stanford 5 * Junior University. All Rights Reserved. 6 * 7 * Permission to use, copy, modify, and distribute this 8 * software and its documentation for any purpose and without 9 * fee is hereby granted, provided that the above copyright 10 * notice appear in all copies. Stanford University 11 * makes no representations about the suitability of this 12 * software for any purpose. It is provided "as is" without 13 * express or implied warranty. 14 */ 15 16 /* 17 * Jump table for MIPS cpu locore functions that are implemented 18 * differently on different generations, or instruction-level 19 * archtecture (ISA) level, the Mips family. 20 * The following functions must be provided for each mips ISA level: 21 * 22 * 23 * MachConfigCache 24 * MachFlushCache 25 * MachFlushDCache 26 * MachFlushICache 27 * MachForceCacheUpdate 28 * MachSetPID 29 * MachTLBFlush 30 * MachTLBFlushAddr __P() 31 * MachTLBUpdate (u_int, (pt_entry_t?) u_int); 32 * wbflush 33 * proc_trampoline() 34 * switch_exit() 35 * cpu_switch_resume() 36 * 37 * We currently provide support for: 38 * 39 * r2000 and r3000 (mips ISA-I) 40 * r4000 and r4400 in 32-bit mode (mips ISA-III?) 41 */ 42 43 #ifndef _MIPS_LOCORE_H 44 #define _MIPS_LOCORE_H 45 46 /* 47 * locore service routine for exeception vectors. Used outside locore 48 * only to print them by name in stack tracebacks 49 */ 50 51 /* Block out one hardware interrupt-enable bit. */ 52 extern int Mach_spl0 __P((void)), Mach_spl1 __P((void)); 53 extern int Mach_spl2 __P((void)), Mach_spl3 __P((void)); 54 extern int Mach_spl4 __P((void)), Mach_spl5 __P((void)); 55 56 /* Block out nested interrupt-enable bits. */ 57 extern int cpu_spl0 __P((void)), cpu_spl1 __P((void)); 58 extern int cpu_spl2 __P((void)), cpu_spl3 __P((void)); 59 extern int cpu_spl4 __P((void)), cpu_spl5 __P((void)); 60 extern int splhigh __P((void)); 61 62 extern u_int32_t mips_read_causereg __P((void)); 63 extern u_int32_t mips_read_statusreg __P((void)); 64 65 extern void mips1_ConfigCache __P((void)); 66 extern void mips1_FlushCache __P((void)); 67 extern void mips1_FlushDCache __P((vm_offset_t addr, vm_offset_t len)); 68 extern void mips1_FlushICache __P((vm_offset_t addr, vm_offset_t len)); 69 extern void mips1_ForceCacheUpdate __P((void)); 70 extern void mips1_SetPID __P((int pid)); 71 extern void mips1_TLBFlush __P((int numtlb)); 72 extern void mips1_TLBFlushAddr __P( /* XXX Really pte highpart ? */ 73 (vm_offset_t addr)); 74 extern int mips1_TLBUpdate __P((u_int, /*pt_entry_t*/ u_int)); 75 extern void mips1_TLBWriteIndexed __P((u_int index, u_int high, 76 u_int low)); 77 extern void mips1_wbflush __P((void)); 78 extern void mips1_proc_trampoline __P((void)); 79 extern void mips1_switch_exit __P((struct proc *)); 80 extern void mips1_cpu_switch_resume __P((void)); 81 82 extern void mips3_ConfigCache __P((void)); 83 extern void mips3_FlushCache __P((void)); 84 extern void mips3_FlushDCache __P((vm_offset_t addr, vm_offset_t len)); 85 extern void mips3_FlushICache __P((vm_offset_t addr, vm_offset_t len)); 86 extern void mips3_ForceCacheUpdate __P((void)); 87 extern void mips3_HitFlushDCache __P((vm_offset_t, int)); 88 extern void mips3_SetPID __P((int pid)); 89 extern void mips3_TLBFlush __P((int numtlb)); 90 extern void mips3_TLBFlushAddr __P( /* XXX Really pte highpart ? */ 91 (vm_offset_t addr)); 92 extern int mips3_TLBUpdate __P((u_int, /*pt_entry_t*/ u_int)); 93 struct tlb; 94 extern void mips3_TLBRead __P((int, struct tlb *)); 95 extern void mips3_TLBWriteIndexedVPS __P((u_int index, struct tlb *tlb)); 96 extern void mips3_TLBWriteIndexed __P((u_int index, u_int high, 97 u_int lo0, u_int lo1)); 98 extern void mips3_wbflush __P((void)); 99 extern void mips3_proc_trampoline __P((void)); 100 extern void mips3_switch_exit __P((struct proc *)); 101 extern void mips3_cpu_switch_resume __P((void)); 102 103 extern void mips3_SetWIRED __P((int)); 104 105 extern u_int32_t mips3_cycle_count __P((void)); 106 extern u_int32_t mips3_read_compare __P((void)); 107 extern u_int32_t mips3_read_config __P((void)); 108 extern void mips3_write_compare __P((u_int32_t)); 109 110 /* 111 * A vector with an entry for each mips-ISA-level dependent 112 * locore function, and macros which jump through it. 113 * XXX the macro names are chosen to be compatible with the old 114 * Sprite coding-convention names used in 4.4bsd/pmax. 115 */ 116 typedef struct { 117 void (*configCache) __P((void)); 118 void (*flushCache) __P((void)); 119 void (*flushDCache) __P((vm_offset_t addr, vm_offset_t len)); 120 void (*flushICache) __P((vm_offset_t addr, vm_offset_t len)); 121 void (*forceCacheUpdate) __P((void)); 122 void (*setTLBpid) __P((int pid)); 123 void (*tlbFlush) __P((int numtlb)); 124 void (*tlbFlushAddr) __P((vm_offset_t)); /* XXX Really pte highpart ? */ 125 int (*tlbUpdate) __P((u_int highreg, u_int lowreg)); 126 void (*wbflush) __P((void)); 127 void (*proc_trampoline) __P((void)); 128 void (*mips_switch_exit) __P((struct proc *)); 129 void (*cpu_switch_resume) __P((void)); 130 } mips_locore_jumpvec_t; 131 132 /* Override writebuffer-drain method. */ 133 void mips_set_wbflush __P((void (*) __P((void)) )); 134 135 136 /* 137 * The "active" locore-fuction vector, and 138 139 */ 140 extern mips_locore_jumpvec_t mips_locore_jumpvec; 141 extern mips_locore_jumpvec_t r2000_locore_vec; 142 extern mips_locore_jumpvec_t r4000_locore_vec; 143 144 #if defined(MIPS3) && !defined (MIPS1) 145 #define MachConfigCache mips3_ConfigCache 146 #define MachFlushCache mips3_FlushCache 147 #define MachFlushDCache mips3_FlushDCache 148 #define MachFlushICache mips3_FlushICache 149 #define MachForceCacheUpdate mips3_ForceCacheUpdate 150 #define MachSetPID mips3_SetPID 151 #define MachTLBFlush() mips3_TLBFlush(mips_num_tlb_entries) 152 #define MachTLBFlushAddr mips3_TLBFlushAddr 153 #define MachTLBUpdate mips3_TLBUpdate 154 #define wbflush mips3_wbflush 155 #define proc_trampoline mips3_proc_trampoline 156 #define switch_exit mips3_switch_exit 157 #endif 158 159 #if !defined(MIPS3) && defined (MIPS1) 160 #define MachConfigCache mips1_ConfigCache 161 #define MachFlushCache mips1_FlushCache 162 #define MachFlushDCache mips1_FlushDCache 163 #define MachFlushICache mips1_FlushICache 164 #define MachForceCacheUpdate mips1_ForceCacheUpdate 165 #define MachSetPID mips1_SetPID 166 #define MachTLBFlush() mips1_TLBFlush(MIPS1_TLB_NUM_TLB_ENTRIES) 167 #define MachTLBFlushAddr mips1_TLBFlushAddr 168 #define MachTLBUpdate mips1_TLBUpdate 169 #define wbflush mips1_wbflush 170 #define proc_trampoline mips1_proc_trampoline 171 #define switch_exit mips1_switch_exit 172 #endif 173 174 175 176 #if defined(MIPS3) && defined (MIPS1) 177 #define MachConfigCache (*(mips_locore_jumpvec.configCache)) 178 #define MachFlushCache (*(mips_locore_jumpvec.flushCache)) 179 #define MachFlushDCache (*(mips_locore_jumpvec.flushDCache)) 180 #define MachFlushICache (*(mips_locore_jumpvec.flushICache)) 181 #define MachForceCacheUpdate (*(mips_locore_jumpvec.forceCacheUpdate)) 182 #define MachSetPID (*(mips_locore_jumpvec.setTLBpid)) 183 #define MachTLBFlush() (*(mips_locore_jumpvec.tlbFlush))(mips_num_tlb_entries) 184 #define MachTLBFlushAddr (*(mips_locore_jumpvec.tlbFlushAddr)) 185 #define MachTLBUpdate (*(mips_locore_jumpvec.tlbUpdate)) 186 #define wbflush (*(mips_locore_jumpvec.wbflush)) 187 #define proc_trampoline (mips_locore_jumpvec.proc_trampoline) 188 #define switch_exit (*(mips_locore_jumpvec.mips_switch_exit)) 189 #endif 190 191 /* cpu_switch_resume not called directly */ 192 193 194 /* 195 * CPU identification, from PRID register. 196 */ 197 union cpuprid { 198 int cpuprid; 199 struct { 200 #if BYTE_ORDER == BIG_ENDIAN 201 u_int pad1:16; /* reserved */ 202 u_int cp_imp:8; /* implementation identifier */ 203 u_int cp_majrev:4; /* major revision identifier */ 204 u_int cp_minrev:4; /* minor revision identifier */ 205 #else 206 u_int cp_minrev:4; /* minor revision identifier */ 207 u_int cp_majrev:4; /* major revision identifier */ 208 u_int cp_imp:8; /* implementation identifier */ 209 u_int pad1:16; /* reserved */ 210 #endif 211 } cpu; 212 }; 213 214 215 #ifdef _KERNEL 216 217 /* 218 * Global variables used to communicate CPU type, and parameters 219 * such as cache size, from locore to higher-level code (e.g., pmap). 220 */ 221 extern union cpuprid cpu_id; 222 extern union cpuprid fpu_id; 223 extern int cpu_arch; 224 extern int mips_num_tlb_entries; 225 extern u_int mips_L1DCacheSize; 226 extern u_int mips_L1ICacheSize; 227 extern u_int mips_L1DCacheLSize; 228 extern u_int mips_L1ICacheLSize; 229 extern int mips_L2CachePresent; 230 extern u_int mips_L2CacheLSize; 231 extern u_int mips_CacheAliasMask; 232 extern struct intr_tab intr_tab[]; 233 234 #ifdef MIPS3 235 extern int mips3_L1TwoWayCache; 236 extern int mips3_cacheflush_bug; 237 #endif /* MIPS3 */ 238 239 #endif 240 241 #endif /* _MIPS_LOCORE_H */ 242
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