locore.h revision 1.16
1 /* $NetBSD: locore.h,v 1.16 1999/01/14 18:45:46 castor Exp $ */ 2 3 /* 4 * Copyright 1996 The Board of Trustees of The Leland Stanford 5 * Junior University. All Rights Reserved. 6 * 7 * Permission to use, copy, modify, and distribute this 8 * software and its documentation for any purpose and without 9 * fee is hereby granted, provided that the above copyright 10 * notice appear in all copies. Stanford University 11 * makes no representations about the suitability of this 12 * software for any purpose. It is provided "as is" without 13 * express or implied warranty. 14 */ 15 16 /* 17 * Jump table for MIPS cpu locore functions that are implemented 18 * differently on different generations, or instruction-level 19 * archtecture (ISA) level, the Mips family. 20 * The following functions must be provided for each mips ISA level: 21 * 22 * 23 * MachFlushCache 24 * MachFlushDCache 25 * MachFlushICache 26 * MachForceCacheUpdate 27 * MachSetPID 28 * MachTLBFlush 29 * MachTLBFlushAddr 30 * MachTLBUpdate 31 * wbflush 32 * proc_trampoline() 33 * cpu_switch_resume() 34 * 35 * We currently provide support for: 36 * 37 * r2000 and r3000 (mips ISA-I) 38 * r4000 and r4400 in 32-bit mode (mips ISA-III?) 39 */ 40 41 #ifndef _MIPS_LOCORE_H 42 #define _MIPS_LOCORE_H 43 44 #include "opt_mips_cache.h" 45 46 /* 47 * locore service routine for exception vectors. Used outside locore 48 * only to print them by name in stack tracebacks 49 */ 50 51 extern u_int32_t mips_read_causereg __P((void)); 52 extern u_int32_t mips_read_statusreg __P((void)); 53 54 extern void mips1_ConfigCache __P((void)); 55 extern void mips1_FlushCache __P((void)); 56 extern void mips1_FlushDCache __P((vaddr_t addr, vsize_t len)); 57 extern void mips1_FlushICache __P((vaddr_t addr, vsize_t len)); 58 extern void mips1_ForceCacheUpdate __P((void)); 59 extern void mips1_SetPID __P((int pid)); 60 extern void mips1_TLBFlush __P((int numtlb)); 61 extern void mips1_TLBFlushAddr __P( /* XXX Really pte highpart ? */ 62 (vaddr_t addr)); 63 extern int mips1_TLBUpdate __P((u_int, /*pt_entry_t*/ u_int)); 64 extern void mips1_TLBWriteIndexed __P((u_int index, u_int high, 65 u_int low)); 66 extern void mips1_wbflush __P((void)); 67 extern void mips1_proc_trampoline __P((void)); 68 extern void mips1_cpu_switch_resume __P((void)); 69 70 extern void mips3_ConfigCache __P((void)); 71 extern void mips3_FlushCache __P((void)); 72 extern void mips3_FlushDCache __P((vaddr_t addr, vaddr_t len)); 73 #ifdef MIPS3_L2CACHE_ABSENT 74 extern void mips52xx_FlushDCache __P((vaddr_t addr, vaddr_t len)); 75 #endif 76 extern void mips3_FlushICache __P((vaddr_t addr, vaddr_t len)); 77 extern void mips3_ForceCacheUpdate __P((void)); 78 extern void mips3_HitFlushDCache __P((vaddr_t, int)); 79 extern void mips3_SetPID __P((int pid)); 80 extern void mips3_TLBFlush __P((int numtlb)); 81 extern void mips3_TLBFlushAddr __P( /* XXX Really pte highpart ? */ 82 (vaddr_t addr)); 83 extern int mips3_TLBUpdate __P((u_int, /*pt_entry_t*/ u_int)); 84 struct tlb; 85 extern void mips3_TLBRead __P((int, struct tlb *)); 86 #if 0 87 extern void mips3_TLBWriteIndexedVPS __P((u_int index, struct tlb *tlb)); 88 extern void mips3_TLBWriteIndexed __P((u_int index, u_int high, 89 u_int lo0, u_int lo1)); 90 #endif 91 extern void mips3_wbflush __P((void)); 92 extern void mips3_proc_trampoline __P((void)); 93 extern void mips3_cpu_switch_resume __P((void)); 94 95 extern void mips3_SetWIRED __P((int)); 96 97 extern u_int32_t mips3_cycle_count __P((void)); 98 extern u_int32_t mips3_write_count __P((u_int32_t)); 99 extern u_int32_t mips3_read_compare __P((void)); 100 extern u_int32_t mips3_read_config __P((void)); 101 extern void mips3_write_compare __P((u_int32_t)); 102 extern void mips3_write_xcontext_upper __P((u_int32_t)); 103 104 /* 105 * A vector with an entry for each mips-ISA-level dependent 106 * locore function, and macros which jump through it. 107 * XXX the macro names are chosen to be compatible with the old 108 * Sprite coding-convention names used in 4.4bsd/pmax. 109 */ 110 typedef struct { 111 void (*flushCache) __P((void)); 112 void (*flushDCache) __P((vaddr_t addr, vsize_t len)); 113 void (*flushICache) __P((vaddr_t addr, vsize_t len)); 114 void (*forceCacheUpdate) __P((void)); 115 void (*setTLBpid) __P((int pid)); 116 void (*tlbFlush) __P((int numtlb)); 117 void (*tlbFlushAddr) __P((vaddr_t)); /* XXX Really pte highpart ? */ 118 int (*tlbUpdate) __P((u_int highreg, u_int lowreg)); 119 void (*wbflush) __P((void)); 120 void (*proc_trampoline) __P((void)); 121 void (*cpu_switch_resume) __P((void)); 122 } mips_locore_jumpvec_t; 123 124 /* Override writebuffer-drain method. */ 125 void mips_set_wbflush __P((void (*) __P((void)) )); 126 127 128 /* 129 * The "active" locore-fuction vector, and 130 131 */ 132 extern mips_locore_jumpvec_t mips_locore_jumpvec; 133 extern mips_locore_jumpvec_t r2000_locore_vec; 134 extern mips_locore_jumpvec_t r4000_locore_vec; 135 136 #if defined(MIPS3) && !defined (MIPS1) 137 #define MachFlushCache mips3_FlushCache 138 #if defined(MIPS3_L2CACHE_ABSENT) && !defined(MIPS3_L2CACHE_PRESENT) 139 #define MachFlushDCache mips52xx_FlushDCache 140 #elif !defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_L2CACHE_PRESENT) 141 #define MachFlushDCache mips3_FlushDCache 142 #else 143 #define MachFlushDCache (*(mips_locore_jumpvec.flushDCache)) 144 #endif 145 #define MachFlushICache mips3_FlushICache 146 #define MachForceCacheUpdate mips3_ForceCacheUpdate 147 #define MachSetPID mips3_SetPID 148 #define MachTLBFlush() mips3_TLBFlush(mips_num_tlb_entries) 149 #define MachTLBFlushAddr mips3_TLBFlushAddr 150 #define MachTLBUpdate mips3_TLBUpdate 151 #define wbflush mips3_wbflush 152 #define proc_trampoline mips3_proc_trampoline 153 #endif 154 155 #if !defined(MIPS3) && defined (MIPS1) 156 #define MachFlushCache mips1_FlushCache 157 #define MachFlushDCache mips1_FlushDCache 158 #define MachFlushICache mips1_FlushICache 159 #define MachForceCacheUpdate mips1_ForceCacheUpdate 160 #define MachSetPID mips1_SetPID 161 #define MachTLBFlush() mips1_TLBFlush(MIPS1_TLB_NUM_TLB_ENTRIES) 162 #define MachTLBFlushAddr mips1_TLBFlushAddr 163 #define MachTLBUpdate mips1_TLBUpdate 164 #define wbflush mips1_wbflush 165 #define proc_trampoline mips1_proc_trampoline 166 #endif 167 168 169 170 #if defined(MIPS3) && defined (MIPS1) 171 #define MachFlushCache (*(mips_locore_jumpvec.flushCache)) 172 #define MachFlushDCache (*(mips_locore_jumpvec.flushDCache)) 173 #define MachFlushICache (*(mips_locore_jumpvec.flushICache)) 174 #define MachForceCacheUpdate (*(mips_locore_jumpvec.forceCacheUpdate)) 175 #define MachSetPID (*(mips_locore_jumpvec.setTLBpid)) 176 #define MachTLBFlush() (*(mips_locore_jumpvec.tlbFlush))(mips_num_tlb_entries) 177 #define MachTLBFlushAddr (*(mips_locore_jumpvec.tlbFlushAddr)) 178 #define MachTLBUpdate (*(mips_locore_jumpvec.tlbUpdate)) 179 #define wbflush (*(mips_locore_jumpvec.wbflush)) 180 #define proc_trampoline (mips_locore_jumpvec.proc_trampoline) 181 #endif 182 183 /* cpu_switch_resume is called inside locore.S */ 184 185 /* 186 * CPU identification, from PRID register. 187 */ 188 union cpuprid { 189 int cpuprid; 190 struct { 191 #if BYTE_ORDER == BIG_ENDIAN 192 u_int pad1:16; /* reserved */ 193 u_int cp_imp:8; /* implementation identifier */ 194 u_int cp_majrev:4; /* major revision identifier */ 195 u_int cp_minrev:4; /* minor revision identifier */ 196 #else 197 u_int cp_minrev:4; /* minor revision identifier */ 198 u_int cp_majrev:4; /* major revision identifier */ 199 u_int cp_imp:8; /* implementation identifier */ 200 u_int pad1:16; /* reserved */ 201 #endif 202 } cpu; 203 }; 204 205 206 #ifdef _KERNEL 207 208 /* 209 * Global variables used to communicate CPU type, and parameters 210 * such as cache size, from locore to higher-level code (e.g., pmap). 211 */ 212 extern union cpuprid cpu_id; 213 extern union cpuprid fpu_id; 214 extern int cpu_arch; 215 extern int mips_num_tlb_entries; 216 extern u_int mips_L1DCacheSize; 217 extern u_int mips_L1ICacheSize; 218 extern u_int mips_L1DCacheLSize; 219 extern u_int mips_L1ICacheLSize; 220 extern int mips_L2CachePresent; 221 extern u_int mips_L2CacheLSize; 222 extern u_int mips_CacheAliasMask; 223 224 #ifdef MIPS3 225 extern int mips3_L1TwoWayCache; 226 extern int mips3_cacheflush_bug; 227 #endif /* MIPS3 */ 228 229 #endif 230 231 #endif /* _MIPS_LOCORE_H */ 232
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