locore.h revision 1.17
1 /* $NetBSD: locore.h,v 1.17 1999/01/15 10:07:12 castor Exp $ */ 2 3 /* 4 * Copyright 1996 The Board of Trustees of The Leland Stanford 5 * Junior University. All Rights Reserved. 6 * 7 * Permission to use, copy, modify, and distribute this 8 * software and its documentation for any purpose and without 9 * fee is hereby granted, provided that the above copyright 10 * notice appear in all copies. Stanford University 11 * makes no representations about the suitability of this 12 * software for any purpose. It is provided "as is" without 13 * express or implied warranty. 14 */ 15 16 /* 17 * Jump table for MIPS cpu locore functions that are implemented 18 * differently on different generations, or instruction-level 19 * archtecture (ISA) level, the Mips family. 20 * The following functions must be provided for each mips ISA level: 21 * 22 * 23 * MachFlushCache 24 * MachFlushDCache 25 * MachFlushICache 26 * MachForceCacheUpdate 27 * MachSetPID 28 * MachTLBFlush 29 * MachTLBFlushAddr 30 * MachTLBUpdate 31 * wbflush 32 * proc_trampoline() 33 * cpu_switch_resume() 34 * 35 * We currently provide support for: 36 * 37 * r2000 and r3000 (mips ISA-I) 38 * r4000 and r4400 in 32-bit mode (mips ISA-III?) 39 */ 40 41 #ifndef _MIPS_LOCORE_H 42 #define _MIPS_LOCORE_H 43 44 #ifndef _LKM 45 #include "opt_mips_cache.h" 46 #endif 47 48 /* 49 * locore service routine for exception vectors. Used outside locore 50 * only to print them by name in stack tracebacks 51 */ 52 53 extern u_int32_t mips_read_causereg __P((void)); 54 extern u_int32_t mips_read_statusreg __P((void)); 55 56 extern void mips1_ConfigCache __P((void)); 57 extern void mips1_FlushCache __P((void)); 58 extern void mips1_FlushDCache __P((vaddr_t addr, vsize_t len)); 59 extern void mips1_FlushICache __P((vaddr_t addr, vsize_t len)); 60 extern void mips1_ForceCacheUpdate __P((void)); 61 extern void mips1_SetPID __P((int pid)); 62 extern void mips1_TLBFlush __P((int numtlb)); 63 extern void mips1_TLBFlushAddr __P( /* XXX Really pte highpart ? */ 64 (vaddr_t addr)); 65 extern int mips1_TLBUpdate __P((u_int, /*pt_entry_t*/ u_int)); 66 extern void mips1_TLBWriteIndexed __P((u_int index, u_int high, 67 u_int low)); 68 extern void mips1_wbflush __P((void)); 69 extern void mips1_proc_trampoline __P((void)); 70 extern void mips1_cpu_switch_resume __P((void)); 71 72 extern void mips3_ConfigCache __P((void)); 73 extern void mips3_FlushCache __P((void)); 74 extern void mips3_FlushDCache __P((vaddr_t addr, vaddr_t len)); 75 #ifdef MIPS3_L2CACHE_ABSENT 76 extern void mips52xx_FlushDCache __P((vaddr_t addr, vaddr_t len)); 77 #endif 78 extern void mips3_FlushICache __P((vaddr_t addr, vaddr_t len)); 79 extern void mips3_ForceCacheUpdate __P((void)); 80 extern void mips3_HitFlushDCache __P((vaddr_t, int)); 81 extern void mips3_SetPID __P((int pid)); 82 extern void mips3_TLBFlush __P((int numtlb)); 83 extern void mips3_TLBFlushAddr __P( /* XXX Really pte highpart ? */ 84 (vaddr_t addr)); 85 extern int mips3_TLBUpdate __P((u_int, /*pt_entry_t*/ u_int)); 86 struct tlb; 87 extern void mips3_TLBRead __P((int, struct tlb *)); 88 #if 0 89 extern void mips3_TLBWriteIndexedVPS __P((u_int index, struct tlb *tlb)); 90 extern void mips3_TLBWriteIndexed __P((u_int index, u_int high, 91 u_int lo0, u_int lo1)); 92 #endif 93 extern void mips3_wbflush __P((void)); 94 extern void mips3_proc_trampoline __P((void)); 95 extern void mips3_cpu_switch_resume __P((void)); 96 97 extern void mips3_SetWIRED __P((int)); 98 99 extern u_int32_t mips3_cycle_count __P((void)); 100 extern u_int32_t mips3_write_count __P((u_int32_t)); 101 extern u_int32_t mips3_read_compare __P((void)); 102 extern u_int32_t mips3_read_config __P((void)); 103 extern void mips3_write_compare __P((u_int32_t)); 104 extern void mips3_write_xcontext_upper __P((u_int32_t)); 105 106 /* 107 * A vector with an entry for each mips-ISA-level dependent 108 * locore function, and macros which jump through it. 109 * XXX the macro names are chosen to be compatible with the old 110 * Sprite coding-convention names used in 4.4bsd/pmax. 111 */ 112 typedef struct { 113 void (*flushCache) __P((void)); 114 void (*flushDCache) __P((vaddr_t addr, vsize_t len)); 115 void (*flushICache) __P((vaddr_t addr, vsize_t len)); 116 void (*forceCacheUpdate) __P((void)); 117 void (*setTLBpid) __P((int pid)); 118 void (*tlbFlush) __P((int numtlb)); 119 void (*tlbFlushAddr) __P((vaddr_t)); /* XXX Really pte highpart ? */ 120 int (*tlbUpdate) __P((u_int highreg, u_int lowreg)); 121 void (*wbflush) __P((void)); 122 void (*proc_trampoline) __P((void)); 123 void (*cpu_switch_resume) __P((void)); 124 } mips_locore_jumpvec_t; 125 126 /* Override writebuffer-drain method. */ 127 void mips_set_wbflush __P((void (*) __P((void)) )); 128 129 130 /* 131 * The "active" locore-fuction vector, and 132 133 */ 134 extern mips_locore_jumpvec_t mips_locore_jumpvec; 135 extern mips_locore_jumpvec_t r2000_locore_vec; 136 extern mips_locore_jumpvec_t r4000_locore_vec; 137 138 #if defined(MIPS3) && !defined (MIPS1) 139 #define MachFlushCache mips3_FlushCache 140 #if defined(MIPS3_L2CACHE_ABSENT) && !defined(MIPS3_L2CACHE_PRESENT) 141 #define MachFlushDCache mips52xx_FlushDCache 142 #elif !defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_L2CACHE_PRESENT) 143 #define MachFlushDCache mips3_FlushDCache 144 #else 145 #define MachFlushDCache (*(mips_locore_jumpvec.flushDCache)) 146 #endif 147 #define MachFlushICache mips3_FlushICache 148 #define MachForceCacheUpdate mips3_ForceCacheUpdate 149 #define MachSetPID mips3_SetPID 150 #define MachTLBFlush() mips3_TLBFlush(mips_num_tlb_entries) 151 #define MachTLBFlushAddr mips3_TLBFlushAddr 152 #define MachTLBUpdate mips3_TLBUpdate 153 #define wbflush mips3_wbflush 154 #define proc_trampoline mips3_proc_trampoline 155 #endif 156 157 #if !defined(MIPS3) && defined (MIPS1) 158 #define MachFlushCache mips1_FlushCache 159 #define MachFlushDCache mips1_FlushDCache 160 #define MachFlushICache mips1_FlushICache 161 #define MachForceCacheUpdate mips1_ForceCacheUpdate 162 #define MachSetPID mips1_SetPID 163 #define MachTLBFlush() mips1_TLBFlush(MIPS1_TLB_NUM_TLB_ENTRIES) 164 #define MachTLBFlushAddr mips1_TLBFlushAddr 165 #define MachTLBUpdate mips1_TLBUpdate 166 #define wbflush mips1_wbflush 167 #define proc_trampoline mips1_proc_trampoline 168 #endif 169 170 171 172 #if defined(MIPS3) && defined (MIPS1) 173 #define MachFlushCache (*(mips_locore_jumpvec.flushCache)) 174 #define MachFlushDCache (*(mips_locore_jumpvec.flushDCache)) 175 #define MachFlushICache (*(mips_locore_jumpvec.flushICache)) 176 #define MachForceCacheUpdate (*(mips_locore_jumpvec.forceCacheUpdate)) 177 #define MachSetPID (*(mips_locore_jumpvec.setTLBpid)) 178 #define MachTLBFlush() (*(mips_locore_jumpvec.tlbFlush))(mips_num_tlb_entries) 179 #define MachTLBFlushAddr (*(mips_locore_jumpvec.tlbFlushAddr)) 180 #define MachTLBUpdate (*(mips_locore_jumpvec.tlbUpdate)) 181 #define wbflush (*(mips_locore_jumpvec.wbflush)) 182 #define proc_trampoline (mips_locore_jumpvec.proc_trampoline) 183 #endif 184 185 /* cpu_switch_resume is called inside locore.S */ 186 187 /* 188 * CPU identification, from PRID register. 189 */ 190 union cpuprid { 191 int cpuprid; 192 struct { 193 #if BYTE_ORDER == BIG_ENDIAN 194 u_int pad1:16; /* reserved */ 195 u_int cp_imp:8; /* implementation identifier */ 196 u_int cp_majrev:4; /* major revision identifier */ 197 u_int cp_minrev:4; /* minor revision identifier */ 198 #else 199 u_int cp_minrev:4; /* minor revision identifier */ 200 u_int cp_majrev:4; /* major revision identifier */ 201 u_int cp_imp:8; /* implementation identifier */ 202 u_int pad1:16; /* reserved */ 203 #endif 204 } cpu; 205 }; 206 207 208 #ifdef _KERNEL 209 210 /* 211 * Global variables used to communicate CPU type, and parameters 212 * such as cache size, from locore to higher-level code (e.g., pmap). 213 */ 214 extern union cpuprid cpu_id; 215 extern union cpuprid fpu_id; 216 extern int cpu_arch; 217 extern int mips_num_tlb_entries; 218 extern u_int mips_L1DCacheSize; 219 extern u_int mips_L1ICacheSize; 220 extern u_int mips_L1DCacheLSize; 221 extern u_int mips_L1ICacheLSize; 222 extern int mips_L2CachePresent; 223 extern u_int mips_L2CacheLSize; 224 extern u_int mips_CacheAliasMask; 225 226 #ifdef MIPS3 227 extern int mips3_L1TwoWayCache; 228 extern int mips3_cacheflush_bug; 229 #endif /* MIPS3 */ 230 231 #endif 232 233 #endif /* _MIPS_LOCORE_H */ 234
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