locore.h revision 1.20
1 /* $NetBSD: locore.h,v 1.20 1999/04/24 08:10:35 simonb Exp $ */ 2 3 /* 4 * Copyright 1996 The Board of Trustees of The Leland Stanford 5 * Junior University. All Rights Reserved. 6 * 7 * Permission to use, copy, modify, and distribute this 8 * software and its documentation for any purpose and without 9 * fee is hereby granted, provided that the above copyright 10 * notice appear in all copies. Stanford University 11 * makes no representations about the suitability of this 12 * software for any purpose. It is provided "as is" without 13 * express or implied warranty. 14 */ 15 16 /* 17 * Jump table for MIPS cpu locore functions that are implemented 18 * differently on different generations, or instruction-level 19 * archtecture (ISA) level, the Mips family. 20 * The following functions must be provided for each mips ISA level: 21 * 22 * 23 * MachFlushCache 24 * MachFlushDCache 25 * MachFlushICache 26 * MachForceCacheUpdate 27 * MachSetPID 28 * MachTLBFlush 29 * MachTLBFlushAddr 30 * MachTLBUpdate 31 * wbflush 32 * proc_trampoline() 33 * cpu_switch_resume() 34 * 35 * We currently provide support for: 36 * 37 * r2000 and r3000 (mips ISA-I) 38 * r4000 and r4400 in 32-bit mode (mips ISA-III?) 39 */ 40 41 #ifndef _MIPS_LOCORE_H 42 #define _MIPS_LOCORE_H 43 44 #ifndef _LKM 45 #include "opt_mips_cache.h" 46 #endif 47 48 /* 49 * locore service routine for exception vectors. Used outside locore 50 * only to print them by name in stack tracebacks 51 */ 52 53 extern u_int32_t mips_read_causereg __P((void)); 54 extern u_int32_t mips_read_statusreg __P((void)); 55 56 extern void mips1_ConfigCache __P((void)); 57 extern void mips1_FlushCache __P((void)); 58 extern void mips1_FlushDCache __P((vaddr_t addr, vsize_t len)); 59 extern void mips1_FlushICache __P((vaddr_t addr, vsize_t len)); 60 extern void mips1_ForceCacheUpdate __P((void)); 61 extern void mips1_SetPID __P((int pid)); 62 extern void mips1_clean_tlb __P((void)); 63 extern void mips1_TLBFlush __P((int numtlb)); 64 extern void mips1_TLBFlushAddr __P( /* XXX Really pte highpart ? */ 65 (vaddr_t addr)); 66 extern int mips1_TLBUpdate __P((u_int, /*pt_entry_t*/ u_int)); 67 extern void mips1_TLBWriteIndexed __P((u_int index, u_int high, 68 u_int low)); 69 extern void mips1_wbflush __P((void)); 70 extern void mips1_proc_trampoline __P((void)); 71 extern void mips1_cpu_switch_resume __P((void)); 72 73 extern void mips3_ConfigCache __P((void)); 74 extern void mips3_FlushCache __P((void)); 75 extern void mips3_FlushDCache __P((vaddr_t addr, vaddr_t len)); 76 #ifdef MIPS3_L2CACHE_ABSENT 77 extern void mips52xx_FlushDCache __P((vaddr_t addr, vaddr_t len)); 78 #endif 79 extern void mips3_FlushICache __P((vaddr_t addr, vaddr_t len)); 80 extern void mips3_ForceCacheUpdate __P((void)); 81 extern void mips3_HitFlushDCache __P((vaddr_t, int)); 82 extern void mips3_SetPID __P((int pid)); 83 extern void mips3_TLBFlush __P((int numtlb)); 84 extern void mips3_TLBFlushAddr __P( /* XXX Really pte highpart ? */ 85 (vaddr_t addr)); 86 extern int mips3_TLBUpdate __P((u_int, /*pt_entry_t*/ u_int)); 87 struct tlb; 88 extern void mips3_TLBRead __P((int, struct tlb *)); 89 #if 0 90 extern void mips3_TLBWriteIndexedVPS __P((u_int index, struct tlb *tlb)); 91 extern void mips3_TLBWriteIndexed __P((u_int index, u_int high, 92 u_int lo0, u_int lo1)); 93 #endif 94 extern void mips3_wbflush __P((void)); 95 extern void mips3_proc_trampoline __P((void)); 96 extern void mips3_cpu_switch_resume __P((void)); 97 98 extern void mips3_SetWIRED __P((int)); 99 100 extern u_int32_t mips3_cycle_count __P((void)); 101 extern u_int32_t mips3_write_count __P((u_int32_t)); 102 extern u_int32_t mips3_read_compare __P((void)); 103 extern u_int32_t mips3_read_config __P((void)); 104 extern void mips3_write_compare __P((u_int32_t)); 105 extern void mips3_write_xcontext_upper __P((u_int32_t)); 106 107 /* 108 * A vector with an entry for each mips-ISA-level dependent 109 * locore function, and macros which jump through it. 110 * XXX the macro names are chosen to be compatible with the old 111 * Sprite coding-convention names used in 4.4bsd/pmax. 112 */ 113 typedef struct { 114 void (*flushCache) __P((void)); 115 void (*flushDCache) __P((vaddr_t addr, vsize_t len)); 116 void (*flushICache) __P((vaddr_t addr, vsize_t len)); 117 void (*forceCacheUpdate) __P((void)); 118 void (*setTLBpid) __P((int pid)); 119 void (*tlbFlush) __P((int numtlb)); 120 void (*tlbFlushAddr) __P((vaddr_t)); /* XXX Really pte highpart ? */ 121 int (*tlbUpdate) __P((u_int highreg, u_int lowreg)); 122 void (*wbflush) __P((void)); 123 void (*proc_trampoline) __P((void)); 124 void (*cpu_switch_resume) __P((void)); 125 } mips_locore_jumpvec_t; 126 127 /* Override writebuffer-drain method. */ 128 void mips_set_wbflush __P((void (*) __P((void)) )); 129 130 131 /* 132 * The "active" locore-fuction vector, and 133 134 */ 135 extern mips_locore_jumpvec_t mips_locore_jumpvec; 136 extern mips_locore_jumpvec_t r2000_locore_vec; 137 extern mips_locore_jumpvec_t r4000_locore_vec; 138 139 #if defined(MIPS3) && !defined (MIPS1) 140 #define MachFlushCache mips3_FlushCache 141 #if defined(MIPS3_L2CACHE_ABSENT) && !defined(MIPS3_L2CACHE_PRESENT) 142 #define MachFlushDCache mips52xx_FlushDCache 143 #elif !defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_L2CACHE_PRESENT) 144 #define MachFlushDCache mips3_FlushDCache 145 #else 146 #define MachFlushDCache (*(mips_locore_jumpvec.flushDCache)) 147 #endif 148 #define MachFlushICache mips3_FlushICache 149 #define MachForceCacheUpdate mips3_ForceCacheUpdate 150 #define MachSetPID mips3_SetPID 151 #define MachTLBFlush() mips3_TLBFlush(mips_num_tlb_entries) 152 #define MachTLBFlushAddr mips3_TLBFlushAddr 153 #define MachTLBUpdate mips3_TLBUpdate 154 #define wbflush mips3_wbflush 155 #define proc_trampoline mips3_proc_trampoline 156 #endif 157 158 #if !defined(MIPS3) && defined (MIPS1) 159 #define MachFlushCache mips1_FlushCache 160 #define MachFlushDCache mips1_FlushDCache 161 #define MachFlushICache mips1_FlushICache 162 #define MachForceCacheUpdate mips1_ForceCacheUpdate 163 #define MachSetPID mips1_SetPID 164 #define MachTLBFlush() mips1_TLBFlush(MIPS1_TLB_NUM_TLB_ENTRIES) 165 #define MachTLBFlushAddr mips1_TLBFlushAddr 166 #define MachTLBUpdate mips1_TLBUpdate 167 #define wbflush mips1_wbflush 168 #define proc_trampoline mips1_proc_trampoline 169 #endif 170 171 172 173 #if defined(MIPS3) && defined (MIPS1) 174 #define MachFlushCache (*(mips_locore_jumpvec.flushCache)) 175 #define MachFlushDCache (*(mips_locore_jumpvec.flushDCache)) 176 #define MachFlushICache (*(mips_locore_jumpvec.flushICache)) 177 #define MachForceCacheUpdate (*(mips_locore_jumpvec.forceCacheUpdate)) 178 #define MachSetPID (*(mips_locore_jumpvec.setTLBpid)) 179 #define MachTLBFlush() (*(mips_locore_jumpvec.tlbFlush))(mips_num_tlb_entries) 180 #define MachTLBFlushAddr (*(mips_locore_jumpvec.tlbFlushAddr)) 181 #define MachTLBUpdate (*(mips_locore_jumpvec.tlbUpdate)) 182 #define wbflush (*(mips_locore_jumpvec.wbflush)) 183 #define proc_trampoline (mips_locore_jumpvec.proc_trampoline) 184 #endif 185 186 /* cpu_switch_resume is called inside locore.S */ 187 188 /* 189 * CPU identification, from PRID register. 190 */ 191 union cpuprid { 192 int cpuprid; 193 struct { 194 #if BYTE_ORDER == BIG_ENDIAN 195 u_int pad1:16; /* reserved */ 196 u_int cp_imp:8; /* implementation identifier */ 197 u_int cp_majrev:4; /* major revision identifier */ 198 u_int cp_minrev:4; /* minor revision identifier */ 199 #else 200 u_int cp_minrev:4; /* minor revision identifier */ 201 u_int cp_majrev:4; /* major revision identifier */ 202 u_int cp_imp:8; /* implementation identifier */ 203 u_int pad1:16; /* reserved */ 204 #endif 205 } cpu; 206 }; 207 208 209 #ifdef _KERNEL 210 211 /* 212 * Global variables used to communicate CPU type, and parameters 213 * such as cache size, from locore to higher-level code (e.g., pmap). 214 */ 215 extern union cpuprid cpu_id; 216 extern union cpuprid fpu_id; 217 extern int cpu_arch; 218 extern int mips_num_tlb_entries; 219 extern u_int mips_L1DCacheSize; 220 extern u_int mips_L1ICacheSize; 221 extern u_int mips_L1DCacheLSize; 222 extern u_int mips_L1ICacheLSize; 223 extern int mips_L2CachePresent; 224 extern u_int mips_L2CacheLSize; 225 extern u_int mips_CacheAliasMask; 226 227 #ifdef MIPS3 228 extern int mips3_L1TwoWayCache; 229 extern int mips3_cacheflush_bug; 230 #endif /* MIPS3 */ 231 232 /* 233 * trapframe argument passed to trap() 234 */ 235 struct trapframe { 236 mips_reg_t tf_regs[17]; 237 mips_reg_t tf_ra; 238 mips_reg_t tf_sr; 239 mips_reg_t tf_mullo; 240 mips_reg_t tf_mulhi; 241 mips_reg_t tf_epc; /* may be changed by trap() call */ 242 }; 243 244 /* 245 * Stack frame for kernel traps. four args passed in registers. 246 * A trapframe is pointed to by the 5th arg, and a dummy sixth argument 247 * is used to avoid alignment problems 248 */ 249 250 struct kernframe { 251 register_t cf_args[4 + 1]; 252 register_t cf_pad; /* (for 8 word alignment) */ 253 register_t cf_sp; 254 register_t cf_ra; 255 struct trapframe cf_frame; 256 }; 257 258 #endif 259 260 #endif /* _MIPS_LOCORE_H */ 261
Indexes created Mon Sep 29 21:09:56 GMT 2025