locore.h revision 1.24
1 /* $NetBSD: locore.h,v 1.24 2000/01/28 15:08:36 takemura Exp $ */ 2 3 /* 4 * Copyright 1996 The Board of Trustees of The Leland Stanford 5 * Junior University. All Rights Reserved. 6 * 7 * Permission to use, copy, modify, and distribute this 8 * software and its documentation for any purpose and without 9 * fee is hereby granted, provided that the above copyright 10 * notice appear in all copies. Stanford University 11 * makes no representations about the suitability of this 12 * software for any purpose. It is provided "as is" without 13 * express or implied warranty. 14 */ 15 16 /* 17 * Jump table for MIPS cpu locore functions that are implemented 18 * differently on different generations, or instruction-level 19 * archtecture (ISA) level, the Mips family. 20 * The following functions must be provided for each mips ISA level: 21 * 22 * 23 * MachFlushCache 24 * MachFlushDCache 25 * MachFlushICache 26 * MachForceCacheUpdate 27 * MachSetPID 28 * MachTLBFlush 29 * MachTLBFlushAddr 30 * MachTLBUpdate 31 * wbflush 32 * proc_trampoline() 33 * cpu_switch_resume() 34 * 35 * We currently provide support for: 36 * 37 * r2000 and r3000 (mips ISA-I) 38 * r4000 and r4400 in 32-bit mode (mips ISA-III?) 39 */ 40 41 #ifndef _MIPS_LOCORE_H 42 #define _MIPS_LOCORE_H 43 44 #ifndef _LKM 45 #include "opt_mips_cache.h" 46 #endif 47 48 /* 49 * locore service routine for exception vectors. Used outside locore 50 * only to print them by name in stack tracebacks 51 */ 52 53 extern u_int32_t mips_read_causereg __P((void)); 54 extern u_int32_t mips_read_statusreg __P((void)); 55 extern void mips_idle __P((void)); 56 57 extern void mips1_ConfigCache __P((void)); 58 extern void mips1_FlushCache __P((void)); 59 extern void mips1_FlushDCache __P((vaddr_t addr, vsize_t len)); 60 extern void mips1_FlushICache __P((vaddr_t addr, vsize_t len)); 61 extern void mips1_ForceCacheUpdate __P((void)); 62 extern void mips1_SetPID __P((int pid)); 63 extern void mips1_clean_tlb __P((void)); 64 extern void mips1_TLBFlush __P((int numtlb)); 65 extern void mips1_TLBFlushAddr __P( /* XXX Really pte highpart ? */ 66 (vaddr_t addr)); 67 extern int mips1_TLBUpdate __P((u_int, /*pt_entry_t*/ u_int)); 68 extern void mips1_TLBWriteIndexed __P((u_int index, u_int high, 69 u_int low)); 70 extern void mips1_wbflush __P((void)); 71 extern void mips1_proc_trampoline __P((void)); 72 extern void mips1_cpu_switch_resume __P((void)); 73 74 extern void mips3_ConfigCache __P((void)); 75 extern void mips3_FlushCache __P((void)); 76 extern void mips3_FlushDCache __P((vaddr_t addr, vaddr_t len)); 77 #ifdef MIPS3_L2CACHE_ABSENT 78 extern void mips52xx_FlushDCache __P((vaddr_t addr, vaddr_t len)); 79 #endif 80 extern void mips3_FlushICache __P((vaddr_t addr, vaddr_t len)); 81 extern void mips3_ForceCacheUpdate __P((void)); 82 extern void mips3_HitFlushDCache __P((vaddr_t, int)); 83 extern void mips3_SetPID __P((int pid)); 84 extern void mips3_TLBFlush __P((int numtlb)); 85 extern void mips3_TLBFlushAddr __P( /* XXX Really pte highpart ? */ 86 (vaddr_t addr)); 87 extern int mips3_TLBUpdate __P((u_int, /*pt_entry_t*/ u_int)); 88 struct tlb; 89 extern void mips3_TLBRead __P((int, struct tlb *)); 90 #if 0 91 extern void mips3_TLBWriteIndexedVPS __P((u_int index, struct tlb *tlb)); 92 extern void mips3_TLBWriteIndexed __P((u_int index, u_int high, 93 u_int lo0, u_int lo1)); 94 #endif 95 extern void mips3_wbflush __P((void)); 96 extern void mips3_proc_trampoline __P((void)); 97 extern void mips3_cpu_switch_resume __P((void)); 98 99 extern void mips3_SetWIRED __P((int)); 100 101 extern u_int32_t mips3_cycle_count __P((void)); 102 extern u_int32_t mips3_write_count __P((u_int32_t)); 103 extern u_int32_t mips3_read_compare __P((void)); 104 extern u_int32_t mips3_read_config __P((void)); 105 extern void mips3_write_compare __P((u_int32_t)); 106 extern void mips3_write_xcontext_upper __P((u_int32_t)); 107 108 /* 109 * A vector with an entry for each mips-ISA-level dependent 110 * locore function, and macros which jump through it. 111 * XXX the macro names are chosen to be compatible with the old 112 * Sprite coding-convention names used in 4.4bsd/pmax. 113 */ 114 typedef struct { 115 void (*flushCache) __P((void)); 116 void (*flushDCache) __P((vaddr_t addr, vsize_t len)); 117 void (*flushICache) __P((vaddr_t addr, vsize_t len)); 118 void (*forceCacheUpdate) __P((void)); 119 void (*setTLBpid) __P((int pid)); 120 void (*tlbFlush) __P((int numtlb)); 121 void (*tlbFlushAddr) __P((vaddr_t)); /* XXX Really pte highpart ? */ 122 int (*tlbUpdate) __P((u_int highreg, u_int lowreg)); 123 void (*wbflush) __P((void)); 124 void (*proc_trampoline) __P((void)); 125 void (*cpu_switch_resume) __P((void)); 126 void (*cpu_idle) __P((void)); 127 } mips_locore_jumpvec_t; 128 129 /* Override writebuffer-drain method. */ 130 void mips_set_wbflush __P((void (*) __P((void)) )); 131 132 133 /* stacktrace() -- print a stack backtrace to the console */ 134 void stacktrace __P((void)); 135 /* logstacktrace() -- log a stack traceback to msgbuf */ 136 void logstacktrace __P((void)); 137 138 /* 139 * The "active" locore-fuction vector, and 140 141 */ 142 extern mips_locore_jumpvec_t mips_locore_jumpvec; 143 extern mips_locore_jumpvec_t r2000_locore_vec; 144 extern mips_locore_jumpvec_t r4000_locore_vec; 145 146 #if defined(MIPS3) && !defined (MIPS1) 147 #define MachFlushCache mips3_FlushCache 148 #if defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_4100) 149 #define MachFlushDCache mips3_FlushDCache /* VR4100 */ 150 #elif defined(MIPS3_L2CACHE_ABSENT) && !defined(MIPS3_L2CACHE_PRESENT) 151 #define MachFlushDCache mips52xx_FlushDCache /* RM5200 */ 152 #elif !defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_L2CACHE_PRESENT) 153 #define MachFlushDCache mips3_FlushDCache 154 #else 155 #define MachFlushDCache (*(mips_locore_jumpvec.flushDCache)) 156 #endif 157 #define MachFlushICache mips3_FlushICache 158 #define MachForceCacheUpdate mips3_ForceCacheUpdate 159 #define MachSetPID mips3_SetPID 160 #define MachTLBFlush() mips3_TLBFlush(mips_num_tlb_entries) 161 #define MachTLBFlushAddr mips3_TLBFlushAddr 162 #define MachTLBUpdate mips3_TLBUpdate 163 #define wbflush() mips3_wbflush() 164 #define proc_trampoline mips3_proc_trampoline 165 #endif 166 167 #if !defined(MIPS3) && defined (MIPS1) 168 #define MachFlushCache mips1_FlushCache 169 #define MachFlushDCache mips1_FlushDCache 170 #define MachFlushICache mips1_FlushICache 171 #define MachForceCacheUpdate mips1_ForceCacheUpdate 172 #define MachSetPID mips1_SetPID 173 #define MachTLBFlush() mips1_TLBFlush(MIPS1_TLB_NUM_TLB_ENTRIES) 174 #define MachTLBFlushAddr mips1_TLBFlushAddr 175 #define MachTLBUpdate mips1_TLBUpdate 176 #define wbflush() mips1_wbflush() 177 #define proc_trampoline mips1_proc_trampoline 178 #endif 179 180 181 182 #if defined(MIPS3) && defined (MIPS1) 183 #define MachFlushCache (*(mips_locore_jumpvec.flushCache)) 184 #define MachFlushDCache (*(mips_locore_jumpvec.flushDCache)) 185 #define MachFlushICache (*(mips_locore_jumpvec.flushICache)) 186 #define MachForceCacheUpdate (*(mips_locore_jumpvec.forceCacheUpdate)) 187 #define MachSetPID (*(mips_locore_jumpvec.setTLBpid)) 188 #define MachTLBFlush() (*(mips_locore_jumpvec.tlbFlush))(mips_num_tlb_entries) 189 #define MachTLBFlushAddr (*(mips_locore_jumpvec.tlbFlushAddr)) 190 #define MachTLBUpdate (*(mips_locore_jumpvec.tlbUpdate)) 191 #define wbflush() (*(mips_locore_jumpvec.wbflush))() 192 #define proc_trampoline (mips_locore_jumpvec.proc_trampoline) 193 #endif 194 195 /* cpu_switch_resume is called inside locore.S */ 196 197 /* 198 * CPU identification, from PRID register. 199 */ 200 union cpuprid { 201 int cpuprid; 202 struct { 203 #if BYTE_ORDER == BIG_ENDIAN 204 u_int pad1:16; /* reserved */ 205 u_int cp_imp:8; /* implementation identifier */ 206 u_int cp_majrev:4; /* major revision identifier */ 207 u_int cp_minrev:4; /* minor revision identifier */ 208 #else 209 u_int cp_minrev:4; /* minor revision identifier */ 210 u_int cp_majrev:4; /* major revision identifier */ 211 u_int cp_imp:8; /* implementation identifier */ 212 u_int pad1:16; /* reserved */ 213 #endif 214 } cpu; 215 }; 216 217 218 #ifdef _KERNEL 219 220 /* 221 * Global variables used to communicate CPU type, and parameters 222 * such as cache size, from locore to higher-level code (e.g., pmap). 223 */ 224 extern union cpuprid cpu_id; 225 extern union cpuprid fpu_id; 226 extern int cpu_arch; 227 extern int mips_num_tlb_entries; 228 extern u_int mips_L1DCacheSize; 229 extern u_int mips_L1ICacheSize; 230 extern u_int mips_L1DCacheLSize; 231 extern u_int mips_L1ICacheLSize; 232 extern int mips_L2CachePresent; 233 extern u_int mips_L2CacheLSize; 234 extern u_int mips_CacheAliasMask; 235 236 #ifdef MIPS3 237 extern int mips3_L1TwoWayCache; 238 extern int mips3_cacheflush_bug; 239 #endif /* MIPS3 */ 240 241 /* 242 * trapframe argument passed to trap() 243 */ 244 struct trapframe { 245 mips_reg_t tf_regs[17]; 246 mips_reg_t tf_ra; 247 mips_reg_t tf_sr; 248 mips_reg_t tf_mullo; 249 mips_reg_t tf_mulhi; 250 mips_reg_t tf_epc; /* may be changed by trap() call */ 251 }; 252 253 /* 254 * Stack frame for kernel traps. four args passed in registers. 255 * A trapframe is pointed to by the 5th arg, and a dummy sixth argument 256 * is used to avoid alignment problems 257 */ 258 259 struct kernframe { 260 register_t cf_args[4 + 1]; 261 register_t cf_pad; /* (for 8 word alignment) */ 262 register_t cf_sp; 263 register_t cf_ra; 264 struct trapframe cf_frame; 265 }; 266 267 #endif 268 269 #endif /* _MIPS_LOCORE_H */ 270
Indexes created Tue Sep 30 11:09:46 GMT 2025