locore.h revision 1.26
1 /* $NetBSD: locore.h,v 1.26 2000/03/23 14:49:29 soren Exp $ */ 2 3 /* 4 * Copyright 1996 The Board of Trustees of The Leland Stanford 5 * Junior University. All Rights Reserved. 6 * 7 * Permission to use, copy, modify, and distribute this 8 * software and its documentation for any purpose and without 9 * fee is hereby granted, provided that the above copyright 10 * notice appear in all copies. Stanford University 11 * makes no representations about the suitability of this 12 * software for any purpose. It is provided "as is" without 13 * express or implied warranty. 14 */ 15 16 /* 17 * Jump table for MIPS cpu locore functions that are implemented 18 * differently on different generations, or instruction-level 19 * archtecture (ISA) level, the Mips family. 20 * The following functions must be provided for each mips ISA level: 21 * 22 * 23 * MachFlushCache 24 * MachFlushDCache 25 * MachFlushICache 26 * MachForceCacheUpdate 27 * MachSetPID 28 * MachTLBFlush 29 * MachTLBFlushAddr 30 * MachTLBUpdate 31 * wbflush 32 * proc_trampoline() 33 * cpu_switch_resume() 34 * 35 * We currently provide support for: 36 * 37 * r2000 and r3000 (mips ISA-I) 38 * r4000 and r4400 in 32-bit mode (mips ISA-III?) 39 */ 40 41 #ifndef _MIPS_LOCORE_H 42 #define _MIPS_LOCORE_H 43 44 #ifndef _LKM 45 #include "opt_mips_cache.h" 46 #endif 47 48 /* 49 * locore service routine for exception vectors. Used outside locore 50 * only to print them by name in stack tracebacks 51 */ 52 53 extern u_int32_t mips_read_causereg __P((void)); 54 extern u_int32_t mips_read_statusreg __P((void)); 55 extern void mips_idle __P((void)); 56 57 extern void mips1_ConfigCache __P((void)); 58 extern void mips1_FlushCache __P((void)); 59 extern void mips1_FlushDCache __P((vaddr_t addr, vsize_t len)); 60 extern void mips1_FlushICache __P((vaddr_t addr, vsize_t len)); 61 extern void mips1_ForceCacheUpdate __P((void)); 62 extern void mips1_SetPID __P((int pid)); 63 extern void mips1_clean_tlb __P((void)); 64 extern void mips1_TLBFlush __P((int numtlb)); 65 extern void mips1_TLBFlushAddr __P( /* XXX Really pte highpart ? */ 66 (vaddr_t addr)); 67 extern int mips1_TLBUpdate __P((u_int, /*pt_entry_t*/ u_int)); 68 extern void mips1_TLBWriteIndexed __P((u_int index, u_int high, 69 u_int low)); 70 extern void mips1_wbflush __P((void)); 71 extern void mips1_proc_trampoline __P((void)); 72 extern void mips1_cpu_switch_resume __P((void)); 73 74 extern void mips3_ConfigCache __P((void)); 75 extern void mips3_FlushCache __P((void)); 76 extern void mips3_FlushDCache __P((vaddr_t addr, vaddr_t len)); 77 extern void mips3_FlushICache __P((vaddr_t addr, vaddr_t len)); 78 extern void mips3_ForceCacheUpdate __P((void)); 79 extern void mips3_HitFlushDCache __P((vaddr_t, int)); 80 extern void mips3_SetPID __P((int pid)); 81 extern void mips3_TLBFlush __P((int numtlb)); 82 extern void mips3_TLBFlushAddr __P( /* XXX Really pte highpart ? */ 83 (vaddr_t addr)); 84 extern int mips3_TLBUpdate __P((u_int, /*pt_entry_t*/ u_int)); 85 struct tlb; 86 extern void mips3_TLBRead __P((int, struct tlb *)); 87 #if 0 88 extern void mips3_TLBWriteIndexedVPS __P((u_int index, struct tlb *tlb)); 89 extern void mips3_TLBWriteIndexed __P((u_int index, u_int high, 90 u_int lo0, u_int lo1)); 91 #endif 92 extern void mips3_wbflush __P((void)); 93 extern void mips3_proc_trampoline __P((void)); 94 extern void mips3_cpu_switch_resume __P((void)); 95 96 extern void mips3_SetWIRED __P((int)); 97 98 extern void mips5200_FlushCache __P((void)); 99 extern void mips5200_FlushDCache __P((vaddr_t addr, vaddr_t len)); 100 extern void mips5200_HitFlushDCache __P((vaddr_t, int)); 101 extern void mips5200_FlushICache __P((vaddr_t addr, vaddr_t len)); 102 103 extern u_int32_t mips3_cycle_count __P((void)); 104 extern u_int32_t mips3_write_count __P((u_int32_t)); 105 extern u_int32_t mips3_read_compare __P((void)); 106 extern u_int32_t mips3_read_config __P((void)); 107 extern void mips3_write_compare __P((u_int32_t)); 108 extern void mips3_write_xcontext_upper __P((u_int32_t)); 109 extern void mips3_clearBEV __P((void)); 110 111 /* 112 * A vector with an entry for each mips-ISA-level dependent 113 * locore function, and macros which jump through it. 114 * XXX the macro names are chosen to be compatible with the old 115 * Sprite coding-convention names used in 4.4bsd/pmax. 116 */ 117 typedef struct { 118 void (*flushCache) __P((void)); 119 void (*flushDCache) __P((vaddr_t addr, vsize_t len)); 120 void (*flushICache) __P((vaddr_t addr, vsize_t len)); 121 void (*forceCacheUpdate) __P((void)); 122 void (*setTLBpid) __P((int pid)); 123 void (*tlbFlush) __P((int numtlb)); 124 void (*tlbFlushAddr) __P((vaddr_t)); /* XXX Really pte highpart ? */ 125 int (*tlbUpdate) __P((u_int highreg, u_int lowreg)); 126 void (*wbflush) __P((void)); 127 void (*proc_trampoline) __P((void)); 128 void (*cpu_switch_resume) __P((void)); 129 void (*cpu_idle) __P((void)); 130 } mips_locore_jumpvec_t; 131 132 /* Override writebuffer-drain method. */ 133 void mips_set_wbflush __P((void (*) __P((void)) )); 134 135 136 /* stacktrace() -- print a stack backtrace to the console */ 137 void stacktrace __P((void)); 138 /* logstacktrace() -- log a stack traceback to msgbuf */ 139 void logstacktrace __P((void)); 140 141 /* 142 * The "active" locore-fuction vector, and 143 144 */ 145 extern mips_locore_jumpvec_t mips_locore_jumpvec; 146 extern mips_locore_jumpvec_t r2000_locore_vec; 147 extern mips_locore_jumpvec_t r4000_locore_vec; 148 149 #if defined(MIPS3) && !defined (MIPS1) 150 #if defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_5200) 151 #define MachFlushCache mips5200_FlushCache 152 #define MachFlushDCache mips5200_FlushDCache 153 #define MachHitFlushDCache mips5200_HitFlushDCache 154 #define MachFlushICache mips5200_FlushICache 155 #else 156 #define MachFlushCache mips3_FlushCache 157 #if defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_4100) 158 #define MachFlushDCache mips3_FlushDCache /* VR4100 */ 159 #elif !defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_L2CACHE_PRESENT) 160 #define MachFlushDCache mips3_FlushDCache 161 #else 162 #define MachFlushDCache (*(mips_locore_jumpvec.flushDCache)) 163 #endif 164 #define MachHitFlushDCache mips3_HitFlushDCache 165 #define MachFlushICache mips3_FlushICache 166 #endif 167 #define MachForceCacheUpdate mips3_ForceCacheUpdate 168 #define MachSetPID mips3_SetPID 169 #define MachTLBFlush() mips3_TLBFlush(mips_num_tlb_entries) 170 #define MachTLBFlushAddr mips3_TLBFlushAddr 171 #define MachTLBUpdate mips3_TLBUpdate 172 #define wbflush() mips3_wbflush() 173 #define proc_trampoline mips3_proc_trampoline 174 #endif 175 176 #if !defined(MIPS3) && defined (MIPS1) 177 #define MachFlushCache mips1_FlushCache 178 #define MachFlushDCache mips1_FlushDCache 179 #define MachFlushICache mips1_FlushICache 180 #define MachForceCacheUpdate mips1_ForceCacheUpdate 181 #define MachSetPID mips1_SetPID 182 #define MachTLBFlush() mips1_TLBFlush(MIPS1_TLB_NUM_TLB_ENTRIES) 183 #define MachTLBFlushAddr mips1_TLBFlushAddr 184 #define MachTLBUpdate mips1_TLBUpdate 185 #define wbflush() mips1_wbflush() 186 #define proc_trampoline mips1_proc_trampoline 187 #endif 188 189 190 191 #if defined(MIPS3) && defined (MIPS1) 192 #define MachFlushCache (*(mips_locore_jumpvec.flushCache)) 193 #define MachFlushDCache (*(mips_locore_jumpvec.flushDCache)) 194 #define MachFlushICache (*(mips_locore_jumpvec.flushICache)) 195 #define MachForceCacheUpdate (*(mips_locore_jumpvec.forceCacheUpdate)) 196 #define MachSetPID (*(mips_locore_jumpvec.setTLBpid)) 197 #define MachTLBFlush() (*(mips_locore_jumpvec.tlbFlush))(mips_num_tlb_entries) 198 #define MachTLBFlushAddr (*(mips_locore_jumpvec.tlbFlushAddr)) 199 #define MachTLBUpdate (*(mips_locore_jumpvec.tlbUpdate)) 200 #define wbflush() (*(mips_locore_jumpvec.wbflush))() 201 #define proc_trampoline (mips_locore_jumpvec.proc_trampoline) 202 #define MachHitFlushDCache mips3_HitFlushDCache 203 #endif 204 205 /* cpu_switch_resume is called inside locore.S */ 206 207 /* 208 * CPU identification, from PRID register. 209 */ 210 union cpuprid { 211 int cpuprid; 212 struct { 213 #if BYTE_ORDER == BIG_ENDIAN 214 u_int pad1:16; /* reserved */ 215 u_int cp_imp:8; /* implementation identifier */ 216 u_int cp_majrev:4; /* major revision identifier */ 217 u_int cp_minrev:4; /* minor revision identifier */ 218 #else 219 u_int cp_minrev:4; /* minor revision identifier */ 220 u_int cp_majrev:4; /* major revision identifier */ 221 u_int cp_imp:8; /* implementation identifier */ 222 u_int pad1:16; /* reserved */ 223 #endif 224 } cpu; 225 }; 226 227 228 #ifdef _KERNEL 229 230 /* 231 * Global variables used to communicate CPU type, and parameters 232 * such as cache size, from locore to higher-level code (e.g., pmap). 233 */ 234 extern union cpuprid cpu_id; 235 extern union cpuprid fpu_id; 236 extern int cpu_arch; 237 extern int mips_num_tlb_entries; 238 extern u_int mips_L1DCacheSize; 239 extern u_int mips_L1ICacheSize; 240 extern u_int mips_L1DCacheLSize; 241 extern u_int mips_L1ICacheLSize; 242 extern int mips_L2CachePresent; 243 extern u_int mips_L2CacheLSize; 244 extern u_int mips_CacheAliasMask; 245 246 #ifdef MIPS3 247 extern int mips3_L1TwoWayCache; 248 extern int mips3_cacheflush_bug; 249 #endif /* MIPS3 */ 250 251 /* 252 * trapframe argument passed to trap() 253 */ 254 struct trapframe { 255 mips_reg_t tf_regs[17]; 256 mips_reg_t tf_ra; 257 mips_reg_t tf_sr; 258 mips_reg_t tf_mullo; 259 mips_reg_t tf_mulhi; 260 mips_reg_t tf_epc; /* may be changed by trap() call */ 261 }; 262 263 /* 264 * Stack frame for kernel traps. four args passed in registers. 265 * A trapframe is pointed to by the 5th arg, and a dummy sixth argument 266 * is used to avoid alignment problems 267 */ 268 269 struct kernframe { 270 register_t cf_args[4 + 1]; 271 register_t cf_pad; /* (for 8 word alignment) */ 272 register_t cf_sp; 273 register_t cf_ra; 274 struct trapframe cf_frame; 275 }; 276 277 #endif 278 279 #endif /* _MIPS_LOCORE_H */ 280
Indexes created Mon Sep 29 21:09:56 GMT 2025