locore.h revision 1.27
1 /* $NetBSD: locore.h,v 1.27 2000/03/27 05:23:42 nisimura Exp $ */ 2 3 /* 4 * Copyright 1996 The Board of Trustees of The Leland Stanford 5 * Junior University. All Rights Reserved. 6 * 7 * Permission to use, copy, modify, and distribute this 8 * software and its documentation for any purpose and without 9 * fee is hereby granted, provided that the above copyright 10 * notice appear in all copies. Stanford University 11 * makes no representations about the suitability of this 12 * software for any purpose. It is provided "as is" without 13 * express or implied warranty. 14 */ 15 16 /* 17 * Jump table for MIPS cpu locore functions that are implemented 18 * differently on different generations, or instruction-level 19 * archtecture (ISA) level, the Mips family. 20 * The following functions must be provided for each mips ISA level: 21 * 22 * 23 * MachFlushCache 24 * MachFlushDCache 25 * MachFlushICache 26 * MachForceCacheUpdate 27 * MachSetPID 28 * MachTLBFlush 29 * MachTLBFlushAddr 30 * MachTLBUpdate 31 * wbflush 32 * proc_trampoline() 33 * cpu_switch_resume() 34 * 35 * We currently provide support for: 36 * 37 * r2000 and r3000 (mips ISA-I) 38 * r4000 and r4400 in 32-bit mode (mips ISA-III?) 39 */ 40 41 #ifndef _MIPS_LOCORE_H 42 #define _MIPS_LOCORE_H 43 44 #ifndef _LKM 45 #include "opt_mips_cache.h" 46 #endif 47 48 /* 49 * locore service routine for exception vectors. Used outside locore 50 * only to print them by name in stack tracebacks 51 */ 52 53 extern u_int32_t mips_read_causereg __P((void)); 54 extern u_int32_t mips_read_statusreg __P((void)); 55 extern void mips_idle __P((void)); 56 57 extern void mips1_ConfigCache __P((void)); 58 extern void mips1_FlushCache __P((void)); 59 extern void mips1_FlushDCache __P((vaddr_t addr, vsize_t len)); 60 extern void mips1_FlushICache __P((vaddr_t addr, vsize_t len)); 61 extern void mips1_ForceCacheUpdate __P((void)); 62 extern void mips1_SetPID __P((int pid)); 63 64 extern void mips1_TBIA __P((int)); 65 extern void mips1_TBIAP __P((int)); 66 extern void mips1_TBIS __P((vaddr_t)); 67 68 extern int mips1_TLBUpdate __P((u_int, /*pt_entry_t*/ u_int)); 69 extern void mips1_TLBWriteIndexed __P((u_int index, u_int high, 70 u_int low)); 71 extern void mips1_wbflush __P((void)); 72 extern void mips1_proc_trampoline __P((void)); 73 extern void mips1_cpu_switch_resume __P((void)); 74 75 extern void mips3_ConfigCache __P((void)); 76 extern void mips3_FlushCache __P((void)); 77 extern void mips3_FlushDCache __P((vaddr_t addr, vaddr_t len)); 78 extern void mips3_FlushICache __P((vaddr_t addr, vaddr_t len)); 79 extern void mips3_ForceCacheUpdate __P((void)); 80 extern void mips3_HitFlushDCache __P((vaddr_t, int)); 81 extern void mips3_SetPID __P((int pid)); 82 extern void mips3_TLBFlush __P((int numtlb)); 83 extern void mips3_TLBFlushAddr __P( /* XXX Really pte highpart ? */ 84 (vaddr_t addr)); 85 extern int mips3_TLBUpdate __P((u_int, /*pt_entry_t*/ u_int)); 86 struct tlb; 87 extern void mips3_TLBRead __P((int, struct tlb *)); 88 #if 0 89 extern void mips3_TLBWriteIndexedVPS __P((u_int index, struct tlb *tlb)); 90 extern void mips3_TLBWriteIndexed __P((u_int index, u_int high, 91 u_int lo0, u_int lo1)); 92 #endif 93 extern void mips3_wbflush __P((void)); 94 extern void mips3_proc_trampoline __P((void)); 95 extern void mips3_cpu_switch_resume __P((void)); 96 97 extern void mips3_SetWIRED __P((int)); 98 99 extern void mips5200_FlushCache __P((void)); 100 extern void mips5200_FlushDCache __P((vaddr_t addr, vaddr_t len)); 101 extern void mips5200_HitFlushDCache __P((vaddr_t, int)); 102 extern void mips5200_FlushICache __P((vaddr_t addr, vaddr_t len)); 103 104 extern u_int32_t mips3_cycle_count __P((void)); 105 extern u_int32_t mips3_write_count __P((u_int32_t)); 106 extern u_int32_t mips3_read_compare __P((void)); 107 extern u_int32_t mips3_read_config __P((void)); 108 extern void mips3_write_compare __P((u_int32_t)); 109 extern void mips3_write_xcontext_upper __P((u_int32_t)); 110 extern void mips3_clearBEV __P((void)); 111 112 /* 113 * A vector with an entry for each mips-ISA-level dependent 114 * locore function, and macros which jump through it. 115 * XXX the macro names are chosen to be compatible with the old 116 * Sprite coding-convention names used in 4.4bsd/pmax. 117 */ 118 typedef struct { 119 void (*flushCache) __P((void)); 120 void (*flushDCache) __P((vaddr_t addr, vsize_t len)); 121 void (*flushICache) __P((vaddr_t addr, vsize_t len)); 122 void (*forceCacheUpdate) __P((void)); 123 void (*setTLBpid) __P((int pid)); 124 void (*tlbFlush) __P((int numtlb)); 125 void (*tlbFlushAddr) __P((vaddr_t)); /* XXX Really pte highpart ? */ 126 int (*tlbUpdate) __P((u_int highreg, u_int lowreg)); 127 void (*wbflush) __P((void)); 128 void (*proc_trampoline) __P((void)); 129 void (*cpu_switch_resume) __P((void)); 130 void (*cpu_idle) __P((void)); 131 } mips_locore_jumpvec_t; 132 133 /* Override writebuffer-drain method. */ 134 void mips_set_wbflush __P((void (*) __P((void)) )); 135 136 137 /* stacktrace() -- print a stack backtrace to the console */ 138 void stacktrace __P((void)); 139 /* logstacktrace() -- log a stack traceback to msgbuf */ 140 void logstacktrace __P((void)); 141 142 /* 143 * The "active" locore-fuction vector, and 144 145 */ 146 extern mips_locore_jumpvec_t mips_locore_jumpvec; 147 extern mips_locore_jumpvec_t r2000_locore_vec; 148 extern mips_locore_jumpvec_t r4000_locore_vec; 149 150 #if defined(MIPS3) && !defined (MIPS1) 151 #if defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_5200) 152 #define MachFlushCache mips5200_FlushCache 153 #define MachFlushDCache mips5200_FlushDCache 154 #define MachHitFlushDCache mips5200_HitFlushDCache 155 #define MachFlushICache mips5200_FlushICache 156 #else 157 #define MachFlushCache mips3_FlushCache 158 #if defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_4100) 159 #define MachFlushDCache mips3_FlushDCache /* VR4100 */ 160 #elif !defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_L2CACHE_PRESENT) 161 #define MachFlushDCache mips3_FlushDCache 162 #else 163 #define MachFlushDCache (*(mips_locore_jumpvec.flushDCache)) 164 #endif 165 #define MachHitFlushDCache mips3_HitFlushDCache 166 #define MachFlushICache mips3_FlushICache 167 #endif 168 #define MachForceCacheUpdate mips3_ForceCacheUpdate 169 #define MachSetPID mips3_SetPID 170 #define MachTLBFlush() mips3_TLBFlush(mips_num_tlb_entries) 171 #define MachTLBFlushAddr mips3_TLBFlushAddr 172 #define MachTLBUpdate mips3_TLBUpdate 173 #define wbflush() mips3_wbflush() 174 #define proc_trampoline mips3_proc_trampoline 175 #endif 176 177 #if !defined(MIPS3) && defined (MIPS1) 178 #define MachFlushCache mips1_FlushCache 179 #define MachFlushDCache mips1_FlushDCache 180 #define MachFlushICache mips1_FlushICache 181 #define MachForceCacheUpdate mips1_ForceCacheUpdate 182 #define MachSetPID mips1_SetPID 183 #define MachTLBFlush() mips1_TBIAP(MIPS1_TLB_NUM_TLB_ENTRIES) 184 #define MachTLBFlushAddr mips1_TBIS 185 #define MachTLBUpdate mips1_TLBUpdate 186 #define wbflush() mips1_wbflush() 187 #define proc_trampoline mips1_proc_trampoline 188 #endif 189 190 191 192 #if defined(MIPS3) && defined (MIPS1) 193 #define MachFlushCache (*(mips_locore_jumpvec.flushCache)) 194 #define MachFlushDCache (*(mips_locore_jumpvec.flushDCache)) 195 #define MachFlushICache (*(mips_locore_jumpvec.flushICache)) 196 #define MachForceCacheUpdate (*(mips_locore_jumpvec.forceCacheUpdate)) 197 #define MachSetPID (*(mips_locore_jumpvec.setTLBpid)) 198 #define MachTLBFlush() (*(mips_locore_jumpvec.tlbFlush))(mips_num_tlb_entries) 199 #define MachTLBFlushAddr (*(mips_locore_jumpvec.tlbFlushAddr)) 200 #define MachTLBUpdate (*(mips_locore_jumpvec.tlbUpdate)) 201 #define wbflush() (*(mips_locore_jumpvec.wbflush))() 202 #define proc_trampoline (mips_locore_jumpvec.proc_trampoline) 203 #define MachHitFlushDCache mips3_HitFlushDCache 204 #endif 205 206 /* cpu_switch_resume is called inside locore.S */ 207 208 /* 209 * CPU identification, from PRID register. 210 */ 211 union cpuprid { 212 int cpuprid; 213 struct { 214 #if BYTE_ORDER == BIG_ENDIAN 215 u_int pad1:16; /* reserved */ 216 u_int cp_imp:8; /* implementation identifier */ 217 u_int cp_majrev:4; /* major revision identifier */ 218 u_int cp_minrev:4; /* minor revision identifier */ 219 #else 220 u_int cp_minrev:4; /* minor revision identifier */ 221 u_int cp_majrev:4; /* major revision identifier */ 222 u_int cp_imp:8; /* implementation identifier */ 223 u_int pad1:16; /* reserved */ 224 #endif 225 } cpu; 226 }; 227 228 229 #ifdef _KERNEL 230 231 /* 232 * Global variables used to communicate CPU type, and parameters 233 * such as cache size, from locore to higher-level code (e.g., pmap). 234 */ 235 extern union cpuprid cpu_id; 236 extern union cpuprid fpu_id; 237 extern int cpu_arch; 238 extern int mips_num_tlb_entries; 239 extern u_int mips_L1DCacheSize; 240 extern u_int mips_L1ICacheSize; 241 extern u_int mips_L1DCacheLSize; 242 extern u_int mips_L1ICacheLSize; 243 extern int mips_L2CachePresent; 244 extern u_int mips_L2CacheLSize; 245 extern u_int mips_CacheAliasMask; 246 247 #ifdef MIPS3 248 extern int mips3_L1TwoWayCache; 249 extern int mips3_cacheflush_bug; 250 #endif /* MIPS3 */ 251 252 /* 253 * trapframe argument passed to trap() 254 */ 255 struct trapframe { 256 mips_reg_t tf_regs[17]; 257 mips_reg_t tf_ra; 258 mips_reg_t tf_sr; 259 mips_reg_t tf_mullo; 260 mips_reg_t tf_mulhi; 261 mips_reg_t tf_epc; /* may be changed by trap() call */ 262 }; 263 264 /* 265 * Stack frame for kernel traps. four args passed in registers. 266 * A trapframe is pointed to by the 5th arg, and a dummy sixth argument 267 * is used to avoid alignment problems 268 */ 269 270 struct kernframe { 271 register_t cf_args[4 + 1]; 272 register_t cf_pad; /* (for 8 word alignment) */ 273 register_t cf_sp; 274 register_t cf_ra; 275 struct trapframe cf_frame; 276 }; 277 278 #endif 279 280 #endif /* _MIPS_LOCORE_H */ 281
Indexes created Mon Sep 29 21:09:56 GMT 2025