locore.h revision 1.30
1 /* $NetBSD: locore.h,v 1.30 2000/04/12 01:05:34 nisimura Exp $ */ 2 3 /* 4 * Copyright 1996 The Board of Trustees of The Leland Stanford 5 * Junior University. All Rights Reserved. 6 * 7 * Permission to use, copy, modify, and distribute this 8 * software and its documentation for any purpose and without 9 * fee is hereby granted, provided that the above copyright 10 * notice appear in all copies. Stanford University 11 * makes no representations about the suitability of this 12 * software for any purpose. It is provided "as is" without 13 * express or implied warranty. 14 */ 15 16 /* 17 * Jump table for MIPS cpu locore functions that are implemented 18 * differently on different generations, or instruction-level 19 * archtecture (ISA) level, the Mips family. 20 * The following functions must be provided for each mips ISA level: 21 * 22 * 23 * MachFlushCache 24 * MachFlushDCache 25 * MachFlushICache 26 * MachForceCacheUpdate 27 * MachSetPID 28 * MachTLBFlush 29 * MachTLBFlushAddr 30 * MachTLBUpdate 31 * wbflush 32 * proc_trampoline() 33 * cpu_switch_resume() 34 * 35 * We currently provide support for: 36 * 37 * r2000 and r3000 (mips ISA-I) 38 * r4000 and r4400 in 32-bit mode (mips ISA-III?) 39 */ 40 41 #ifndef _MIPS_LOCORE_H 42 #define _MIPS_LOCORE_H 43 44 #ifndef _LKM 45 #include "opt_mips_cache.h" 46 #endif 47 48 /* 49 * locore service routine for exception vectors. Used outside locore 50 * only to print them by name in stack tracebacks 51 */ 52 53 u_int32_t mips_read_causereg __P((void)); 54 u_int32_t mips_read_statusreg __P((void)); 55 void mips_idle __P((void)); 56 57 void mips1_ConfigCache __P((void)); 58 void mips1_FlushCache __P((void)); 59 void mips1_FlushDCache __P((vaddr_t addr, vsize_t len)); 60 void mips1_FlushICache __P((vaddr_t addr, vsize_t len)); 61 void mips1_ForceCacheUpdate __P((void)); 62 63 void mips1_SetPID __P((int pid)); 64 void mips1_TBIA __P((int)); 65 void mips1_TBIAP __P((int)); 66 void mips1_TBIS __P((vaddr_t)); 67 int mips1_TLBUpdate __P((u_int, /*pt_entry_t*/ u_int)); 68 69 void mips1_wbflush __P((void)); 70 void mips1_proc_trampoline __P((void)); 71 void mips1_cpu_switch_resume __P((void)); 72 73 void mips3_ConfigCache __P((void)); 74 void mips3_FlushCache __P((void)); 75 void mips3_FlushDCache __P((vaddr_t addr, vaddr_t len)); 76 void mips3_FlushICache __P((vaddr_t addr, vaddr_t len)); 77 void mips3_ForceCacheUpdate __P((void)); 78 void mips3_HitFlushDCache __P((vaddr_t, int)); 79 80 void mips3_SetPID __P((int pid)); 81 void mips3_TBIA __P((int)); 82 void mips3_TBIAP __P((int)); 83 void mips3_TBIS __P((vaddr_t)); 84 int mips3_TLBUpdate __P((u_int, /*pt_entry_t*/ u_int)); 85 struct tlb; 86 void mips3_TLBRead __P((int, struct tlb *)); 87 #if 0 88 void mips3_TLBWriteIndexedVPS __P((u_int index, struct tlb *tlb)); 89 void mips3_TLBWriteIndexed __P((u_int index, u_int high, 90 u_int lo0, u_int lo1)); 91 #endif 92 void mips3_SetWIRED __P((int)); 93 void mips3_wbflush __P((void)); 94 void mips3_proc_trampoline __P((void)); 95 void mips3_cpu_switch_resume __P((void)); 96 97 void mips5200_FlushCache __P((void)); 98 void mips5200_FlushDCache __P((vaddr_t addr, vaddr_t len)); 99 void mips5200_HitFlushDCache __P((vaddr_t, int)); 100 void mips5200_FlushICache __P((vaddr_t addr, vaddr_t len)); 101 102 u_int32_t mips3_cycle_count __P((void)); 103 u_int32_t mips3_write_count __P((u_int32_t)); 104 u_int32_t mips3_read_compare __P((void)); 105 u_int32_t mips3_read_config __P((void)); 106 void mips3_write_compare __P((u_int32_t)); 107 void mips3_write_xcontext_upper __P((u_int32_t)); 108 void mips3_clearBEV __P((void)); 109 110 /* 111 * A vector with an entry for each mips-ISA-level dependent 112 * locore function, and macros which jump through it. 113 * XXX the macro names are chosen to be compatible with the old 114 * Sprite coding-convention names used in 4.4bsd/pmax. 115 */ 116 typedef struct { 117 void (*flushCache) __P((void)); 118 void (*flushDCache) __P((vaddr_t addr, vsize_t len)); 119 void (*flushICache) __P((vaddr_t addr, vsize_t len)); 120 void (*forceCacheUpdate) __P((void)); 121 void (*setTLBpid) __P((int pid)); 122 void (*tlbFlush) __P((int numtlb)); 123 void (*tlbFlushAddr) __P((vaddr_t)); /* XXX Really pte highpart ? */ 124 int (*tlbUpdate) __P((u_int highreg, u_int lowreg)); 125 void (*wbflush) __P((void)); 126 void (*proc_trampoline) __P((void)); 127 void (*cpu_switch_resume) __P((void)); 128 void (*cpu_idle) __P((void)); 129 } mips_locore_jumpvec_t; 130 131 /* Override writebuffer-drain method. */ 132 void mips_set_wbflush __P((void (*) __P((void)) )); 133 134 135 /* stacktrace() -- print a stack backtrace to the console */ 136 void stacktrace __P((void)); 137 /* logstacktrace() -- log a stack traceback to msgbuf */ 138 void logstacktrace __P((void)); 139 140 /* 141 * The "active" locore-fuction vector, and 142 143 */ 144 extern mips_locore_jumpvec_t mips_locore_jumpvec; 145 extern mips_locore_jumpvec_t r2000_locore_vec; 146 extern mips_locore_jumpvec_t r4000_locore_vec; 147 148 #if defined(MIPS3) && !defined (MIPS1) 149 #if defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_5200) 150 #define MachFlushCache mips5200_FlushCache 151 #define MachFlushDCache mips5200_FlushDCache 152 #define MachHitFlushDCache mips5200_HitFlushDCache 153 #define MachFlushICache mips5200_FlushICache 154 #else 155 #define MachFlushCache mips3_FlushCache 156 #if defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_4100) 157 #define MachFlushDCache mips3_FlushDCache /* VR4100 */ 158 #elif !defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_L2CACHE_PRESENT) 159 #define MachFlushDCache mips3_FlushDCache 160 #else 161 #define MachFlushDCache (*(mips_locore_jumpvec.flushDCache)) 162 #endif 163 #define MachHitFlushDCache mips3_HitFlushDCache 164 #define MachFlushICache mips3_FlushICache 165 #endif 166 #define MachForceCacheUpdate mips3_ForceCacheUpdate 167 #define MachSetPID mips3_SetPID 168 #define MIPS_TBIAP() mips3_TBIAP(mips_num_tlb_entries) 169 #define MIPS_TBIS mips3_TBIS 170 #define MachTLBUpdate mips3_TLBUpdate 171 #define wbflush() mips3_wbflush() 172 #define proc_trampoline mips3_proc_trampoline 173 #endif 174 175 #if !defined(MIPS3) && defined (MIPS1) 176 #define MachFlushCache mips1_FlushCache 177 #define MachFlushDCache mips1_FlushDCache 178 #define MachFlushICache mips1_FlushICache 179 #define MachForceCacheUpdate mips1_ForceCacheUpdate 180 #define MachSetPID mips1_SetPID 181 #define MIPS_TBIAP() mips1_TBIAP(mips_num_tlb_entries) 182 #define MIPS_TBIS mips1_TBIS 183 #define MachTLBUpdate mips1_TLBUpdate 184 #define wbflush() mips1_wbflush() 185 #define proc_trampoline mips1_proc_trampoline 186 #endif 187 188 189 190 #if defined(MIPS3) && defined (MIPS1) 191 #define MachFlushCache (*(mips_locore_jumpvec.flushCache)) 192 #define MachFlushDCache (*(mips_locore_jumpvec.flushDCache)) 193 #define MachFlushICache (*(mips_locore_jumpvec.flushICache)) 194 #define MachForceCacheUpdate (*(mips_locore_jumpvec.forceCacheUpdate)) 195 #define MachSetPID (*(mips_locore_jumpvec.setTLBpid)) 196 #define MIPS_TBIAP() (*(mips_locore_jumpvec.tlbFlush))(mips_num_tlb_entries) 197 #define MIPS_TBIS (*(mips_locore_jumpvec.tlbFlushAddr)) 198 #define MachTLBUpdate (*(mips_locore_jumpvec.tlbUpdate)) 199 #define wbflush() (*(mips_locore_jumpvec.wbflush))() 200 #define proc_trampoline (mips_locore_jumpvec.proc_trampoline) 201 #define MachHitFlushDCache mips3_HitFlushDCache 202 #endif 203 204 /* cpu_switch_resume is called inside locore.S */ 205 206 /* 207 * CPU identification, from PRID register. 208 */ 209 union cpuprid { 210 int cpuprid; 211 struct { 212 #if BYTE_ORDER == BIG_ENDIAN 213 u_int pad1:16; /* reserved */ 214 u_int cp_imp:8; /* implementation identifier */ 215 u_int cp_majrev:4; /* major revision identifier */ 216 u_int cp_minrev:4; /* minor revision identifier */ 217 #else 218 u_int cp_minrev:4; /* minor revision identifier */ 219 u_int cp_majrev:4; /* major revision identifier */ 220 u_int cp_imp:8; /* implementation identifier */ 221 u_int pad1:16; /* reserved */ 222 #endif 223 } cpu; 224 }; 225 226 227 #ifdef _KERNEL 228 229 /* 230 * Global variables used to communicate CPU type, and parameters 231 * such as cache size, from locore to higher-level code (e.g., pmap). 232 */ 233 extern union cpuprid cpu_id; 234 extern union cpuprid fpu_id; 235 extern int cpu_arch; 236 extern int mips_num_tlb_entries; 237 extern u_int mips_L1DCacheSize; 238 extern u_int mips_L1ICacheSize; 239 extern u_int mips_L1DCacheLSize; 240 extern u_int mips_L1ICacheLSize; 241 extern int mips_L2CachePresent; 242 extern u_int mips_L2CacheLSize; 243 extern u_int mips_CacheAliasMask; 244 245 #ifdef MIPS3 246 extern int mips3_L1TwoWayCache; 247 extern int mips3_cacheflush_bug; 248 #endif /* MIPS3 */ 249 250 /* 251 * trapframe argument passed to trap() 252 */ 253 struct trapframe { 254 mips_reg_t tf_regs[17]; 255 mips_reg_t tf_ra; 256 mips_reg_t tf_sr; 257 mips_reg_t tf_mullo; 258 mips_reg_t tf_mulhi; 259 mips_reg_t tf_epc; /* may be changed by trap() call */ 260 }; 261 262 /* 263 * Stack frame for kernel traps. four args passed in registers. 264 * A trapframe is pointed to by the 5th arg, and a dummy sixth argument 265 * is used to avoid alignment problems 266 */ 267 268 struct kernframe { 269 register_t cf_args[4 + 1]; 270 register_t cf_pad; /* (for 8 word alignment) */ 271 register_t cf_sp; 272 register_t cf_ra; 273 struct trapframe cf_frame; 274 }; 275 276 #endif 277 278 #endif /* _MIPS_LOCORE_H */ 279
Indexes created Tue Sep 30 20:09:53 GMT 2025