locore.h revision 1.31
1 /* $NetBSD: locore.h,v 1.31 2000/05/10 01:34:13 nisimura Exp $ */ 2 3 /* 4 * Copyright 1996 The Board of Trustees of The Leland Stanford 5 * Junior University. All Rights Reserved. 6 * 7 * Permission to use, copy, modify, and distribute this 8 * software and its documentation for any purpose and without 9 * fee is hereby granted, provided that the above copyright 10 * notice appear in all copies. Stanford University 11 * makes no representations about the suitability of this 12 * software for any purpose. It is provided "as is" without 13 * express or implied warranty. 14 */ 15 16 /* 17 * Jump table for MIPS cpu locore functions that are implemented 18 * differently on different generations, or instruction-level 19 * archtecture (ISA) level, the Mips family. 20 * The following functions must be provided for each mips ISA level: 21 * 22 * 23 * MachFlushCache 24 * MachFlushDCache 25 * MachFlushICache 26 * MachForceCacheUpdate 27 * wbflush 28 * proc_trampoline() 29 * cpu_switch_resume() 30 * 31 * We currently provide support for: 32 * 33 * r2000 and r3000 (mips ISA-I) 34 * r4000 and r4400 in 32-bit mode (mips ISA-III?) 35 */ 36 37 #ifndef _MIPS_LOCORE_H 38 #define _MIPS_LOCORE_H 39 40 #ifndef _LKM 41 #include "opt_mips_cache.h" 42 #endif 43 44 /* 45 * locore service routine for exception vectors. Used outside locore 46 * only to print them by name in stack tracebacks 47 */ 48 49 u_int32_t mips_read_causereg __P((void)); 50 u_int32_t mips_read_statusreg __P((void)); 51 52 void mips1_ConfigCache __P((void)); 53 void mips1_FlushCache __P((void)); 54 void mips1_FlushDCache __P((vaddr_t addr, vsize_t len)); 55 void mips1_FlushICache __P((vaddr_t addr, vsize_t len)); 56 void mips1_ForceCacheUpdate __P((void)); 57 58 void mips1_SetPID __P((int pid)); 59 void mips1_TBIA __P((int)); 60 void mips1_TBIAP __P((int)); 61 void mips1_TBIS __P((vaddr_t)); 62 void mips1_TBRPL __P((vaddr_t, vaddr_t, paddr_t)); 63 int mips1_TLBUpdate __P((u_int, /*pt_entry_t*/ u_int)); 64 65 void mips1_wbflush __P((void)); 66 void mips1_proc_trampoline __P((void)); 67 void mips1_cpu_switch_resume __P((void)); 68 69 void mips3_ConfigCache __P((void)); 70 void mips3_FlushCache __P((void)); 71 void mips3_FlushDCache __P((vaddr_t addr, vaddr_t len)); 72 void mips3_FlushICache __P((vaddr_t addr, vaddr_t len)); 73 void mips3_ForceCacheUpdate __P((void)); 74 void mips3_HitFlushDCache __P((vaddr_t, int)); 75 76 void mips3_SetPID __P((int pid)); 77 void mips3_TBIA __P((int)); 78 void mips3_TBIAP __P((int)); 79 void mips3_TBIS __P((vaddr_t)); 80 void mips3_TBRPL __P((vaddr_t, vaddr_t, paddr_t)); 81 int mips3_TLBUpdate __P((u_int, /*pt_entry_t*/ u_int)); 82 struct tlb; 83 void mips3_TLBRead __P((int, struct tlb *)); 84 #if 0 85 void mips3_TLBWriteIndexedVPS __P((u_int index, struct tlb *tlb)); 86 void mips3_TLBWriteIndexed __P((u_int index, u_int high, 87 u_int lo0, u_int lo1)); 88 #endif 89 void mips3_SetWIRED __P((int)); 90 void mips3_wbflush __P((void)); 91 void mips3_proc_trampoline __P((void)); 92 void mips3_cpu_switch_resume __P((void)); 93 94 void mips5200_FlushCache __P((void)); 95 void mips5200_FlushDCache __P((vaddr_t addr, vaddr_t len)); 96 void mips5200_HitFlushDCache __P((vaddr_t, int)); 97 void mips5200_FlushICache __P((vaddr_t addr, vaddr_t len)); 98 99 u_int32_t mips3_cycle_count __P((void)); 100 u_int32_t mips3_write_count __P((u_int32_t)); 101 u_int32_t mips3_read_compare __P((void)); 102 u_int32_t mips3_read_config __P((void)); 103 void mips3_write_compare __P((u_int32_t)); 104 void mips3_write_xcontext_upper __P((u_int32_t)); 105 void mips3_clearBEV __P((void)); 106 107 /* 108 * A vector with an entry for each mips-ISA-level dependent 109 * locore function, and macros which jump through it. 110 * XXX the macro names are chosen to be compatible with the old 111 * Sprite coding-convention names used in 4.4bsd/pmax. 112 */ 113 typedef struct { 114 void (*flushCache) __P((void)); 115 void (*flushDCache) __P((vaddr_t addr, vsize_t len)); 116 void (*flushICache) __P((vaddr_t addr, vsize_t len)); 117 void (*forceCacheUpdate) __P((void)); 118 void (*setTLBpid) __P((int pid)); 119 void (*TBIAP) __P((int)); 120 void (*TBIS) __P((vaddr_t)); 121 void (*TBRPL) __P((vaddr_t, vaddr_t, paddr_t)); 122 int (*tlbUpdate) __P((u_int highreg, u_int lowreg)); 123 void (*wbflush) __P((void)); 124 } mips_locore_jumpvec_t; 125 126 /* Override writebuffer-drain method. */ 127 void mips_set_wbflush __P((void (*) __P((void)) )); 128 129 130 /* stacktrace() -- print a stack backtrace to the console */ 131 void stacktrace __P((void)); 132 /* logstacktrace() -- log a stack traceback to msgbuf */ 133 void logstacktrace __P((void)); 134 135 /* 136 * The "active" locore-fuction vector, and 137 138 */ 139 extern mips_locore_jumpvec_t mips_locore_jumpvec; 140 extern mips_locore_jumpvec_t r2000_locore_vec; 141 extern mips_locore_jumpvec_t r4000_locore_vec; 142 extern long *mips_locoresw[]; 143 144 #if defined(MIPS3) && !defined (MIPS1) 145 #if defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_5200) 146 #define MachFlushCache mips5200_FlushCache 147 #define MachFlushDCache mips5200_FlushDCache 148 #define MachHitFlushDCache mips5200_HitFlushDCache 149 #define MachFlushICache mips5200_FlushICache 150 #else 151 #define MachFlushCache mips3_FlushCache 152 #if defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_4100) 153 #define MachFlushDCache mips3_FlushDCache /* VR4100 */ 154 #elif !defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_L2CACHE_PRESENT) 155 #define MachFlushDCache mips3_FlushDCache 156 #else 157 #define MachFlushDCache (*(mips_locore_jumpvec.flushDCache)) 158 #endif 159 #define MachHitFlushDCache mips3_HitFlushDCache 160 #define MachFlushICache mips3_FlushICache 161 #endif 162 #define MachForceCacheUpdate mips3_ForceCacheUpdate 163 #define MachSetPID mips3_SetPID 164 #define MIPS_TBIAP() mips3_TBIAP(mips_num_tlb_entries) 165 #define MIPS_TBIS mips3_TBIS 166 #define MIPS_TBRPL mips3_TBRPL 167 #define MachTLBUpdate mips3_TLBUpdate 168 #define wbflush() mips3_wbflush() 169 #define proc_trampoline mips3_proc_trampoline 170 #endif 171 172 #if !defined(MIPS3) && defined (MIPS1) 173 #define MachFlushCache mips1_FlushCache 174 #define MachFlushDCache mips1_FlushDCache 175 #define MachFlushICache mips1_FlushICache 176 #define MachForceCacheUpdate mips1_ForceCacheUpdate 177 #define MachSetPID mips1_SetPID 178 #define MIPS_TBIAP() mips1_TBIAP(mips_num_tlb_entries) 179 #define MIPS_TBIS mips1_TBIS 180 #define MIPS_TBRPL mips1_TBRPL 181 #define MachTLBUpdate mips1_TLBUpdate 182 #define wbflush() mips1_wbflush() 183 #define proc_trampoline mips1_proc_trampoline 184 #endif 185 186 187 188 #if defined(MIPS3) && defined (MIPS1) 189 #define MachFlushCache (*(mips_locore_jumpvec.flushCache)) 190 #define MachFlushDCache (*(mips_locore_jumpvec.flushDCache)) 191 #define MachFlushICache (*(mips_locore_jumpvec.flushICache)) 192 #define MachForceCacheUpdate (*(mips_locore_jumpvec.forceCacheUpdate)) 193 #define MachSetPID (*(mips_locore_jumpvec.setTLBpid)) 194 #define MIPS_TBIAP() (*(mips_locore_jumpvec.TBIAP))(mips_num_tlb_entries) 195 #define MIPS_TBIS (*(mips_locore_jumpvec.TBIS)) 196 #define MIPS_TBRPL (*(mips_locore_jumpvec.TBRPL)) 197 #define MachTLBUpdate (*(mips_locore_jumpvec.tlbUpdate)) 198 #define MachHitFlushDCache mips3_HitFlushDCache 199 #define wbflush() (*(mips_locore_jumpvec.wbflush))() 200 #define proc_trampoline (mips_locoresw[1]) 201 #endif 202 203 #define CPU_IDLE (mips_locoresw[2]) 204 205 /* cpu_switch_resume is called inside locore.S */ 206 207 /* 208 * CPU identification, from PRID register. 209 */ 210 union cpuprid { 211 int cpuprid; 212 struct { 213 #if BYTE_ORDER == BIG_ENDIAN 214 u_int pad1:16; /* reserved */ 215 u_int cp_imp:8; /* implementation identifier */ 216 u_int cp_majrev:4; /* major revision identifier */ 217 u_int cp_minrev:4; /* minor revision identifier */ 218 #else 219 u_int cp_minrev:4; /* minor revision identifier */ 220 u_int cp_majrev:4; /* major revision identifier */ 221 u_int cp_imp:8; /* implementation identifier */ 222 u_int pad1:16; /* reserved */ 223 #endif 224 } cpu; 225 }; 226 227 228 #ifdef _KERNEL 229 230 /* 231 * Global variables used to communicate CPU type, and parameters 232 * such as cache size, from locore to higher-level code (e.g., pmap). 233 */ 234 extern union cpuprid cpu_id; 235 extern union cpuprid fpu_id; 236 extern int cpu_arch; 237 extern int mips_num_tlb_entries; 238 extern u_int mips_L1DCacheSize; 239 extern u_int mips_L1ICacheSize; 240 extern u_int mips_L1DCacheLSize; 241 extern u_int mips_L1ICacheLSize; 242 extern int mips_L2CachePresent; 243 extern u_int mips_L2CacheLSize; 244 extern u_int mips_CacheAliasMask; 245 246 #ifdef MIPS3 247 extern int mips3_L1TwoWayCache; 248 extern int mips3_cacheflush_bug; 249 #endif /* MIPS3 */ 250 251 /* 252 * trapframe argument passed to trap() 253 */ 254 struct trapframe { 255 mips_reg_t tf_regs[17]; 256 mips_reg_t tf_ra; 257 mips_reg_t tf_sr; 258 mips_reg_t tf_mullo; 259 mips_reg_t tf_mulhi; 260 mips_reg_t tf_epc; /* may be changed by trap() call */ 261 }; 262 263 /* 264 * Stack frame for kernel traps. four args passed in registers. 265 * A trapframe is pointed to by the 5th arg, and a dummy sixth argument 266 * is used to avoid alignment problems 267 */ 268 269 struct kernframe { 270 register_t cf_args[4 + 1]; 271 register_t cf_pad; /* (for 8 word alignment) */ 272 register_t cf_sp; 273 register_t cf_ra; 274 struct trapframe cf_frame; 275 }; 276 277 #endif 278 279 #endif /* _MIPS_LOCORE_H */ 280
Indexes created Tue Sep 30 11:09:46 GMT 2025