locore.h revision 1.32
1 /* $NetBSD: locore.h,v 1.32 2000/05/21 03:23:15 soren Exp $ */ 2 3 /* 4 * Copyright 1996 The Board of Trustees of The Leland Stanford 5 * Junior University. All Rights Reserved. 6 * 7 * Permission to use, copy, modify, and distribute this 8 * software and its documentation for any purpose and without 9 * fee is hereby granted, provided that the above copyright 10 * notice appear in all copies. Stanford University 11 * makes no representations about the suitability of this 12 * software for any purpose. It is provided "as is" without 13 * express or implied warranty. 14 */ 15 16 /* 17 * Jump table for MIPS cpu locore functions that are implemented 18 * differently on different generations, or instruction-level 19 * archtecture (ISA) level, the Mips family. 20 * The following functions must be provided for each mips ISA level: 21 * 22 * 23 * MachFlushCache 24 * MachFlushDCache 25 * MachFlushICache 26 * MachForceCacheUpdate 27 * wbflush 28 * proc_trampoline() 29 * cpu_switch_resume() 30 * 31 * We currently provide support for: 32 * 33 * r2000 and r3000 (mips ISA-I) 34 * r4000 and r4400 in 32-bit mode (mips ISA-III?) 35 */ 36 37 #ifndef _MIPS_LOCORE_H 38 #define _MIPS_LOCORE_H 39 40 #ifndef _LKM 41 #include "opt_cputype.h" 42 #include "opt_mips_cache.h" 43 #endif 44 45 /* 46 * locore service routine for exception vectors. Used outside locore 47 * only to print them by name in stack tracebacks 48 */ 49 50 u_int32_t mips_read_causereg __P((void)); 51 u_int32_t mips_read_statusreg __P((void)); 52 53 void mips1_ConfigCache __P((void)); 54 void mips1_FlushCache __P((void)); 55 void mips1_FlushDCache __P((vaddr_t addr, vsize_t len)); 56 void mips1_FlushICache __P((vaddr_t addr, vsize_t len)); 57 void mips1_ForceCacheUpdate __P((void)); 58 59 void mips1_SetPID __P((int pid)); 60 void mips1_TBIA __P((int)); 61 void mips1_TBIAP __P((int)); 62 void mips1_TBIS __P((vaddr_t)); 63 void mips1_TBRPL __P((vaddr_t, vaddr_t, paddr_t)); 64 int mips1_TLBUpdate __P((u_int, /*pt_entry_t*/ u_int)); 65 66 void mips1_wbflush __P((void)); 67 void mips1_proc_trampoline __P((void)); 68 void mips1_cpu_switch_resume __P((void)); 69 70 void mips3_ConfigCache __P((void)); 71 void mips3_FlushCache __P((void)); 72 void mips3_FlushDCache __P((vaddr_t addr, vaddr_t len)); 73 void mips3_FlushICache __P((vaddr_t addr, vaddr_t len)); 74 void mips3_ForceCacheUpdate __P((void)); 75 void mips3_HitFlushDCache __P((vaddr_t, int)); 76 77 void mips3_SetPID __P((int pid)); 78 void mips3_TBIA __P((int)); 79 void mips3_TBIAP __P((int)); 80 void mips3_TBIS __P((vaddr_t)); 81 void mips3_TBRPL __P((vaddr_t, vaddr_t, paddr_t)); 82 int mips3_TLBUpdate __P((u_int, /*pt_entry_t*/ u_int)); 83 struct tlb; 84 void mips3_TLBRead __P((int, struct tlb *)); 85 #if 0 86 void mips3_TLBWriteIndexedVPS __P((u_int index, struct tlb *tlb)); 87 void mips3_TLBWriteIndexed __P((u_int index, u_int high, 88 u_int lo0, u_int lo1)); 89 #endif 90 void mips3_SetWIRED __P((int)); 91 void mips3_wbflush __P((void)); 92 void mips3_proc_trampoline __P((void)); 93 void mips3_cpu_switch_resume __P((void)); 94 95 void mips5200_FlushCache __P((void)); 96 void mips5200_FlushDCache __P((vaddr_t addr, vaddr_t len)); 97 void mips5200_HitFlushDCache __P((vaddr_t, int)); 98 void mips5200_FlushICache __P((vaddr_t addr, vaddr_t len)); 99 100 u_int32_t mips3_cycle_count __P((void)); 101 u_int32_t mips3_write_count __P((u_int32_t)); 102 u_int32_t mips3_read_compare __P((void)); 103 u_int32_t mips3_read_config __P((void)); 104 void mips3_write_compare __P((u_int32_t)); 105 void mips3_write_xcontext_upper __P((u_int32_t)); 106 void mips3_clearBEV __P((void)); 107 108 /* 109 * A vector with an entry for each mips-ISA-level dependent 110 * locore function, and macros which jump through it. 111 * XXX the macro names are chosen to be compatible with the old 112 * Sprite coding-convention names used in 4.4bsd/pmax. 113 */ 114 typedef struct { 115 void (*flushCache) __P((void)); 116 void (*flushDCache) __P((vaddr_t addr, vsize_t len)); 117 void (*flushICache) __P((vaddr_t addr, vsize_t len)); 118 void (*forceCacheUpdate) __P((void)); 119 void (*setTLBpid) __P((int pid)); 120 void (*TBIAP) __P((int)); 121 void (*TBIS) __P((vaddr_t)); 122 void (*TBRPL) __P((vaddr_t, vaddr_t, paddr_t)); 123 int (*tlbUpdate) __P((u_int highreg, u_int lowreg)); 124 void (*wbflush) __P((void)); 125 } mips_locore_jumpvec_t; 126 127 /* Override writebuffer-drain method. */ 128 void mips_set_wbflush __P((void (*) __P((void)) )); 129 130 131 /* stacktrace() -- print a stack backtrace to the console */ 132 void stacktrace __P((void)); 133 /* logstacktrace() -- log a stack traceback to msgbuf */ 134 void logstacktrace __P((void)); 135 136 /* 137 * The "active" locore-fuction vector, and 138 139 */ 140 extern mips_locore_jumpvec_t mips_locore_jumpvec; 141 extern mips_locore_jumpvec_t r2000_locore_vec; 142 extern mips_locore_jumpvec_t r4000_locore_vec; 143 extern long *mips_locoresw[]; 144 145 #if defined(MIPS3) && !defined (MIPS1) 146 #if defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_5200) 147 #define MachFlushCache mips5200_FlushCache 148 #define MachFlushDCache mips5200_FlushDCache 149 #define MachHitFlushDCache mips5200_HitFlushDCache 150 #define MachFlushICache mips5200_FlushICache 151 #else 152 #define MachFlushCache mips3_FlushCache 153 #if defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_4100) 154 #define MachFlushDCache mips3_FlushDCache /* VR4100 */ 155 #elif !defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_L2CACHE_PRESENT) 156 #define MachFlushDCache mips3_FlushDCache 157 #else 158 #define MachFlushDCache (*(mips_locore_jumpvec.flushDCache)) 159 #endif 160 #define MachHitFlushDCache mips3_HitFlushDCache 161 #define MachFlushICache mips3_FlushICache 162 #endif 163 #define MachForceCacheUpdate mips3_ForceCacheUpdate 164 #define MachSetPID mips3_SetPID 165 #define MIPS_TBIAP() mips3_TBIAP(mips_num_tlb_entries) 166 #define MIPS_TBIS mips3_TBIS 167 #define MIPS_TBRPL mips3_TBRPL 168 #define MachTLBUpdate mips3_TLBUpdate 169 #define wbflush() mips3_wbflush() 170 #define proc_trampoline mips3_proc_trampoline 171 #endif 172 173 #if !defined(MIPS3) && defined (MIPS1) 174 #define MachFlushCache mips1_FlushCache 175 #define MachFlushDCache mips1_FlushDCache 176 #define MachFlushICache mips1_FlushICache 177 #define MachForceCacheUpdate mips1_ForceCacheUpdate 178 #define MachSetPID mips1_SetPID 179 #define MIPS_TBIAP() mips1_TBIAP(mips_num_tlb_entries) 180 #define MIPS_TBIS mips1_TBIS 181 #define MIPS_TBRPL mips1_TBRPL 182 #define MachTLBUpdate mips1_TLBUpdate 183 #define wbflush() mips1_wbflush() 184 #define proc_trampoline mips1_proc_trampoline 185 #endif 186 187 188 189 #if defined(MIPS3) && defined (MIPS1) 190 #define MachFlushCache (*(mips_locore_jumpvec.flushCache)) 191 #define MachFlushDCache (*(mips_locore_jumpvec.flushDCache)) 192 #define MachFlushICache (*(mips_locore_jumpvec.flushICache)) 193 #define MachForceCacheUpdate (*(mips_locore_jumpvec.forceCacheUpdate)) 194 #define MachSetPID (*(mips_locore_jumpvec.setTLBpid)) 195 #define MIPS_TBIAP() (*(mips_locore_jumpvec.TBIAP))(mips_num_tlb_entries) 196 #define MIPS_TBIS (*(mips_locore_jumpvec.TBIS)) 197 #define MIPS_TBRPL (*(mips_locore_jumpvec.TBRPL)) 198 #define MachTLBUpdate (*(mips_locore_jumpvec.tlbUpdate)) 199 #define MachHitFlushDCache mips3_HitFlushDCache 200 #define wbflush() (*(mips_locore_jumpvec.wbflush))() 201 #define proc_trampoline (mips_locoresw[1]) 202 #endif 203 204 #define CPU_IDLE (mips_locoresw[2]) 205 206 /* cpu_switch_resume is called inside locore.S */ 207 208 /* 209 * CPU identification, from PRID register. 210 */ 211 union cpuprid { 212 int cpuprid; 213 struct { 214 #if BYTE_ORDER == BIG_ENDIAN 215 u_int pad1:16; /* reserved */ 216 u_int cp_imp:8; /* implementation identifier */ 217 u_int cp_majrev:4; /* major revision identifier */ 218 u_int cp_minrev:4; /* minor revision identifier */ 219 #else 220 u_int cp_minrev:4; /* minor revision identifier */ 221 u_int cp_majrev:4; /* major revision identifier */ 222 u_int cp_imp:8; /* implementation identifier */ 223 u_int pad1:16; /* reserved */ 224 #endif 225 } cpu; 226 }; 227 228 229 #ifdef _KERNEL 230 231 /* 232 * Global variables used to communicate CPU type, and parameters 233 * such as cache size, from locore to higher-level code (e.g., pmap). 234 */ 235 extern union cpuprid cpu_id; 236 extern union cpuprid fpu_id; 237 extern int cpu_arch; 238 extern int mips_num_tlb_entries; 239 extern u_int mips_L1DCacheSize; 240 extern u_int mips_L1ICacheSize; 241 extern u_int mips_L1DCacheLSize; 242 extern u_int mips_L1ICacheLSize; 243 extern int mips_L2CachePresent; 244 extern u_int mips_L2CacheLSize; 245 extern u_int mips_CacheAliasMask; 246 247 #ifdef MIPS3 248 extern int mips3_L1TwoWayCache; 249 extern int mips3_cacheflush_bug; 250 #endif /* MIPS3 */ 251 252 /* 253 * trapframe argument passed to trap() 254 */ 255 struct trapframe { 256 mips_reg_t tf_regs[17]; 257 mips_reg_t tf_ra; 258 mips_reg_t tf_sr; 259 mips_reg_t tf_mullo; 260 mips_reg_t tf_mulhi; 261 mips_reg_t tf_epc; /* may be changed by trap() call */ 262 }; 263 264 /* 265 * Stack frame for kernel traps. four args passed in registers. 266 * A trapframe is pointed to by the 5th arg, and a dummy sixth argument 267 * is used to avoid alignment problems 268 */ 269 270 struct kernframe { 271 register_t cf_args[4 + 1]; 272 register_t cf_pad; /* (for 8 word alignment) */ 273 register_t cf_sp; 274 register_t cf_ra; 275 struct trapframe cf_frame; 276 }; 277 278 #endif 279 280 #endif /* _MIPS_LOCORE_H */ 281
Indexes created Mon Sep 29 21:09:56 GMT 2025