locore.h revision 1.33
1 /* $NetBSD: locore.h,v 1.33 2000/05/23 04:21:40 soren Exp $ */ 2 3 /* 4 * Copyright 1996 The Board of Trustees of The Leland Stanford 5 * Junior University. All Rights Reserved. 6 * 7 * Permission to use, copy, modify, and distribute this 8 * software and its documentation for any purpose and without 9 * fee is hereby granted, provided that the above copyright 10 * notice appear in all copies. Stanford University 11 * makes no representations about the suitability of this 12 * software for any purpose. It is provided "as is" without 13 * express or implied warranty. 14 */ 15 16 /* 17 * Jump table for MIPS cpu locore functions that are implemented 18 * differently on different generations, or instruction-level 19 * archtecture (ISA) level, the Mips family. 20 * The following functions must be provided for each mips ISA level: 21 * 22 * 23 * MachFlushCache 24 * MachFlushDCache 25 * MachFlushICache 26 * wbflush 27 * proc_trampoline() 28 * cpu_switch_resume() 29 * 30 * We currently provide support for MIPS I and MIPS III. 31 */ 32 33 #ifndef _MIPS_LOCORE_H 34 #define _MIPS_LOCORE_H 35 36 #ifndef _LKM 37 #include "opt_cputype.h" 38 #include "opt_mips_cache.h" 39 #endif 40 41 /* 42 * locore service routine for exception vectors. Used outside locore 43 * only to print them by name in stack tracebacks 44 */ 45 46 u_int32_t mips_read_causereg __P((void)); 47 u_int32_t mips_read_statusreg __P((void)); 48 49 void mips1_ConfigCache __P((void)); 50 void mips1_FlushCache __P((void)); 51 void mips1_FlushDCache __P((vaddr_t addr, vsize_t len)); 52 void mips1_FlushICache __P((vaddr_t addr, vsize_t len)); 53 54 void mips1_SetPID __P((int pid)); 55 void mips1_TBIA __P((int)); 56 void mips1_TBIAP __P((int)); 57 void mips1_TBIS __P((vaddr_t)); 58 void mips1_TBRPL __P((vaddr_t, vaddr_t, paddr_t)); 59 int mips1_TLBUpdate __P((u_int, /*pt_entry_t*/ u_int)); 60 61 void mips1_wbflush __P((void)); 62 void mips1_proc_trampoline __P((void)); 63 void mips1_cpu_switch_resume __P((void)); 64 65 void mips3_ConfigCache __P((void)); 66 void mips3_FlushCache __P((void)); 67 void mips3_FlushDCache __P((vaddr_t addr, vaddr_t len)); 68 void mips3_FlushICache __P((vaddr_t addr, vaddr_t len)); 69 void mips3_HitFlushDCache __P((vaddr_t, int)); 70 71 void mips3_SetPID __P((int pid)); 72 void mips3_TBIA __P((int)); 73 void mips3_TBIAP __P((int)); 74 void mips3_TBIS __P((vaddr_t)); 75 void mips3_TBRPL __P((vaddr_t, vaddr_t, paddr_t)); 76 int mips3_TLBUpdate __P((u_int, /*pt_entry_t*/ u_int)); 77 struct tlb; 78 void mips3_TLBRead __P((int, struct tlb *)); 79 #if 0 80 void mips3_TLBWriteIndexedVPS __P((u_int index, struct tlb *tlb)); 81 void mips3_TLBWriteIndexed __P((u_int index, u_int high, 82 u_int lo0, u_int lo1)); 83 #endif 84 void mips3_SetWIRED __P((int)); 85 void mips3_wbflush __P((void)); 86 void mips3_proc_trampoline __P((void)); 87 void mips3_cpu_switch_resume __P((void)); 88 89 void mips5200_FlushCache __P((void)); 90 void mips5200_FlushDCache __P((vaddr_t addr, vaddr_t len)); 91 void mips5200_HitFlushDCache __P((vaddr_t, int)); 92 void mips5200_FlushICache __P((vaddr_t addr, vaddr_t len)); 93 94 u_int32_t mips3_cycle_count __P((void)); 95 u_int32_t mips3_write_count __P((u_int32_t)); 96 u_int32_t mips3_read_compare __P((void)); 97 u_int32_t mips3_read_config __P((void)); 98 void mips3_write_compare __P((u_int32_t)); 99 void mips3_write_xcontext_upper __P((u_int32_t)); 100 void mips3_clearBEV __P((void)); 101 102 /* 103 * A vector with an entry for each mips-ISA-level dependent 104 * locore function, and macros which jump through it. 105 * XXX the macro names are chosen to be compatible with the old 106 * Sprite coding-convention names used in 4.4bsd/pmax. 107 */ 108 typedef struct { 109 void (*flushCache) __P((void)); 110 void (*flushDCache) __P((vaddr_t addr, vsize_t len)); 111 void (*flushICache) __P((vaddr_t addr, vsize_t len)); 112 void (*setTLBpid) __P((int pid)); 113 void (*TBIAP) __P((int)); 114 void (*TBIS) __P((vaddr_t)); 115 void (*TBRPL) __P((vaddr_t, vaddr_t, paddr_t)); 116 int (*tlbUpdate) __P((u_int highreg, u_int lowreg)); 117 void (*wbflush) __P((void)); 118 } mips_locore_jumpvec_t; 119 120 /* Override writebuffer-drain method. */ 121 void mips_set_wbflush __P((void (*) __P((void)) )); 122 123 124 /* stacktrace() -- print a stack backtrace to the console */ 125 void stacktrace __P((void)); 126 /* logstacktrace() -- log a stack traceback to msgbuf */ 127 void logstacktrace __P((void)); 128 129 /* 130 * The "active" locore-fuction vector, and 131 132 */ 133 extern mips_locore_jumpvec_t mips_locore_jumpvec; 134 extern mips_locore_jumpvec_t r2000_locore_vec; 135 extern mips_locore_jumpvec_t r4000_locore_vec; 136 extern long *mips_locoresw[]; 137 138 #if defined(MIPS3) && !defined (MIPS1) 139 #if defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_5200) 140 #define MachFlushCache mips5200_FlushCache 141 #define MachFlushDCache mips5200_FlushDCache 142 #define MachHitFlushDCache mips5200_HitFlushDCache 143 #define MachFlushICache mips5200_FlushICache 144 #else 145 #define MachFlushCache mips3_FlushCache 146 #if defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_4100) 147 #define MachFlushDCache mips3_FlushDCache /* VR4100 */ 148 #elif !defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_L2CACHE_PRESENT) 149 #define MachFlushDCache mips3_FlushDCache 150 #else 151 #define MachFlushDCache (*(mips_locore_jumpvec.flushDCache)) 152 #endif 153 #define MachHitFlushDCache mips3_HitFlushDCache 154 #define MachFlushICache mips3_FlushICache 155 #endif 156 #define MachSetPID mips3_SetPID 157 #define MIPS_TBIAP() mips3_TBIAP(mips_num_tlb_entries) 158 #define MIPS_TBIS mips3_TBIS 159 #define MIPS_TBRPL mips3_TBRPL 160 #define MachTLBUpdate mips3_TLBUpdate 161 #define wbflush() mips3_wbflush() 162 #define proc_trampoline mips3_proc_trampoline 163 #endif 164 165 #if !defined(MIPS3) && defined (MIPS1) 166 #define MachFlushCache mips1_FlushCache 167 #define MachFlushDCache mips1_FlushDCache 168 #define MachFlushICache mips1_FlushICache 169 #define MachSetPID mips1_SetPID 170 #define MIPS_TBIAP() mips1_TBIAP(mips_num_tlb_entries) 171 #define MIPS_TBIS mips1_TBIS 172 #define MIPS_TBRPL mips1_TBRPL 173 #define MachTLBUpdate mips1_TLBUpdate 174 #define wbflush() mips1_wbflush() 175 #define proc_trampoline mips1_proc_trampoline 176 #endif 177 178 179 180 #if defined(MIPS3) && defined (MIPS1) 181 #define MachFlushCache (*(mips_locore_jumpvec.flushCache)) 182 #define MachFlushDCache (*(mips_locore_jumpvec.flushDCache)) 183 #define MachFlushICache (*(mips_locore_jumpvec.flushICache)) 184 #define MachSetPID (*(mips_locore_jumpvec.setTLBpid)) 185 #define MIPS_TBIAP() (*(mips_locore_jumpvec.TBIAP))(mips_num_tlb_entries) 186 #define MIPS_TBIS (*(mips_locore_jumpvec.TBIS)) 187 #define MIPS_TBRPL (*(mips_locore_jumpvec.TBRPL)) 188 #define MachTLBUpdate (*(mips_locore_jumpvec.tlbUpdate)) 189 #define MachHitFlushDCache mips3_HitFlushDCache 190 #define wbflush() (*(mips_locore_jumpvec.wbflush))() 191 #define proc_trampoline (mips_locoresw[1]) 192 #endif 193 194 #define CPU_IDLE (mips_locoresw[2]) 195 196 /* cpu_switch_resume is called inside locore.S */ 197 198 /* 199 * CPU identification, from PRID register. 200 */ 201 union cpuprid { 202 int cpuprid; 203 struct { 204 #if BYTE_ORDER == BIG_ENDIAN 205 u_int pad1:16; /* reserved */ 206 u_int cp_imp:8; /* implementation identifier */ 207 u_int cp_majrev:4; /* major revision identifier */ 208 u_int cp_minrev:4; /* minor revision identifier */ 209 #else 210 u_int cp_minrev:4; /* minor revision identifier */ 211 u_int cp_majrev:4; /* major revision identifier */ 212 u_int cp_imp:8; /* implementation identifier */ 213 u_int pad1:16; /* reserved */ 214 #endif 215 } cpu; 216 }; 217 218 219 #ifdef _KERNEL 220 221 /* 222 * Global variables used to communicate CPU type, and parameters 223 * such as cache size, from locore to higher-level code (e.g., pmap). 224 */ 225 extern union cpuprid cpu_id; 226 extern union cpuprid fpu_id; 227 extern int cpu_arch; 228 extern int mips_num_tlb_entries; 229 extern u_int mips_L1DCacheSize; 230 extern u_int mips_L1ICacheSize; 231 extern u_int mips_L1DCacheLSize; 232 extern u_int mips_L1ICacheLSize; 233 extern int mips_L2CachePresent; 234 extern u_int mips_L2CacheLSize; 235 extern u_int mips_CacheAliasMask; 236 237 #ifdef MIPS3 238 extern int mips3_L1TwoWayCache; 239 extern int mips3_cacheflush_bug; 240 #endif /* MIPS3 */ 241 242 /* 243 * trapframe argument passed to trap() 244 */ 245 struct trapframe { 246 mips_reg_t tf_regs[17]; 247 mips_reg_t tf_ra; 248 mips_reg_t tf_sr; 249 mips_reg_t tf_mullo; 250 mips_reg_t tf_mulhi; 251 mips_reg_t tf_epc; /* may be changed by trap() call */ 252 }; 253 254 /* 255 * Stack frame for kernel traps. four args passed in registers. 256 * A trapframe is pointed to by the 5th arg, and a dummy sixth argument 257 * is used to avoid alignment problems 258 */ 259 260 struct kernframe { 261 register_t cf_args[4 + 1]; 262 register_t cf_pad; /* (for 8 word alignment) */ 263 register_t cf_sp; 264 register_t cf_ra; 265 struct trapframe cf_frame; 266 }; 267 268 #endif 269 270 #endif /* _MIPS_LOCORE_H */ 271
Indexes created Tue Sep 30 11:09:46 GMT 2025