locore.h revision 1.34
1 /* $NetBSD: locore.h,v 1.34 2000/06/06 17:41:07 soren Exp $ */ 2 3 /* 4 * Copyright 1996 The Board of Trustees of The Leland Stanford 5 * Junior University. All Rights Reserved. 6 * 7 * Permission to use, copy, modify, and distribute this 8 * software and its documentation for any purpose and without 9 * fee is hereby granted, provided that the above copyright 10 * notice appear in all copies. Stanford University 11 * makes no representations about the suitability of this 12 * software for any purpose. It is provided "as is" without 13 * express or implied warranty. 14 */ 15 16 /* 17 * Jump table for MIPS cpu locore functions that are implemented 18 * differently on different generations, or instruction-level 19 * archtecture (ISA) level, the Mips family. 20 * The following functions must be provided for each mips ISA level: 21 * 22 * 23 * MachFlushCache 24 * MachFlushDCache 25 * MachFlushICache 26 * wbflush 27 * proc_trampoline() 28 * cpu_switch_resume() 29 * 30 * We currently provide support for MIPS I and MIPS III. 31 */ 32 33 #ifndef _MIPS_LOCORE_H 34 #define _MIPS_LOCORE_H 35 36 #ifndef _LKM 37 #include "opt_cputype.h" 38 #include "opt_mips_cache.h" 39 #endif 40 41 /* 42 * locore service routine for exception vectors. Used outside locore 43 * only to print them by name in stack tracebacks 44 */ 45 46 u_int32_t mips_read_causereg __P((void)); 47 u_int32_t mips_read_statusreg __P((void)); 48 49 void mips1_ConfigCache __P((void)); 50 void mips1_FlushCache __P((void)); 51 void mips1_FlushDCache __P((vaddr_t addr, vsize_t len)); 52 void mips1_FlushICache __P((vaddr_t addr, vsize_t len)); 53 54 void mips1_SetPID __P((int pid)); 55 void mips1_TBIA __P((int)); 56 void mips1_TBIAP __P((int)); 57 void mips1_TBIS __P((vaddr_t)); 58 void mips1_TBRPL __P((vaddr_t, vaddr_t, paddr_t)); 59 int mips1_TLBUpdate __P((u_int, u_int)); 60 61 void mips1_wbflush __P((void)); 62 void mips1_proc_trampoline __P((void)); 63 void mips1_cpu_switch_resume __P((void)); 64 65 void mips3_ConfigCache __P((void)); 66 void mips3_FlushCache __P((void)); 67 void mips3_FlushDCache __P((vaddr_t addr, vaddr_t len)); 68 void mips3_FlushICache __P((vaddr_t addr, vaddr_t len)); 69 void mips3_HitFlushDCache __P((vaddr_t, int)); 70 71 void mips3_SetPID __P((int pid)); 72 void mips3_TBIA __P((int)); 73 void mips3_TBIAP __P((int)); 74 void mips3_TBIS __P((vaddr_t)); 75 void mips3_TBRPL __P((vaddr_t, vaddr_t, paddr_t)); 76 int mips3_TLBUpdate __P((u_int, u_int)); 77 struct tlb; 78 void mips3_TLBRead __P((int, struct tlb *)); 79 void mips3_SetWIRED __P((int)); 80 void mips3_wbflush __P((void)); 81 void mips3_proc_trampoline __P((void)); 82 void mips3_cpu_switch_resume __P((void)); 83 84 void mips3_FlushCache_2way __P((void)); 85 void mips3_FlushDCache_2way __P((vaddr_t addr, vaddr_t len)); 86 void mips3_HitFlushDCache_2way __P((vaddr_t, int)); 87 void mips3_FlushICache_2way __P((vaddr_t addr, vaddr_t len)); 88 89 u_int32_t mips3_cycle_count __P((void)); 90 u_int32_t mips3_write_count __P((u_int32_t)); 91 u_int32_t mips3_read_compare __P((void)); 92 u_int32_t mips3_read_config __P((void)); 93 void mips3_write_compare __P((u_int32_t)); 94 void mips3_write_xcontext_upper __P((u_int32_t)); 95 void mips3_clearBEV __P((void)); 96 97 /* 98 * A vector with an entry for each mips-ISA-level dependent 99 * locore function, and macros which jump through it. 100 * XXX the macro names are chosen to be compatible with the old 101 * Sprite coding-convention names used in 4.4bsd/pmax. 102 */ 103 typedef struct { 104 void (*flushCache) __P((void)); 105 void (*flushDCache) __P((vaddr_t addr, vsize_t len)); 106 void (*flushICache) __P((vaddr_t addr, vsize_t len)); 107 void (*setTLBpid) __P((int pid)); 108 void (*TBIAP) __P((int)); 109 void (*TBIS) __P((vaddr_t)); 110 void (*TBRPL) __P((vaddr_t, vaddr_t, paddr_t)); 111 int (*tlbUpdate) __P((u_int highreg, u_int lowreg)); 112 void (*wbflush) __P((void)); 113 } mips_locore_jumpvec_t; 114 115 /* Override writebuffer-drain method. */ 116 void mips_set_wbflush __P((void (*) __P((void)) )); 117 118 119 /* stacktrace() -- print a stack backtrace to the console */ 120 void stacktrace __P((void)); 121 /* logstacktrace() -- log a stack traceback to msgbuf */ 122 void logstacktrace __P((void)); 123 124 /* 125 * The "active" locore-fuction vector, and 126 127 */ 128 extern mips_locore_jumpvec_t mips_locore_jumpvec; 129 extern mips_locore_jumpvec_t r2000_locore_vec; 130 extern mips_locore_jumpvec_t r4000_locore_vec; 131 extern long *mips_locoresw[]; 132 133 #if defined(MIPS3) && !defined (MIPS1) 134 #if defined(MIPS3_5200) 135 #define MachFlushCache mips3_FlushCache_2way 136 #define MachFlushDCache mips3_FlushDCache_2way 137 #define MachHitFlushDCache mips3_HitFlushDCache_2way 138 #define MachFlushICache mips3_FlushICache_2way 139 #else 140 #define MachFlushCache mips3_FlushCache 141 #if defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_4100) 142 #define MachFlushDCache mips3_FlushDCache /* VR4100 */ 143 #elif !defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_L2CACHE_PRESENT) 144 #define MachFlushDCache mips3_FlushDCache 145 #else 146 #define MachFlushDCache (*(mips_locore_jumpvec.flushDCache)) 147 #endif 148 #define MachHitFlushDCache mips3_HitFlushDCache 149 #define MachFlushICache mips3_FlushICache 150 #endif 151 #define MachSetPID mips3_SetPID 152 #define MIPS_TBIAP() mips3_TBIAP(mips_num_tlb_entries) 153 #define MIPS_TBIS mips3_TBIS 154 #define MIPS_TBRPL mips3_TBRPL 155 #define MachTLBUpdate mips3_TLBUpdate 156 #define wbflush() mips3_wbflush() 157 #define proc_trampoline mips3_proc_trampoline 158 #endif 159 160 #if !defined(MIPS3) && defined (MIPS1) 161 #define MachFlushCache mips1_FlushCache 162 #define MachFlushDCache mips1_FlushDCache 163 #define MachFlushICache mips1_FlushICache 164 #define MachSetPID mips1_SetPID 165 #define MIPS_TBIAP() mips1_TBIAP(mips_num_tlb_entries) 166 #define MIPS_TBIS mips1_TBIS 167 #define MIPS_TBRPL mips1_TBRPL 168 #define MachTLBUpdate mips1_TLBUpdate 169 #define wbflush() mips1_wbflush() 170 #define proc_trampoline mips1_proc_trampoline 171 #endif 172 173 174 175 #if defined(MIPS3) && defined (MIPS1) 176 #define MachFlushCache (*(mips_locore_jumpvec.flushCache)) 177 #define MachFlushDCache (*(mips_locore_jumpvec.flushDCache)) 178 #define MachFlushICache (*(mips_locore_jumpvec.flushICache)) 179 #define MachSetPID (*(mips_locore_jumpvec.setTLBpid)) 180 #define MIPS_TBIAP() (*(mips_locore_jumpvec.TBIAP))(mips_num_tlb_entries) 181 #define MIPS_TBIS (*(mips_locore_jumpvec.TBIS)) 182 #define MIPS_TBRPL (*(mips_locore_jumpvec.TBRPL)) 183 #define MachTLBUpdate (*(mips_locore_jumpvec.tlbUpdate)) 184 #define MachHitFlushDCache mips3_HitFlushDCache 185 #define wbflush() (*(mips_locore_jumpvec.wbflush))() 186 #define proc_trampoline (mips_locoresw[1]) 187 #endif 188 189 #define CPU_IDLE (mips_locoresw[2]) 190 191 /* cpu_switch_resume is called inside locore.S */ 192 193 /* 194 * CPU identification, from PRID register. 195 */ 196 union cpuprid { 197 int cpuprid; 198 struct { 199 #if BYTE_ORDER == BIG_ENDIAN 200 u_int pad1:16; /* reserved */ 201 u_int cp_imp:8; /* implementation identifier */ 202 u_int cp_majrev:4; /* major revision identifier */ 203 u_int cp_minrev:4; /* minor revision identifier */ 204 #else 205 u_int cp_minrev:4; /* minor revision identifier */ 206 u_int cp_majrev:4; /* major revision identifier */ 207 u_int cp_imp:8; /* implementation identifier */ 208 u_int pad1:16; /* reserved */ 209 #endif 210 } cpu; 211 }; 212 213 214 #ifdef _KERNEL 215 216 /* 217 * Global variables used to communicate CPU type, and parameters 218 * such as cache size, from locore to higher-level code (e.g., pmap). 219 */ 220 extern union cpuprid cpu_id; 221 extern union cpuprid fpu_id; 222 extern int cpu_arch; 223 extern int mips_num_tlb_entries; 224 extern u_int mips_L1DCacheSize; 225 extern u_int mips_L1ICacheSize; 226 extern u_int mips_L1DCacheLSize; 227 extern u_int mips_L1ICacheLSize; 228 extern int mips_L2CachePresent; 229 extern u_int mips_L2CacheLSize; 230 extern u_int mips_CacheAliasMask; 231 232 #ifdef MIPS3 233 extern int mips3_L1TwoWayCache; 234 extern int mips3_cacheflush_bug; 235 #endif /* MIPS3 */ 236 237 /* 238 * trapframe argument passed to trap() 239 */ 240 struct trapframe { 241 mips_reg_t tf_regs[17]; 242 mips_reg_t tf_ra; 243 mips_reg_t tf_sr; 244 mips_reg_t tf_mullo; 245 mips_reg_t tf_mulhi; 246 mips_reg_t tf_epc; /* may be changed by trap() call */ 247 }; 248 249 /* 250 * Stack frame for kernel traps. four args passed in registers. 251 * A trapframe is pointed to by the 5th arg, and a dummy sixth argument 252 * is used to avoid alignment problems 253 */ 254 255 struct kernframe { 256 register_t cf_args[4 + 1]; 257 register_t cf_pad; /* (for 8 word alignment) */ 258 register_t cf_sp; 259 register_t cf_ra; 260 struct trapframe cf_frame; 261 }; 262 263 #endif 264 265 #endif /* _MIPS_LOCORE_H */ 266
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