locore.h revision 1.35
1 /* $NetBSD: locore.h,v 1.35 2000/06/20 02:57:19 soren Exp $ */ 2 3 /* 4 * Copyright 1996 The Board of Trustees of The Leland Stanford 5 * Junior University. All Rights Reserved. 6 * 7 * Permission to use, copy, modify, and distribute this 8 * software and its documentation for any purpose and without 9 * fee is hereby granted, provided that the above copyright 10 * notice appear in all copies. Stanford University 11 * makes no representations about the suitability of this 12 * software for any purpose. It is provided "as is" without 13 * express or implied warranty. 14 */ 15 16 /* 17 * Jump table for MIPS cpu locore functions that are implemented 18 * differently on different generations, or instruction-level 19 * archtecture (ISA) level, the Mips family. 20 * The following functions must be provided for each mips ISA level: 21 * 22 * 23 * MachFlushCache 24 * MachFlushDCache 25 * MachFlushICache 26 * wbflush 27 * proc_trampoline() 28 * cpu_switch_resume() 29 * 30 * We currently provide support for MIPS I and MIPS III. 31 */ 32 33 #ifndef _MIPS_LOCORE_H 34 #define _MIPS_LOCORE_H 35 36 #ifndef _LKM 37 #include "opt_cputype.h" 38 #include "opt_mips_cache.h" 39 #endif 40 41 /* 42 * locore service routine for exception vectors. Used outside locore 43 * only to print them by name in stack tracebacks 44 */ 45 46 u_int32_t mips_read_causereg __P((void)); 47 u_int32_t mips_read_statusreg __P((void)); 48 49 void mips1_ConfigCache __P((void)); 50 void mips1_FlushCache __P((void)); 51 void mips1_FlushDCache __P((vaddr_t addr, vsize_t len)); 52 void mips1_FlushICache __P((vaddr_t addr, vsize_t len)); 53 54 void mips1_SetPID __P((int pid)); 55 void mips1_TBIA __P((int)); 56 void mips1_TBIAP __P((int)); 57 void mips1_TBIS __P((vaddr_t)); 58 void mips1_TBRPL __P((vaddr_t, vaddr_t, paddr_t)); 59 int mips1_TLBUpdate __P((u_int, u_int)); 60 61 void mips1_wbflush __P((void)); 62 void mips1_proc_trampoline __P((void)); 63 void mips1_cpu_switch_resume __P((void)); 64 65 void mips3_ConfigCache __P((void)); 66 void mips3_FlushCache __P((void)); 67 void mips3_FlushDCache __P((vaddr_t addr, vaddr_t len)); 68 void mips3_FlushICache __P((vaddr_t addr, vaddr_t len)); 69 void mips3_HitFlushDCache __P((vaddr_t, int)); 70 71 void mips3_SetPID __P((int pid)); 72 void mips3_TBIA __P((int)); 73 void mips3_TBIAP __P((int)); 74 void mips3_TBIS __P((vaddr_t)); 75 void mips3_TBRPL __P((vaddr_t, vaddr_t, paddr_t)); 76 int mips3_TLBUpdate __P((u_int, u_int)); 77 struct tlb; 78 void mips3_TLBRead __P((int, struct tlb *)); 79 void mips3_SetWIRED __P((int)); 80 void mips3_wbflush __P((void)); 81 void mips3_proc_trampoline __P((void)); 82 void mips3_cpu_switch_resume __P((void)); 83 84 void mips3_FlushCache_2way __P((void)); 85 void mips3_FlushDCache_2way __P((vaddr_t addr, vaddr_t len)); 86 void mips3_HitFlushDCache_2way __P((vaddr_t, int)); 87 void mips3_FlushICache_2way __P((vaddr_t addr, vaddr_t len)); 88 89 u_int32_t mips3_read_config __P((void)); 90 u_int32_t mips3_cycle_count __P((void)); 91 u_int32_t mips3_write_count __P((u_int32_t)); 92 u_int32_t mips3_read_compare __P((void)); 93 void mips3_write_config __P((u_int32_t)); 94 void mips3_write_compare __P((u_int32_t)); 95 void mips3_write_xcontext_upper __P((u_int32_t)); 96 void mips3_clearBEV __P((void)); 97 98 /* 99 * A vector with an entry for each mips-ISA-level dependent 100 * locore function, and macros which jump through it. 101 * XXX the macro names are chosen to be compatible with the old 102 * Sprite coding-convention names used in 4.4bsd/pmax. 103 */ 104 typedef struct { 105 void (*flushCache) __P((void)); 106 void (*flushDCache) __P((vaddr_t addr, vsize_t len)); 107 void (*flushICache) __P((vaddr_t addr, vsize_t len)); 108 void (*setTLBpid) __P((int pid)); 109 void (*TBIAP) __P((int)); 110 void (*TBIS) __P((vaddr_t)); 111 void (*TBRPL) __P((vaddr_t, vaddr_t, paddr_t)); 112 int (*tlbUpdate) __P((u_int highreg, u_int lowreg)); 113 void (*wbflush) __P((void)); 114 } mips_locore_jumpvec_t; 115 116 /* Override writebuffer-drain method. */ 117 void mips_set_wbflush __P((void (*) __P((void)) )); 118 119 120 /* stacktrace() -- print a stack backtrace to the console */ 121 void stacktrace __P((void)); 122 /* logstacktrace() -- log a stack traceback to msgbuf */ 123 void logstacktrace __P((void)); 124 125 /* 126 * The "active" locore-fuction vector, and 127 128 */ 129 extern mips_locore_jumpvec_t mips_locore_jumpvec; 130 extern mips_locore_jumpvec_t r2000_locore_vec; 131 extern mips_locore_jumpvec_t r4000_locore_vec; 132 extern long *mips_locoresw[]; 133 134 #if defined(MIPS3) && !defined (MIPS1) 135 #if defined(MIPS3_5200) 136 #define MachFlushCache mips3_FlushCache_2way 137 #define MachFlushDCache mips3_FlushDCache_2way 138 #define MachHitFlushDCache mips3_HitFlushDCache_2way 139 #define MachFlushICache mips3_FlushICache_2way 140 #else 141 #define MachFlushCache mips3_FlushCache 142 #if defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_4100) 143 #define MachFlushDCache mips3_FlushDCache /* VR4100 */ 144 #elif !defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_L2CACHE_PRESENT) 145 #define MachFlushDCache mips3_FlushDCache 146 #else 147 #define MachFlushDCache (*(mips_locore_jumpvec.flushDCache)) 148 #endif 149 #define MachHitFlushDCache mips3_HitFlushDCache 150 #define MachFlushICache mips3_FlushICache 151 #endif 152 #define MachSetPID mips3_SetPID 153 #define MIPS_TBIAP() mips3_TBIAP(mips_num_tlb_entries) 154 #define MIPS_TBIS mips3_TBIS 155 #define MIPS_TBRPL mips3_TBRPL 156 #define MachTLBUpdate mips3_TLBUpdate 157 #define wbflush() mips3_wbflush() 158 #define proc_trampoline mips3_proc_trampoline 159 #endif 160 161 #if !defined(MIPS3) && defined (MIPS1) 162 #define MachFlushCache mips1_FlushCache 163 #define MachFlushDCache mips1_FlushDCache 164 #define MachFlushICache mips1_FlushICache 165 #define MachSetPID mips1_SetPID 166 #define MIPS_TBIAP() mips1_TBIAP(mips_num_tlb_entries) 167 #define MIPS_TBIS mips1_TBIS 168 #define MIPS_TBRPL mips1_TBRPL 169 #define MachTLBUpdate mips1_TLBUpdate 170 #define wbflush() mips1_wbflush() 171 #define proc_trampoline mips1_proc_trampoline 172 #endif 173 174 175 176 #if defined(MIPS3) && defined (MIPS1) 177 #define MachFlushCache (*(mips_locore_jumpvec.flushCache)) 178 #define MachFlushDCache (*(mips_locore_jumpvec.flushDCache)) 179 #define MachFlushICache (*(mips_locore_jumpvec.flushICache)) 180 #define MachSetPID (*(mips_locore_jumpvec.setTLBpid)) 181 #define MIPS_TBIAP() (*(mips_locore_jumpvec.TBIAP))(mips_num_tlb_entries) 182 #define MIPS_TBIS (*(mips_locore_jumpvec.TBIS)) 183 #define MIPS_TBRPL (*(mips_locore_jumpvec.TBRPL)) 184 #define MachTLBUpdate (*(mips_locore_jumpvec.tlbUpdate)) 185 #define MachHitFlushDCache mips3_HitFlushDCache 186 #define wbflush() (*(mips_locore_jumpvec.wbflush))() 187 #define proc_trampoline (mips_locoresw[1]) 188 #endif 189 190 #define CPU_IDLE (mips_locoresw[2]) 191 192 /* cpu_switch_resume is called inside locore.S */ 193 194 /* 195 * CPU identification, from PRID register. 196 */ 197 union cpuprid { 198 int cpuprid; 199 struct { 200 #if BYTE_ORDER == BIG_ENDIAN 201 u_int pad1:16; /* reserved */ 202 u_int cp_imp:8; /* implementation identifier */ 203 u_int cp_majrev:4; /* major revision identifier */ 204 u_int cp_minrev:4; /* minor revision identifier */ 205 #else 206 u_int cp_minrev:4; /* minor revision identifier */ 207 u_int cp_majrev:4; /* major revision identifier */ 208 u_int cp_imp:8; /* implementation identifier */ 209 u_int pad1:16; /* reserved */ 210 #endif 211 } cpu; 212 }; 213 214 215 #ifdef _KERNEL 216 217 /* 218 * Global variables used to communicate CPU type, and parameters 219 * such as cache size, from locore to higher-level code (e.g., pmap). 220 */ 221 extern union cpuprid cpu_id; 222 extern union cpuprid fpu_id; 223 extern int cpu_arch; 224 extern int mips_num_tlb_entries; 225 extern u_int mips_L1DCacheSize; 226 extern u_int mips_L1ICacheSize; 227 extern u_int mips_L1DCacheLSize; 228 extern u_int mips_L1ICacheLSize; 229 extern int mips_L2CachePresent; 230 extern u_int mips_L2CacheLSize; 231 extern u_int mips_CacheAliasMask; 232 233 #ifdef MIPS3 234 extern int mips3_L1TwoWayCache; 235 extern int mips3_cacheflush_bug; 236 #endif /* MIPS3 */ 237 238 /* 239 * trapframe argument passed to trap() 240 */ 241 struct trapframe { 242 mips_reg_t tf_regs[17]; 243 mips_reg_t tf_ra; 244 mips_reg_t tf_sr; 245 mips_reg_t tf_mullo; 246 mips_reg_t tf_mulhi; 247 mips_reg_t tf_epc; /* may be changed by trap() call */ 248 }; 249 250 /* 251 * Stack frame for kernel traps. four args passed in registers. 252 * A trapframe is pointed to by the 5th arg, and a dummy sixth argument 253 * is used to avoid alignment problems 254 */ 255 256 struct kernframe { 257 register_t cf_args[4 + 1]; 258 register_t cf_pad; /* (for 8 word alignment) */ 259 register_t cf_sp; 260 register_t cf_ra; 261 struct trapframe cf_frame; 262 }; 263 264 #endif 265 266 #endif /* _MIPS_LOCORE_H */ 267
Indexes created Sun Oct 19 02:09:48 GMT 2025