locore.h revision 1.37
1 /* $NetBSD: locore.h,v 1.37 2000/06/26 02:55:45 nisimura Exp $ */ 2 3 /* 4 * Copyright 1996 The Board of Trustees of The Leland Stanford 5 * Junior University. All Rights Reserved. 6 * 7 * Permission to use, copy, modify, and distribute this 8 * software and its documentation for any purpose and without 9 * fee is hereby granted, provided that the above copyright 10 * notice appear in all copies. Stanford University 11 * makes no representations about the suitability of this 12 * software for any purpose. It is provided "as is" without 13 * express or implied warranty. 14 */ 15 16 /* 17 * Jump table for MIPS cpu locore functions that are implemented 18 * differently on different generations, or instruction-level 19 * archtecture (ISA) level, the Mips family. 20 * The following functions must be provided for each mips ISA level: 21 * 22 * 23 * MachFlushCache 24 * MachFlushDCache 25 * MachFlushICache 26 * wbflush 27 * proc_trampoline() 28 * cpu_switch_resume() 29 * 30 * We currently provide support for MIPS I and MIPS III. 31 */ 32 33 #ifndef _MIPS_LOCORE_H 34 #define _MIPS_LOCORE_H 35 36 #ifndef _LKM 37 #include "opt_cputype.h" 38 #include "opt_mips_cache.h" 39 #endif 40 41 /* 42 * locore service routine for exception vectors. Used outside locore 43 * only to print them by name in stack tracebacks 44 */ 45 46 u_int32_t mips_read_causereg __P((void)); 47 u_int32_t mips_read_statusreg __P((void)); 48 49 void mips1_ConfigCache __P((void)); 50 void mips1_FlushCache __P((void)); 51 void mips1_FlushDCache __P((vaddr_t addr, vsize_t len)); 52 void mips1_FlushICache __P((vaddr_t addr, vsize_t len)); 53 54 void mips1_SetPID __P((int pid)); 55 void mips1_TBIA __P((int)); 56 void mips1_TBIAP __P((int)); 57 void mips1_TBIS __P((vaddr_t)); 58 int mips1_TLBUpdate __P((u_int, u_int)); 59 60 void mips1_wbflush __P((void)); 61 void mips1_proc_trampoline __P((void)); 62 void mips1_cpu_switch_resume __P((void)); 63 64 void mips3_ConfigCache __P((void)); 65 void mips3_FlushCache __P((void)); 66 void mips3_FlushDCache __P((vaddr_t addr, vaddr_t len)); 67 void mips3_FlushICache __P((vaddr_t addr, vaddr_t len)); 68 void mips3_HitFlushDCache __P((vaddr_t, int)); 69 70 void mips3_SetPID __P((int pid)); 71 void mips3_TBIA __P((int)); 72 void mips3_TBIAP __P((int)); 73 void mips3_TBIS __P((vaddr_t)); 74 int mips3_TLBUpdate __P((u_int, u_int)); 75 struct tlb; 76 void mips3_TLBRead __P((int, struct tlb *)); 77 void mips3_SetWIRED __P((int)); 78 void mips3_wbflush __P((void)); 79 void mips3_proc_trampoline __P((void)); 80 void mips3_cpu_switch_resume __P((void)); 81 82 void mips3_FlushCache_2way __P((void)); 83 void mips3_FlushDCache_2way __P((vaddr_t addr, vaddr_t len)); 84 void mips3_HitFlushDCache_2way __P((vaddr_t, int)); 85 void mips3_FlushICache_2way __P((vaddr_t addr, vaddr_t len)); 86 87 u_int32_t mips3_read_config __P((void)); 88 u_int32_t mips3_cycle_count __P((void)); 89 u_int32_t mips3_write_count __P((u_int32_t)); 90 u_int32_t mips3_read_compare __P((void)); 91 void mips3_write_config __P((u_int32_t)); 92 void mips3_write_compare __P((u_int32_t)); 93 void mips3_write_xcontext_upper __P((u_int32_t)); 94 void mips3_clearBEV __P((void)); 95 96 /* 97 * A vector with an entry for each mips-ISA-level dependent 98 * locore function, and macros which jump through it. 99 * XXX the macro names are chosen to be compatible with the old 100 * Sprite coding-convention names used in 4.4bsd/pmax. 101 */ 102 typedef struct { 103 void (*flushCache) __P((void)); 104 void (*flushDCache) __P((vaddr_t addr, vsize_t len)); 105 void (*flushICache) __P((vaddr_t addr, vsize_t len)); 106 void (*setTLBpid) __P((int pid)); 107 void (*TBIAP) __P((int)); 108 void (*TBIS) __P((vaddr_t)); 109 int (*tlbUpdate) __P((u_int highreg, u_int lowreg)); 110 void (*wbflush) __P((void)); 111 } mips_locore_jumpvec_t; 112 113 /* Override writebuffer-drain method. */ 114 void mips_set_wbflush __P((void (*) __P((void)) )); 115 116 117 /* stacktrace() -- print a stack backtrace to the console */ 118 void stacktrace __P((void)); 119 /* logstacktrace() -- log a stack traceback to msgbuf */ 120 void logstacktrace __P((void)); 121 122 /* 123 * The "active" locore-fuction vector, and 124 125 */ 126 extern mips_locore_jumpvec_t mips_locore_jumpvec; 127 extern mips_locore_jumpvec_t r2000_locore_vec; 128 extern mips_locore_jumpvec_t r4000_locore_vec; 129 extern long *mips_locoresw[]; 130 131 #if defined(MIPS3) && !defined (MIPS1) 132 #if defined(MIPS3_5200) 133 #define MachFlushCache mips3_FlushCache_2way 134 #define MachFlushDCache mips3_FlushDCache_2way 135 #define MachHitFlushDCache mips3_HitFlushDCache_2way 136 #define MachFlushICache mips3_FlushICache_2way 137 #else 138 #define MachFlushCache mips3_FlushCache 139 #if defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_4100) 140 #define MachFlushDCache mips3_FlushDCache /* VR4100 */ 141 #elif !defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_L2CACHE_PRESENT) 142 #define MachFlushDCache mips3_FlushDCache 143 #else 144 #define MachFlushDCache (*(mips_locore_jumpvec.flushDCache)) 145 #endif 146 #define MachHitFlushDCache mips3_HitFlushDCache 147 #define MachFlushICache mips3_FlushICache 148 #endif 149 #define MachSetPID mips3_SetPID 150 #define MIPS_TBIAP() mips3_TBIAP(mips_num_tlb_entries) 151 #define MIPS_TBIS mips3_TBIS 152 #define MachTLBUpdate mips3_TLBUpdate 153 #define wbflush() mips3_wbflush() 154 #define proc_trampoline mips3_proc_trampoline 155 #endif 156 157 #if !defined(MIPS3) && defined (MIPS1) 158 #define MachFlushCache mips1_FlushCache 159 #define MachFlushDCache mips1_FlushDCache 160 #define MachFlushICache mips1_FlushICache 161 #define MachSetPID mips1_SetPID 162 #define MIPS_TBIAP() mips1_TBIAP(mips_num_tlb_entries) 163 #define MIPS_TBIS mips1_TBIS 164 #define MachTLBUpdate mips1_TLBUpdate 165 #define wbflush() mips1_wbflush() 166 #define proc_trampoline mips1_proc_trampoline 167 #endif 168 169 170 171 #if defined(MIPS3) && defined (MIPS1) 172 #define MachFlushCache (*(mips_locore_jumpvec.flushCache)) 173 #define MachFlushDCache (*(mips_locore_jumpvec.flushDCache)) 174 #define MachFlushICache (*(mips_locore_jumpvec.flushICache)) 175 #define MachSetPID (*(mips_locore_jumpvec.setTLBpid)) 176 #define MIPS_TBIAP() (*(mips_locore_jumpvec.TBIAP))(mips_num_tlb_entries) 177 #define MIPS_TBIS (*(mips_locore_jumpvec.TBIS)) 178 #define MachTLBUpdate (*(mips_locore_jumpvec.tlbUpdate)) 179 #define MachHitFlushDCache mips3_HitFlushDCache 180 #define wbflush() (*(mips_locore_jumpvec.wbflush))() 181 #define proc_trampoline (mips_locoresw[1]) 182 #endif 183 184 #define CPU_IDLE (mips_locoresw[2]) 185 186 /* cpu_switch_resume is called inside locore.S */ 187 188 /* 189 * CPU identification, from PRID register. 190 */ 191 union cpuprid { 192 int cpuprid; 193 struct { 194 #if BYTE_ORDER == BIG_ENDIAN 195 u_int pad1:16; /* reserved */ 196 u_int cp_imp:8; /* implementation identifier */ 197 u_int cp_majrev:4; /* major revision identifier */ 198 u_int cp_minrev:4; /* minor revision identifier */ 199 #else 200 u_int cp_minrev:4; /* minor revision identifier */ 201 u_int cp_majrev:4; /* major revision identifier */ 202 u_int cp_imp:8; /* implementation identifier */ 203 u_int pad1:16; /* reserved */ 204 #endif 205 } cpu; 206 }; 207 208 209 #ifdef _KERNEL 210 211 /* 212 * Global variables used to communicate CPU type, and parameters 213 * such as cache size, from locore to higher-level code (e.g., pmap). 214 */ 215 extern union cpuprid cpu_id; 216 extern union cpuprid fpu_id; 217 extern int cpu_arch; 218 extern int mips_num_tlb_entries; 219 extern u_int mips_L1DCacheSize; 220 extern u_int mips_L1ICacheSize; 221 extern u_int mips_L1DCacheLSize; 222 extern u_int mips_L1ICacheLSize; 223 extern int mips_L2CachePresent; 224 extern u_int mips_L2CacheLSize; 225 extern u_int mips_CacheAliasMask; 226 227 #ifdef MIPS3 228 extern int mips3_L1TwoWayCache; 229 extern int mips3_cacheflush_bug; 230 #endif /* MIPS3 */ 231 232 /* 233 * trapframe argument passed to trap() 234 */ 235 struct trapframe { 236 mips_reg_t tf_regs[17]; 237 mips_reg_t tf_ra; 238 mips_reg_t tf_sr; 239 mips_reg_t tf_mullo; 240 mips_reg_t tf_mulhi; 241 mips_reg_t tf_epc; /* may be changed by trap() call */ 242 }; 243 244 /* 245 * Stack frame for kernel traps. four args passed in registers. 246 * A trapframe is pointed to by the 5th arg, and a dummy sixth argument 247 * is used to avoid alignment problems 248 */ 249 250 struct kernframe { 251 register_t cf_args[4 + 1]; 252 register_t cf_pad; /* (for 8 word alignment) */ 253 register_t cf_sp; 254 register_t cf_ra; 255 struct trapframe cf_frame; 256 }; 257 258 #endif 259 260 #endif /* _MIPS_LOCORE_H */ 261
Indexes created Wed Oct 22 06:10:02 GMT 2025