locore.h revision 1.42
1 /* $NetBSD: locore.h,v 1.42 2000/09/16 00:04:57 chuck Exp $ */ 2 3 /* 4 * Copyright 1996 The Board of Trustees of The Leland Stanford 5 * Junior University. All Rights Reserved. 6 * 7 * Permission to use, copy, modify, and distribute this 8 * software and its documentation for any purpose and without 9 * fee is hereby granted, provided that the above copyright 10 * notice appear in all copies. Stanford University 11 * makes no representations about the suitability of this 12 * software for any purpose. It is provided "as is" without 13 * express or implied warranty. 14 */ 15 16 /* 17 * Jump table for MIPS cpu locore functions that are implemented 18 * differently on different generations, or instruction-level 19 * archtecture (ISA) level, the Mips family. 20 * The following functions must be provided for each mips ISA level: 21 * 22 * 23 * MachFlushCache 24 * MachFlushDCache 25 * MachFlushICache 26 * wbflush 27 * proc_trampoline() 28 * cpu_switch_resume() 29 * 30 * We currently provide support for MIPS I and MIPS III. 31 */ 32 33 #ifndef _MIPS_LOCORE_H 34 #define _MIPS_LOCORE_H 35 36 #ifndef _LKM 37 #include "opt_cputype.h" 38 #include "opt_mips_cache.h" 39 #endif 40 41 struct tlb; 42 43 /* 44 * locore service routine for exception vectors. Used outside locore 45 * only to print them by name in stack tracebacks 46 */ 47 48 u_int32_t mips_read_causereg(void); 49 u_int32_t mips_read_statusreg(void); 50 51 void mips1_ConfigCache(void); 52 void mips1_FlushCache(void); 53 void mips1_FlushDCache(vaddr_t addr, vsize_t len); 54 void mips1_FlushICache(vaddr_t addr, vsize_t len); 55 56 void mips1_SetPID(int pid); 57 void mips1_TBIA(int); 58 void mips1_TBIAP(int); 59 void mips1_TBIS(vaddr_t); 60 int mips1_TLBUpdate(u_int, u_int); 61 void mips1_wbflush(void); 62 void mips1_proc_trampoline(void); 63 void mips1_cpu_switch_resume(void); 64 65 void mips3_ConfigCache(int); 66 void mips3_FlushCache(void); 67 void mips3_FlushDCache(vaddr_t addr, vaddr_t len); 68 void mips3_FlushICache(vaddr_t addr, vaddr_t len); 69 void mips3_HitFlushDCache(vaddr_t, int); 70 71 void mips3_SetPID(int pid); 72 void mips3_TBIA(int); 73 void mips3_TBIAP(int); 74 void mips3_TBIS(vaddr_t); 75 int mips3_TLBUpdate(u_int, u_int); 76 void mips3_TLBRead(int, struct tlb *); 77 void mips3_SetWIRED(int); 78 void mips3_wbflush(void); 79 void mips3_proc_trampoline(void); 80 void mips3_cpu_switch_resume(void); 81 82 void mips3_FlushCache_2way(void); 83 void mips3_FlushDCache_2way(vaddr_t addr, vaddr_t len); 84 void mips3_HitFlushDCache_2way(vaddr_t, int); 85 void mips3_FlushICache_2way(vaddr_t addr, vaddr_t len); 86 87 u_int32_t mips3_read_config(void); 88 u_int32_t mips3_cycle_count(void); 89 u_int32_t mips3_write_count(u_int32_t); 90 u_int32_t mips3_read_compare(void); 91 void mips3_write_config(u_int32_t); 92 void mips3_write_compare(u_int32_t); 93 void mips3_clearBEV(void); 94 95 /* 96 * A vector with an entry for each mips-ISA-level dependent 97 * locore function, and macros which jump through it. 98 * XXX the macro names are chosen to be compatible with the old 99 * Sprite coding-convention names used in 4.4bsd/pmax. 100 */ 101 typedef struct { 102 void (*flushCache)(void); 103 void (*flushDCache)(vaddr_t addr, vsize_t len); 104 void (*flushICache)(vaddr_t addr, vsize_t len); 105 void (*setTLBpid)(int pid); 106 void (*TBIAP)(int); 107 void (*TBIS)(vaddr_t); 108 int (*tlbUpdate)(u_int highreg, u_int lowreg); 109 void (*wbflush)(void); 110 } mips_locore_jumpvec_t; 111 112 /* Override writebuffer-drain method. */ 113 void mips_set_wbflush(void (*)(void)); 114 115 116 /* stacktrace() -- print a stack backtrace to the console */ 117 void stacktrace(void); 118 /* logstacktrace() -- log a stack traceback to msgbuf */ 119 void logstacktrace(void); 120 121 /* 122 * The "active" locore-fuction vector, and 123 124 */ 125 extern mips_locore_jumpvec_t mips_locore_jumpvec; 126 extern mips_locore_jumpvec_t r2000_locore_vec; 127 extern mips_locore_jumpvec_t r4000_locore_vec; 128 extern long *mips_locoresw[]; 129 130 #if defined(MIPS3) && !defined (MIPS1) 131 #if defined(MIPS3_5200) 132 #define MachFlushCache mips3_FlushCache_2way 133 #define MachFlushDCache mips3_FlushDCache_2way 134 #define MachHitFlushDCache mips3_HitFlushDCache_2way 135 #define MachFlushICache mips3_FlushICache_2way 136 #else 137 #define MachFlushCache mips3_FlushCache 138 #if defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_4100) 139 #define MachFlushDCache mips3_FlushDCache /* VR4100 */ 140 #elif !defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_L2CACHE_PRESENT) 141 #define MachFlushDCache mips3_FlushDCache 142 #else 143 #define MachFlushDCache (*(mips_locore_jumpvec.flushDCache)) 144 #endif 145 #define MachHitFlushDCache mips3_HitFlushDCache 146 #define MachFlushICache mips3_FlushICache 147 #endif 148 #define MachSetPID mips3_SetPID 149 #define MIPS_TBIAP() mips3_TBIAP(mips_num_tlb_entries) 150 #define MIPS_TBIS mips3_TBIS 151 #define MachTLBUpdate mips3_TLBUpdate 152 #define wbflush() mips3_wbflush() 153 #define proc_trampoline mips3_proc_trampoline 154 #endif 155 156 #if !defined(MIPS3) && defined (MIPS1) 157 #define MachFlushCache mips1_FlushCache 158 #define MachFlushDCache mips1_FlushDCache 159 #define MachFlushICache mips1_FlushICache 160 #define MachSetPID mips1_SetPID 161 #define MIPS_TBIAP() mips1_TBIAP(mips_num_tlb_entries) 162 #define MIPS_TBIS mips1_TBIS 163 #define MachTLBUpdate mips1_TLBUpdate 164 #define wbflush() mips1_wbflush() 165 #define proc_trampoline mips1_proc_trampoline 166 #endif 167 168 169 170 #if defined(MIPS3) && defined (MIPS1) 171 #define MachFlushCache (*(mips_locore_jumpvec.flushCache)) 172 #define MachFlushDCache (*(mips_locore_jumpvec.flushDCache)) 173 #define MachFlushICache (*(mips_locore_jumpvec.flushICache)) 174 #define MachSetPID (*(mips_locore_jumpvec.setTLBpid)) 175 #define MIPS_TBIAP() (*(mips_locore_jumpvec.TBIAP))(mips_num_tlb_entries) 176 #define MIPS_TBIS (*(mips_locore_jumpvec.TBIS)) 177 #define MachTLBUpdate (*(mips_locore_jumpvec.tlbUpdate)) 178 #define MachHitFlushDCache mips3_HitFlushDCache 179 #define wbflush() (*(mips_locore_jumpvec.wbflush))() 180 #define proc_trampoline (mips_locoresw[1]) 181 #endif 182 183 #define CPU_IDLE (mips_locoresw[2]) 184 185 /* cpu_switch_resume is called inside locore.S */ 186 187 /* 188 * CPU identification, from PRID register. 189 */ 190 typedef int mips_prid_t; 191 192 #define MIPS_PRID_REV(x) (((x) >> 0) & 0x00ff) 193 #define MIPS_PRID_IMPL(x) (((x) >> 8) & 0x00ff) 194 #define MIPS_PRID_RSVD(x) (((x) >> 16) & 0xffff) 195 196 #define MIPS_PRID_REV_MIN(x) ((MIPS_PRID_REV(x) >> 0) & 0x0f) 197 #define MIPS_PRID_REV_MAJ(x) ((MIPS_PRID_REV(x) >> 4) & 0x0f) 198 199 #ifdef _KERNEL 200 201 /* 202 * Global variables used to communicate CPU type, and parameters 203 * such as cache size, from locore to higher-level code (e.g., pmap). 204 */ 205 206 extern mips_prid_t cpu_id; 207 extern mips_prid_t fpu_id; 208 extern int cpu_arch; 209 extern int mips_num_tlb_entries; 210 extern u_int mips_L1DCacheSize; 211 extern u_int mips_L1ICacheSize; 212 extern u_int mips_L1DCacheLSize; 213 extern u_int mips_L1ICacheLSize; 214 extern int mips_L2CachePresent; 215 extern u_int mips_L2CacheLSize; 216 extern u_int mips_CacheAliasMask; 217 extern u_int mips_CachePreferMask; 218 219 #ifdef MIPS3 220 extern int mips3_L1TwoWayCache; 221 extern int mips3_cacheflush_bug; 222 #endif /* MIPS3 */ 223 224 /* 225 * trapframe argument passed to trap() 226 */ 227 struct trapframe { 228 mips_reg_t tf_regs[17]; 229 mips_reg_t tf_ra; 230 mips_reg_t tf_sr; 231 mips_reg_t tf_mullo; 232 mips_reg_t tf_mulhi; 233 mips_reg_t tf_epc; /* may be changed by trap() call */ 234 }; 235 236 /* 237 * Stack frame for kernel traps. four args passed in registers. 238 * A trapframe is pointed to by the 5th arg, and a dummy sixth argument 239 * is used to avoid alignment problems 240 */ 241 242 struct kernframe { 243 register_t cf_args[4 + 1]; 244 register_t cf_pad; /* (for 8 word alignment) */ 245 register_t cf_sp; 246 register_t cf_ra; 247 struct trapframe cf_frame; 248 }; 249 250 #endif 251 252 #endif /* _MIPS_LOCORE_H */ 253
Indexes created Tue Sep 30 11:09:46 GMT 2025