locore.h revision 1.43
1 /* $NetBSD: locore.h,v 1.43 2000/09/16 07:20:17 nisimura Exp $ */ 2 3 /* 4 * Copyright 1996 The Board of Trustees of The Leland Stanford 5 * Junior University. All Rights Reserved. 6 * 7 * Permission to use, copy, modify, and distribute this 8 * software and its documentation for any purpose and without 9 * fee is hereby granted, provided that the above copyright 10 * notice appear in all copies. Stanford University 11 * makes no representations about the suitability of this 12 * software for any purpose. It is provided "as is" without 13 * express or implied warranty. 14 */ 15 16 /* 17 * Jump table for MIPS cpu locore functions that are implemented 18 * differently on different generations, or instruction-level 19 * archtecture (ISA) level, the Mips family. 20 * The following functions must be provided for each mips ISA level: 21 * 22 * 23 * MachFlushCache 24 * MachFlushDCache 25 * MachFlushICache 26 * wbflush 27 * proc_trampoline() 28 * cpu_switch_resume() 29 * 30 * We currently provide support for MIPS I and MIPS III. 31 */ 32 33 #ifndef _MIPS_LOCORE_H 34 #define _MIPS_LOCORE_H 35 36 #ifndef _LKM 37 #include "opt_cputype.h" 38 #include "opt_mips_cache.h" 39 #endif 40 41 struct tlb; 42 43 /* 44 * locore service routine for exception vectors. Used outside locore 45 * only to print them by name in stack tracebacks 46 */ 47 48 u_int32_t mips_read_causereg(void); 49 u_int32_t mips_read_statusreg(void); 50 51 int mips1_icsize(void); 52 int mips1_dcsize(void); 53 void mips1_ConfigCache(void); /* XXX TX3900 XXX */ 54 void mips1_FlushCache(void); 55 void mips1_FlushDCache(vaddr_t addr, vsize_t len); 56 void mips1_FlushICache(vaddr_t addr, vsize_t len); 57 58 void mips1_SetPID(int pid); 59 void mips1_TBIA(int); 60 void mips1_TBIAP(int); 61 void mips1_TBIS(vaddr_t); 62 int mips1_TLBUpdate(u_int, u_int); 63 void mips1_wbflush(void); 64 void mips1_proc_trampoline(void); 65 void mips1_cpu_switch_resume(void); 66 67 void mips3_ConfigCache(int); 68 void mips3_FlushCache(void); 69 void mips3_FlushDCache(vaddr_t addr, vaddr_t len); 70 void mips3_FlushICache(vaddr_t addr, vaddr_t len); 71 void mips3_HitFlushDCache(vaddr_t, int); 72 73 void mips3_SetPID(int pid); 74 void mips3_TBIA(int); 75 void mips3_TBIAP(int); 76 void mips3_TBIS(vaddr_t); 77 int mips3_TLBUpdate(u_int, u_int); 78 void mips3_TLBRead(int, struct tlb *); 79 void mips3_SetWIRED(int); 80 void mips3_wbflush(void); 81 void mips3_proc_trampoline(void); 82 void mips3_cpu_switch_resume(void); 83 84 void mips3_FlushCache_2way(void); 85 void mips3_FlushDCache_2way(vaddr_t addr, vaddr_t len); 86 void mips3_HitFlushDCache_2way(vaddr_t, int); 87 void mips3_FlushICache_2way(vaddr_t addr, vaddr_t len); 88 89 u_int32_t mips3_read_config(void); 90 u_int32_t mips3_cycle_count(void); 91 u_int32_t mips3_write_count(u_int32_t); 92 u_int32_t mips3_read_compare(void); 93 void mips3_write_config(u_int32_t); 94 void mips3_write_compare(u_int32_t); 95 void mips3_clearBEV(void); 96 97 /* 98 * A vector with an entry for each mips-ISA-level dependent 99 * locore function, and macros which jump through it. 100 * XXX the macro names are chosen to be compatible with the old 101 * Sprite coding-convention names used in 4.4bsd/pmax. 102 */ 103 typedef struct { 104 void (*flushCache)(void); 105 void (*flushDCache)(vaddr_t addr, vsize_t len); 106 void (*flushICache)(vaddr_t addr, vsize_t len); 107 void (*setTLBpid)(int pid); 108 void (*TBIAP)(int); 109 void (*TBIS)(vaddr_t); 110 int (*tlbUpdate)(u_int highreg, u_int lowreg); 111 void (*wbflush)(void); 112 } mips_locore_jumpvec_t; 113 114 /* Override writebuffer-drain method. */ 115 void mips_set_wbflush(void (*)(void)); 116 117 118 /* stacktrace() -- print a stack backtrace to the console */ 119 void stacktrace(void); 120 /* logstacktrace() -- log a stack traceback to msgbuf */ 121 void logstacktrace(void); 122 123 /* 124 * The "active" locore-fuction vector, and 125 126 */ 127 extern mips_locore_jumpvec_t mips_locore_jumpvec; 128 extern mips_locore_jumpvec_t r2000_locore_vec; 129 extern mips_locore_jumpvec_t r4000_locore_vec; 130 extern long *mips_locoresw[]; 131 132 #if defined(MIPS3) && !defined (MIPS1) 133 #if defined(MIPS3_5200) 134 #define MachFlushCache mips3_FlushCache_2way 135 #define MachFlushDCache mips3_FlushDCache_2way 136 #define MachHitFlushDCache mips3_HitFlushDCache_2way 137 #define MachFlushICache mips3_FlushICache_2way 138 #else 139 #define MachFlushCache mips3_FlushCache 140 #if defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_4100) 141 #define MachFlushDCache mips3_FlushDCache /* VR4100 */ 142 #elif !defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_L2CACHE_PRESENT) 143 #define MachFlushDCache mips3_FlushDCache 144 #else 145 #define MachFlushDCache (*(mips_locore_jumpvec.flushDCache)) 146 #endif 147 #define MachHitFlushDCache mips3_HitFlushDCache 148 #define MachFlushICache mips3_FlushICache 149 #endif 150 #define MachSetPID mips3_SetPID 151 #define MIPS_TBIAP() mips3_TBIAP(mips_num_tlb_entries) 152 #define MIPS_TBIS mips3_TBIS 153 #define MachTLBUpdate mips3_TLBUpdate 154 #define wbflush() mips3_wbflush() 155 #define proc_trampoline mips3_proc_trampoline 156 #endif 157 158 #if !defined(MIPS3) && defined (MIPS1) 159 #define MachFlushCache mips1_FlushCache 160 #define MachFlushDCache mips1_FlushDCache 161 #define MachFlushICache mips1_FlushICache 162 #define MachSetPID mips1_SetPID 163 #define MIPS_TBIAP() mips1_TBIAP(mips_num_tlb_entries) 164 #define MIPS_TBIS mips1_TBIS 165 #define MachTLBUpdate mips1_TLBUpdate 166 #define wbflush() mips1_wbflush() 167 #define proc_trampoline mips1_proc_trampoline 168 #endif 169 170 171 172 #if defined(MIPS3) && defined (MIPS1) 173 #define MachFlushCache (*(mips_locore_jumpvec.flushCache)) 174 #define MachFlushDCache (*(mips_locore_jumpvec.flushDCache)) 175 #define MachFlushICache (*(mips_locore_jumpvec.flushICache)) 176 #define MachSetPID (*(mips_locore_jumpvec.setTLBpid)) 177 #define MIPS_TBIAP() (*(mips_locore_jumpvec.TBIAP))(mips_num_tlb_entries) 178 #define MIPS_TBIS (*(mips_locore_jumpvec.TBIS)) 179 #define MachTLBUpdate (*(mips_locore_jumpvec.tlbUpdate)) 180 #define MachHitFlushDCache mips3_HitFlushDCache 181 #define wbflush() (*(mips_locore_jumpvec.wbflush))() 182 #define proc_trampoline (mips_locoresw[1]) 183 #endif 184 185 #define CPU_IDLE (mips_locoresw[2]) 186 187 /* cpu_switch_resume is called inside locore.S */ 188 189 /* 190 * CPU identification, from PRID register. 191 */ 192 typedef int mips_prid_t; 193 194 #define MIPS_PRID_REV(x) (((x) >> 0) & 0x00ff) 195 #define MIPS_PRID_IMPL(x) (((x) >> 8) & 0x00ff) 196 #define MIPS_PRID_RSVD(x) (((x) >> 16) & 0xffff) 197 198 #define MIPS_PRID_REV_MIN(x) ((MIPS_PRID_REV(x) >> 0) & 0x0f) 199 #define MIPS_PRID_REV_MAJ(x) ((MIPS_PRID_REV(x) >> 4) & 0x0f) 200 201 #ifdef _KERNEL 202 203 /* 204 * Global variables used to communicate CPU type, and parameters 205 * such as cache size, from locore to higher-level code (e.g., pmap). 206 */ 207 208 extern mips_prid_t cpu_id; 209 extern mips_prid_t fpu_id; 210 extern int cpu_arch; 211 extern int mips_num_tlb_entries; 212 extern u_int mips_L1DCacheSize; 213 extern u_int mips_L1ICacheSize; 214 extern u_int mips_L1DCacheLSize; 215 extern u_int mips_L1ICacheLSize; 216 extern int mips_L2CachePresent; 217 extern u_int mips_L2CacheLSize; 218 extern u_int mips_CacheAliasMask; 219 extern u_int mips_CachePreferMask; 220 221 #ifdef MIPS3 222 extern int mips3_L1TwoWayCache; 223 extern int mips3_cacheflush_bug; 224 #endif /* MIPS3 */ 225 226 /* 227 * trapframe argument passed to trap() 228 */ 229 struct trapframe { 230 mips_reg_t tf_regs[17]; 231 mips_reg_t tf_ra; 232 mips_reg_t tf_sr; 233 mips_reg_t tf_mullo; 234 mips_reg_t tf_mulhi; 235 mips_reg_t tf_epc; /* may be changed by trap() call */ 236 }; 237 238 /* 239 * Stack frame for kernel traps. four args passed in registers. 240 * A trapframe is pointed to by the 5th arg, and a dummy sixth argument 241 * is used to avoid alignment problems 242 */ 243 244 struct kernframe { 245 register_t cf_args[4 + 1]; 246 register_t cf_pad; /* (for 8 word alignment) */ 247 register_t cf_sp; 248 register_t cf_ra; 249 struct trapframe cf_frame; 250 }; 251 252 #endif 253 254 #endif /* _MIPS_LOCORE_H */ 255
Indexes created Tue Sep 30 07:10:03 GMT 2025