locore.h revision 1.46
1 /* $NetBSD: locore.h,v 1.46 2000/10/04 22:44:01 cgd Exp $ */ 2 3 /* 4 * Copyright 1996 The Board of Trustees of The Leland Stanford 5 * Junior University. All Rights Reserved. 6 * 7 * Permission to use, copy, modify, and distribute this 8 * software and its documentation for any purpose and without 9 * fee is hereby granted, provided that the above copyright 10 * notice appear in all copies. Stanford University 11 * makes no representations about the suitability of this 12 * software for any purpose. It is provided "as is" without 13 * express or implied warranty. 14 */ 15 16 /* 17 * Jump table for MIPS cpu locore functions that are implemented 18 * differently on different generations, or instruction-level 19 * archtecture (ISA) level, the Mips family. 20 * The following functions must be provided for each mips ISA level: 21 * 22 * 23 * MachFlushCache 24 * MachFlushDCache 25 * MachFlushICache 26 * wbflush 27 * proc_trampoline() 28 * cpu_switch_resume() 29 * 30 * We currently provide support for MIPS I and MIPS III. 31 */ 32 33 #ifndef _MIPS_LOCORE_H 34 #define _MIPS_LOCORE_H 35 36 #ifndef _LKM 37 #include "opt_cputype.h" 38 #include "opt_mips_cache.h" 39 #endif 40 41 struct tlb; 42 43 /* 44 * locore service routine for exception vectors. Used outside locore 45 * only to print them by name in stack tracebacks 46 */ 47 48 u_int32_t mips_cp0_cause_read(void); 49 void mips_cp0_cause_write(u_int32_t); 50 u_int32_t mips_cp0_status_read(void); 51 void mips_cp0_status_write(u_int32_t); 52 53 int mips1_icsize(void); 54 int mips1_dcsize(void); 55 void mips1_ConfigCache(void); /* XXX TX3900 XXX */ 56 void mips1_FlushCache(void); 57 void mips1_FlushDCache(vaddr_t addr, vsize_t len); 58 void mips1_FlushICache(vaddr_t addr, vsize_t len); 59 60 void mips1_SetPID(int pid); 61 void mips1_TBIA(int); 62 void mips1_TBIAP(int); 63 void mips1_TBIS(vaddr_t); 64 int mips1_TLBUpdate(u_int, u_int); 65 void mips1_wbflush(void); 66 void mips1_proc_trampoline(void); 67 void mips1_cpu_switch_resume(void); 68 69 void mips3_ConfigCache(int); 70 void mips3_FlushCache(void); 71 void mips3_FlushDCache(vaddr_t addr, vaddr_t len); 72 void mips3_FlushICache(vaddr_t addr, vaddr_t len); 73 void mips3_HitFlushDCache(vaddr_t, int); 74 75 void mips3_SetPID(int pid); 76 void mips3_TBIA(int); 77 void mips3_TBIAP(int); 78 void mips3_TBIS(vaddr_t); 79 int mips3_TLBUpdate(u_int, u_int); 80 void mips3_TLBRead(int, struct tlb *); 81 void mips3_SetWIRED(int); 82 void mips3_wbflush(void); 83 void mips3_proc_trampoline(void); 84 void mips3_cpu_switch_resume(void); 85 86 void mips3_FlushCache_2way(void); 87 void mips3_FlushDCache_2way(vaddr_t addr, vaddr_t len); 88 void mips3_HitFlushDCache_2way(vaddr_t, int); 89 void mips3_FlushICache_2way(vaddr_t addr, vaddr_t len); 90 91 u_int32_t mips3_read_config(void); 92 u_int32_t mips3_cycle_count(void); 93 u_int32_t mips3_write_count(u_int32_t); 94 u_int32_t mips3_read_compare(void); 95 void mips3_write_config(u_int32_t); 96 void mips3_write_compare(u_int32_t); 97 void mips3_clearBEV(void); 98 99 u_int64_t mips3_ld(u_int64_t *); 100 void mips3_sd(u_int64_t *, u_int64_t); 101 102 /* 103 * A vector with an entry for each mips-ISA-level dependent 104 * locore function, and macros which jump through it. 105 * XXX the macro names are chosen to be compatible with the old 106 * Sprite coding-convention names used in 4.4bsd/pmax. 107 */ 108 typedef struct { 109 void (*flushCache)(void); 110 void (*flushDCache)(vaddr_t addr, vsize_t len); 111 void (*flushICache)(vaddr_t addr, vsize_t len); 112 void (*setTLBpid)(int pid); 113 void (*TBIAP)(int); 114 void (*TBIS)(vaddr_t); 115 int (*tlbUpdate)(u_int highreg, u_int lowreg); 116 void (*wbflush)(void); 117 } mips_locore_jumpvec_t; 118 119 /* Override writebuffer-drain method. */ 120 void mips_set_wbflush(void (*)(void)); 121 122 123 /* stacktrace() -- print a stack backtrace to the console */ 124 void stacktrace(void); 125 /* logstacktrace() -- log a stack traceback to msgbuf */ 126 void logstacktrace(void); 127 128 /* 129 * The "active" locore-fuction vector, and 130 131 */ 132 extern mips_locore_jumpvec_t mips_locore_jumpvec; 133 extern mips_locore_jumpvec_t r2000_locore_vec; 134 extern mips_locore_jumpvec_t r4000_locore_vec; 135 extern long *mips_locoresw[]; 136 137 #if defined(MIPS3) && !defined (MIPS1) 138 #if defined(MIPS3_5200) 139 #define MachFlushCache mips3_FlushCache_2way 140 #define MachFlushDCache mips3_FlushDCache_2way 141 #define MachHitFlushDCache mips3_HitFlushDCache_2way 142 #define MachFlushICache mips3_FlushICache_2way 143 #else 144 #define MachFlushCache mips3_FlushCache 145 #if defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_4100) 146 #define MachFlushDCache mips3_FlushDCache /* VR4100 */ 147 #elif !defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_L2CACHE_PRESENT) 148 #define MachFlushDCache mips3_FlushDCache 149 #else 150 #define MachFlushDCache (*(mips_locore_jumpvec.flushDCache)) 151 #endif 152 #define MachHitFlushDCache mips3_HitFlushDCache 153 #define MachFlushICache mips3_FlushICache 154 #endif 155 #define MachSetPID mips3_SetPID 156 #define MIPS_TBIAP() mips3_TBIAP(mips_num_tlb_entries) 157 #define MIPS_TBIS mips3_TBIS 158 #define MachTLBUpdate mips3_TLBUpdate 159 #define wbflush() mips3_wbflush() 160 #define proc_trampoline mips3_proc_trampoline 161 #endif 162 163 #if !defined(MIPS3) && defined (MIPS1) 164 #define MachFlushCache mips1_FlushCache 165 #define MachFlushDCache mips1_FlushDCache 166 #define MachFlushICache mips1_FlushICache 167 #define MachSetPID mips1_SetPID 168 #define MIPS_TBIAP() mips1_TBIAP(mips_num_tlb_entries) 169 #define MIPS_TBIS mips1_TBIS 170 #define MachTLBUpdate mips1_TLBUpdate 171 #define wbflush() mips1_wbflush() 172 #define proc_trampoline mips1_proc_trampoline 173 #endif 174 175 176 177 #if defined(MIPS3) && defined (MIPS1) 178 #define MachFlushCache (*(mips_locore_jumpvec.flushCache)) 179 #define MachFlushDCache (*(mips_locore_jumpvec.flushDCache)) 180 #define MachFlushICache (*(mips_locore_jumpvec.flushICache)) 181 #define MachSetPID (*(mips_locore_jumpvec.setTLBpid)) 182 #define MIPS_TBIAP() (*(mips_locore_jumpvec.TBIAP))(mips_num_tlb_entries) 183 #define MIPS_TBIS (*(mips_locore_jumpvec.TBIS)) 184 #define MachTLBUpdate (*(mips_locore_jumpvec.tlbUpdate)) 185 #define MachHitFlushDCache mips3_HitFlushDCache 186 #define wbflush() (*(mips_locore_jumpvec.wbflush))() 187 #define proc_trampoline (mips_locoresw[1]) 188 #endif 189 190 #define CPU_IDLE (mips_locoresw[2]) 191 192 /* cpu_switch_resume is called inside locore.S */ 193 194 /* 195 * CPU identification, from PRID register. 196 */ 197 typedef int mips_prid_t; 198 199 #define MIPS_PRID_REV(x) (((x) >> 0) & 0x00ff) 200 #define MIPS_PRID_IMPL(x) (((x) >> 8) & 0x00ff) 201 202 /* pre-MIPS32 */ 203 #define MIPS_PRID_RSVD(x) (((x) >> 16) & 0xffff) 204 #define MIPS_PRID_REV_MIN(x) ((MIPS_PRID_REV(x) >> 0) & 0x0f) 205 #define MIPS_PRID_REV_MAJ(x) ((MIPS_PRID_REV(x) >> 4) & 0x0f) 206 207 /* MIPS32 */ 208 #define MIPS_PRID_CID(x) (((x) >> 16) & 0x00ff) /* Company ID */ 209 #define MIPS_PRID_CID_PREHISTORIC 0x00 /* Not MIPS32 */ 210 #define MIPS_PRID_CID_MTI 0x01 /* MIPS Technologies, Inc. */ 211 212 #ifdef _KERNEL 213 214 /* 215 * Global variables used to communicate CPU type, and parameters 216 * such as cache size, from locore to higher-level code (e.g., pmap). 217 */ 218 219 extern mips_prid_t cpu_id; 220 extern mips_prid_t fpu_id; 221 extern int cpu_arch; 222 extern int mips_num_tlb_entries; 223 extern u_int mips_L1DCacheSize; 224 extern u_int mips_L1ICacheSize; 225 extern u_int mips_L1DCacheLSize; 226 extern u_int mips_L1ICacheLSize; 227 extern int mips_L2CachePresent; 228 extern u_int mips_L2CacheLSize; 229 extern u_int mips_CacheAliasMask; 230 extern u_int mips_CachePreferMask; 231 232 #ifdef MIPS3 233 extern int mips3_L1TwoWayCache; 234 extern int mips3_cacheflush_bug; 235 #endif /* MIPS3 */ 236 237 /* 238 * trapframe argument passed to trap() 239 */ 240 struct trapframe { 241 mips_reg_t tf_regs[17]; 242 mips_reg_t tf_ra; 243 mips_reg_t tf_sr; 244 mips_reg_t tf_mullo; 245 mips_reg_t tf_mulhi; 246 mips_reg_t tf_epc; /* may be changed by trap() call */ 247 }; 248 249 /* 250 * Stack frame for kernel traps. four args passed in registers. 251 * A trapframe is pointed to by the 5th arg, and a dummy sixth argument 252 * is used to avoid alignment problems 253 */ 254 255 struct kernframe { 256 register_t cf_args[4 + 1]; 257 register_t cf_pad; /* (for 8 word alignment) */ 258 register_t cf_sp; 259 register_t cf_ra; 260 struct trapframe cf_frame; 261 }; 262 263 #endif 264 265 #endif /* _MIPS_LOCORE_H */ 266
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