locore.h revision 1.49
1 /* $NetBSD: locore.h,v 1.49 2000/10/05 02:36:45 cgd Exp $ */ 2 3 /* 4 * Copyright 1996 The Board of Trustees of The Leland Stanford 5 * Junior University. All Rights Reserved. 6 * 7 * Permission to use, copy, modify, and distribute this 8 * software and its documentation for any purpose and without 9 * fee is hereby granted, provided that the above copyright 10 * notice appear in all copies. Stanford University 11 * makes no representations about the suitability of this 12 * software for any purpose. It is provided "as is" without 13 * express or implied warranty. 14 */ 15 16 /* 17 * Jump table for MIPS cpu locore functions that are implemented 18 * differently on different generations, or instruction-level 19 * archtecture (ISA) level, the Mips family. 20 * The following functions must be provided for each mips ISA level: 21 * 22 * 23 * MachFlushCache 24 * MachFlushDCache 25 * MachFlushICache 26 * wbflush 27 * proc_trampoline() 28 * cpu_switch_resume() 29 * 30 * We currently provide support for MIPS I and MIPS III. 31 */ 32 33 #ifndef _MIPS_LOCORE_H 34 #define _MIPS_LOCORE_H 35 36 #ifndef _LKM 37 #include "opt_cputype.h" 38 #include "opt_mips_cache.h" 39 #endif 40 41 struct tlb; 42 43 /* 44 * locore service routine for exception vectors. Used outside locore 45 * only to print them by name in stack tracebacks 46 */ 47 48 u_int32_t mips_cp0_cause_read(void); 49 void mips_cp0_cause_write(u_int32_t); 50 u_int32_t mips_cp0_status_read(void); 51 void mips_cp0_status_write(u_int32_t); 52 53 int mips1_icsize(void); 54 int mips1_dcsize(void); 55 void mips1_ConfigCache(void); /* XXX TX3900 XXX */ 56 void mips1_FlushCache(void); 57 void mips1_FlushDCache(vaddr_t addr, vsize_t len); 58 void mips1_FlushICache(vaddr_t addr, vsize_t len); 59 60 void mips1_SetPID(int pid); 61 void mips1_TBIA(int); 62 void mips1_TBIAP(int); 63 void mips1_TBIS(vaddr_t); 64 int mips1_TLBUpdate(u_int, u_int); 65 void mips1_wbflush(void); 66 void mips1_proc_trampoline(void); 67 void mips1_cpu_switch_resume(void); 68 69 void mips3_ConfigCache(int); 70 void mips3_FlushCache(void); 71 void mips3_FlushDCache(vaddr_t addr, vaddr_t len); 72 void mips3_FlushICache(vaddr_t addr, vaddr_t len); 73 void mips3_HitFlushDCache(vaddr_t, int); 74 75 void mips3_SetPID(int pid); 76 void mips3_TBIA(int); 77 void mips3_TBIAP(int); 78 void mips3_TBIS(vaddr_t); 79 int mips3_TLBUpdate(u_int, u_int); 80 void mips3_TLBRead(int, struct tlb *); 81 void mips3_wbflush(void); 82 void mips3_proc_trampoline(void); 83 void mips3_cpu_switch_resume(void); 84 85 void mips3_FlushCache_2way(void); 86 void mips3_FlushDCache_2way(vaddr_t addr, vaddr_t len); 87 void mips3_HitFlushDCache_2way(vaddr_t, int); 88 void mips3_FlushICache_2way(vaddr_t addr, vaddr_t len); 89 90 u_int32_t mips3_cp0_compare_read(void); 91 void mips3_cp0_compare_write(u_int32_t); 92 93 u_int32_t mips3_cp0_config_read(void); 94 void mips3_cp0_count_write(u_int32_t); 95 96 u_int32_t mips3_cp0_count_read(void); 97 void mips3_cp0_config_write(u_int32_t); 98 99 u_int32_t mips3_cp0_wired_read(void); 100 void mips3_cp0_wired_write(u_int32_t); 101 102 u_int64_t mips3_ld(u_int64_t *); 103 void mips3_sd(u_int64_t *, u_int64_t); 104 105 /* 106 * A vector with an entry for each mips-ISA-level dependent 107 * locore function, and macros which jump through it. 108 * XXX the macro names are chosen to be compatible with the old 109 * Sprite coding-convention names used in 4.4bsd/pmax. 110 */ 111 typedef struct { 112 void (*flushCache)(void); 113 void (*flushDCache)(vaddr_t addr, vsize_t len); 114 void (*flushICache)(vaddr_t addr, vsize_t len); 115 void (*setTLBpid)(int pid); 116 void (*TBIAP)(int); 117 void (*TBIS)(vaddr_t); 118 int (*tlbUpdate)(u_int highreg, u_int lowreg); 119 void (*wbflush)(void); 120 } mips_locore_jumpvec_t; 121 122 /* Override writebuffer-drain method. */ 123 void mips_set_wbflush(void (*)(void)); 124 125 126 /* stacktrace() -- print a stack backtrace to the console */ 127 void stacktrace(void); 128 /* logstacktrace() -- log a stack traceback to msgbuf */ 129 void logstacktrace(void); 130 131 /* 132 * The "active" locore-fuction vector, and 133 134 */ 135 extern mips_locore_jumpvec_t mips_locore_jumpvec; 136 extern mips_locore_jumpvec_t r2000_locore_vec; 137 extern mips_locore_jumpvec_t r4000_locore_vec; 138 extern long *mips_locoresw[]; 139 140 #if defined(MIPS3) && !defined (MIPS1) 141 #if defined(MIPS3_5200) 142 #define MachFlushCache mips3_FlushCache_2way 143 #define MachFlushDCache mips3_FlushDCache_2way 144 #define MachHitFlushDCache mips3_HitFlushDCache_2way 145 #define MachFlushICache mips3_FlushICache_2way 146 #else 147 #define MachFlushCache mips3_FlushCache 148 #if defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_4100) 149 #define MachFlushDCache mips3_FlushDCache /* VR4100 */ 150 #elif !defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_L2CACHE_PRESENT) 151 #define MachFlushDCache mips3_FlushDCache 152 #else 153 #define MachFlushDCache (*(mips_locore_jumpvec.flushDCache)) 154 #endif 155 #define MachHitFlushDCache mips3_HitFlushDCache 156 #define MachFlushICache mips3_FlushICache 157 #endif 158 #define MachSetPID mips3_SetPID 159 #define MIPS_TBIAP() mips3_TBIAP(mips_num_tlb_entries) 160 #define MIPS_TBIS mips3_TBIS 161 #define MachTLBUpdate mips3_TLBUpdate 162 #define wbflush() mips3_wbflush() 163 #define proc_trampoline mips3_proc_trampoline 164 #endif 165 166 #if !defined(MIPS3) && defined (MIPS1) 167 #define MachFlushCache mips1_FlushCache 168 #define MachFlushDCache mips1_FlushDCache 169 #define MachFlushICache mips1_FlushICache 170 #define MachSetPID mips1_SetPID 171 #define MIPS_TBIAP() mips1_TBIAP(mips_num_tlb_entries) 172 #define MIPS_TBIS mips1_TBIS 173 #define MachTLBUpdate mips1_TLBUpdate 174 #define wbflush() mips1_wbflush() 175 #define proc_trampoline mips1_proc_trampoline 176 #endif 177 178 179 180 #if defined(MIPS3) && defined (MIPS1) 181 #define MachFlushCache (*(mips_locore_jumpvec.flushCache)) 182 #define MachFlushDCache (*(mips_locore_jumpvec.flushDCache)) 183 #define MachFlushICache (*(mips_locore_jumpvec.flushICache)) 184 #define MachSetPID (*(mips_locore_jumpvec.setTLBpid)) 185 #define MIPS_TBIAP() (*(mips_locore_jumpvec.TBIAP))(mips_num_tlb_entries) 186 #define MIPS_TBIS (*(mips_locore_jumpvec.TBIS)) 187 #define MachTLBUpdate (*(mips_locore_jumpvec.tlbUpdate)) 188 #define MachHitFlushDCache mips3_HitFlushDCache 189 #define wbflush() (*(mips_locore_jumpvec.wbflush))() 190 #define proc_trampoline (mips_locoresw[1]) 191 #endif 192 193 #define CPU_IDLE (mips_locoresw[2]) 194 195 /* cpu_switch_resume is called inside locore.S */ 196 197 /* 198 * CPU identification, from PRID register. 199 */ 200 typedef int mips_prid_t; 201 202 #define MIPS_PRID_REV(x) (((x) >> 0) & 0x00ff) 203 #define MIPS_PRID_IMPL(x) (((x) >> 8) & 0x00ff) 204 205 /* pre-MIPS32 */ 206 #define MIPS_PRID_RSVD(x) (((x) >> 16) & 0xffff) 207 #define MIPS_PRID_REV_MIN(x) ((MIPS_PRID_REV(x) >> 0) & 0x0f) 208 #define MIPS_PRID_REV_MAJ(x) ((MIPS_PRID_REV(x) >> 4) & 0x0f) 209 210 /* MIPS32 */ 211 #define MIPS_PRID_CID(x) (((x) >> 16) & 0x00ff) /* Company ID */ 212 #define MIPS_PRID_CID_PREHISTORIC 0x00 /* Not MIPS32 */ 213 #define MIPS_PRID_CID_MTI 0x01 /* MIPS Technologies, Inc. */ 214 215 #ifdef _KERNEL 216 217 /* 218 * Global variables used to communicate CPU type, and parameters 219 * such as cache size, from locore to higher-level code (e.g., pmap). 220 */ 221 222 extern mips_prid_t cpu_id; 223 extern mips_prid_t fpu_id; 224 extern int mips_num_tlb_entries; 225 extern u_int mips_L1DCacheSize; 226 extern u_int mips_L1ICacheSize; 227 extern u_int mips_L1DCacheLSize; 228 extern u_int mips_L1ICacheLSize; 229 extern int mips_L2CachePresent; 230 extern u_int mips_L2CacheLSize; 231 extern u_int mips_CacheAliasMask; 232 extern u_int mips_CachePreferMask; 233 234 #ifdef MIPS3 235 extern int mips3_L1TwoWayCache; 236 extern int mips3_cacheflush_bug; 237 #endif /* MIPS3 */ 238 239 /* 240 * trapframe argument passed to trap() 241 */ 242 struct trapframe { 243 mips_reg_t tf_regs[17]; 244 mips_reg_t tf_ra; 245 mips_reg_t tf_sr; 246 mips_reg_t tf_mullo; 247 mips_reg_t tf_mulhi; 248 mips_reg_t tf_epc; /* may be changed by trap() call */ 249 }; 250 251 /* 252 * Stack frame for kernel traps. four args passed in registers. 253 * A trapframe is pointed to by the 5th arg, and a dummy sixth argument 254 * is used to avoid alignment problems 255 */ 256 257 struct kernframe { 258 register_t cf_args[4 + 1]; 259 register_t cf_pad; /* (for 8 word alignment) */ 260 register_t cf_sp; 261 register_t cf_ra; 262 struct trapframe cf_frame; 263 }; 264 265 #endif 266 267 #endif /* _MIPS_LOCORE_H */ 268
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