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locore.h revision 1.5 
      1 /*	$NetBSD: locore.h,v 1.5 1997/06/15 17:33:53 mhitch Exp $	*/
      2 
      3 /*
      4  * Copyright 1996 The Board of Trustees of The Leland Stanford
      5  * Junior University. All Rights Reserved.
      6  *
      7  * Permission to use, copy, modify, and distribute this
      8  * software and its documentation for any purpose and without
      9  * fee is hereby granted, provided that the above copyright
     10  * notice appear in all copies.  Stanford University
     11  * makes no representations about the suitability of this
     12  * software for any purpose.  It is provided "as is" without
     13  * express or implied warranty.
     14  */
     15 
     16 /*
     17  * Jump table for MIPS cpu locore functions that are implemented
     18  * differently on different generations, or instruction-level
     19  * archtecture (ISA) level, the Mips family.
     20  * The following functions must be provided for each mips ISA level:
     21  *
     22  *
     23  *	MachConfigCache
     24  *	MachFlushCache
     25  *	MachFlushDCache
     26  *	MachFlushICache
     27  *	MachForceCacheUpdate
     28  *	MachSetPID
     29  *	MachTLBFlush
     30  *	MachTLBFlushAddr __P()
     31  *	MachTLBUpdate (u_int, (pt_entry_t?) u_int);
     32  *	MachTLBWriteIndexed
     33  *	wbflush
     34  *	proc_trampoline()
     35  *
     36  * We currently provide support for:
     37  *
     38  *	r2000 and r3000 (mips ISA-I)
     39  *	r4000 and r4400 in 32-bit mode (mips ISA-III?)
     40  */
     41 
     42 #ifndef _MIPS_LOCORE_H
     43 #define  _MIPS_LOCORE_H
     44 
     45 /*
     46  * locore service routine for exeception vectors. Used outside locore
     47  * only to print them by name in stack tracebacks
     48  */
     49 
     50 extern void mips1_ConfigCache  __P((void));
     51 extern void mips1_FlushCache  __P((void));
     52 extern void mips1_FlushDCache  __P((vm_offset_t addr, vm_offset_t len));
     53 extern void mips1_FlushICache  __P((vm_offset_t addr, vm_offset_t len));
     54 extern void mips1_ForceCacheUpdate __P((void));
     55 extern void mips1_SetPID   __P((int pid));
     56 extern void mips1_TLBFlush __P((void));
     57 extern void mips1_TLBFlushAddr   __P( /* XXX Really pte highpart ? */
     58 					  (vm_offset_t addr));
     59 extern int mips1_TLBUpdate __P((u_int, /*pt_entry_t*/ u_int));
     60 extern void mips1_TLBWriteIndexed  __P((u_int index, u_int high,
     61 					    u_int low));
     62 extern void mips1_wbflush __P((void));
     63 extern void mips1_proc_trampoline __P((void));
     64 
     65 extern void mips3_ConfigCache __P((void));
     66 extern void mips3_FlushCache  __P((void));
     67 extern void mips3_FlushDCache __P((vm_offset_t addr, vm_offset_t len));
     68 extern void mips3_FlushICache __P((vm_offset_t addr, vm_offset_t len));
     69 extern void mips3_ForceCacheUpdate __P((void));
     70 extern void mips3_SetPID  __P((int pid));
     71 extern void mips3_TLBFlush __P((void));
     72 extern void mips3_TLBFlushAddr __P( /* XXX Really pte highpart ? */
     73 					  (vm_offset_t addr));
     74 extern int mips3_TLBUpdate __P((u_int, /*pt_entry_t*/ u_int));
     75 extern void mips3_TLBWriteIndexedVPS __P((u_int index, void *tlb));
     76 extern void mips3_TLBWriteIndexed __P((u_int index, u_int high,
     77 					   u_int lo0, u_int lo1));
     78 extern void mips3_wbflush __P((void));
     79 extern void mips3_proc_trampoline __P((void));
     80 
     81 /*
     82  *  A vector with an entry for each mips-ISA-level dependent
     83  * locore function, and macros which jump through it.
     84  * XXX the macro names are chosen to be compatible with the old
     85  * Sprite  coding-convention names used in 4.4bsd/pmax.
     86  */
     87 typedef struct  {
     88 	void (*configCache) __P((void));
     89 	void (*flushCache)  __P((void));
     90 	void (*flushDCache) __P((vm_offset_t addr, vm_offset_t len));
     91 	void (*flushICache) __P((vm_offset_t addr, vm_offset_t len));
     92 	void (*forceCacheUpdate)  __P((void));
     93 	void (*setTLBpid)  __P((int pid));
     94 	void (*tlbFlush)  __P((void));
     95 	void (*tlbFlushAddr)  __P((vm_offset_t)); /* XXX Really pte highpart ? */
     96 	int (*tlbUpdate)  __P((u_int highreg, u_int lowreg));
     97 #ifdef MIPS3
     98 	void (*tlbWriteIndexed)  __P((u_int, u_int, u_int, u_int));
     99 #else
    100 	void (*tlbWriteIndexed)  __P((u_int, u_int, u_int));
    101 #endif
    102 	void (*wbflush) __P((void));
    103 	void (*proc_trampoline) __P((void));
    104 } mips_locore_jumpvec_t;
    105 
    106 
    107 /*
    108  * The "active" locore-fuction vector, and
    109 
    110  */
    111 extern mips_locore_jumpvec_t mips_locore_jumpvec;
    112 extern mips_locore_jumpvec_t r2000_locore_vec;
    113 extern mips_locore_jumpvec_t r4000_locore_vec;
    114 
    115 #define MachConfigCache		(*(mips_locore_jumpvec.configCache))
    116 #define MachFlushCache		(*(mips_locore_jumpvec.flushCache))
    117 #define MachFlushDCache		(*(mips_locore_jumpvec.flushDCache))
    118 #define MachFlushICache		(*(mips_locore_jumpvec.flushICache))
    119 #define MachForceCacheUpdate	(*(mips_locore_jumpvec.forceCacheUpdate))
    120 #define MachSetPID		(*(mips_locore_jumpvec.setTLBpid))
    121 #define MachTLBFlush		(*(mips_locore_jumpvec.tlbFlush))
    122 #define MachTLBFlushAddr	(*(mips_locore_jumpvec.tlbFlushAddr))
    123 #define MachTLBUpdate		(*(mips_locore_jumpvec.tlbUpdate))
    124 #define MachTLBWriteIndexed	(*(mips_locore_jumpvec.tlbWriteIndexed))
    125 #define wbflush			(*(mips_locore_jumpvec.wbflush))
    126 #define proc_trampoline		(mips_locore_jumpvec.proc_trampoline)
    127 
    128 #endif	/* _MIPS_LOCORE_H */
    129