locore.h revision 1.52
1 /* $NetBSD: locore.h,v 1.52 2000/10/31 23:39:24 jeffs Exp $ */ 2 3 /* 4 * Copyright 1996 The Board of Trustees of The Leland Stanford 5 * Junior University. All Rights Reserved. 6 * 7 * Permission to use, copy, modify, and distribute this 8 * software and its documentation for any purpose and without 9 * fee is hereby granted, provided that the above copyright 10 * notice appear in all copies. Stanford University 11 * makes no representations about the suitability of this 12 * software for any purpose. It is provided "as is" without 13 * express or implied warranty. 14 */ 15 16 /* 17 * Jump table for MIPS cpu locore functions that are implemented 18 * differently on different generations, or instruction-level 19 * archtecture (ISA) level, the Mips family. 20 * The following functions must be provided for each mips ISA level: 21 * 22 * 23 * MachFlushCache 24 * MachFlushDCache 25 * MachFlushICache 26 * wbflush 27 * proc_trampoline() 28 * cpu_switch_resume() 29 * 30 * We currently provide support for MIPS I and MIPS III. 31 */ 32 33 #ifndef _MIPS_LOCORE_H 34 #define _MIPS_LOCORE_H 35 36 #ifndef _LKM 37 #include "opt_cputype.h" 38 #include "opt_mips_cache.h" 39 #endif 40 41 struct tlb; 42 43 /* 44 * locore service routine for exception vectors. Used outside locore 45 * only to print them by name in stack tracebacks 46 */ 47 48 u_int32_t mips_cp0_cause_read(void); 49 void mips_cp0_cause_write(u_int32_t); 50 u_int32_t mips_cp0_status_read(void); 51 void mips_cp0_status_write(u_int32_t); 52 53 int mips1_icsize(void); 54 int mips1_dcsize(void); 55 void mips1_FlushCache(void); 56 void mips1_FlushDCache(vaddr_t addr, vsize_t len); 57 void mips1_FlushICache(vaddr_t addr, vsize_t len); 58 59 void mips1_SetPID(int pid); 60 void mips1_TBIA(int); 61 void mips1_TBIAP(int); 62 void mips1_TBIS(vaddr_t); 63 int mips1_TLBUpdate(u_int, u_int); 64 void mips1_wbflush(void); 65 void mips1_proc_trampoline(void); 66 void mips1_cpu_switch_resume(void); 67 68 void mips3_ConfigCache(int); 69 void mips3_FlushCache(void); 70 void mips3_FlushDCache(vaddr_t addr, vaddr_t len); 71 void mips3_FlushICache(vaddr_t addr, vaddr_t len); 72 void mips3_HitFlushDCache(vaddr_t, int); 73 74 void mips3_SetPID(int pid); 75 void mips3_TBIA(int); 76 void mips3_TBIAP(int); 77 void mips3_TBIS(vaddr_t); 78 int mips3_TLBUpdate(u_int, u_int); 79 void mips3_TLBRead(int, struct tlb *); 80 void mips3_wbflush(void); 81 void mips3_proc_trampoline(void); 82 void mips3_cpu_switch_resume(void); 83 84 void mips3_FlushCache_2way(void); 85 void mips3_FlushDCache_2way(vaddr_t addr, vaddr_t len); 86 void mips3_HitFlushDCache_2way(vaddr_t, int); 87 void mips3_FlushICache_2way(vaddr_t addr, vaddr_t len); 88 89 u_int32_t mips3_cp0_compare_read(void); 90 void mips3_cp0_compare_write(u_int32_t); 91 92 u_int32_t mips3_cp0_config_read(void); 93 void mips3_cp0_count_write(u_int32_t); 94 95 u_int32_t mips3_cp0_count_read(void); 96 void mips3_cp0_config_write(u_int32_t); 97 98 u_int32_t mips3_cp0_wired_read(void); 99 void mips3_cp0_wired_write(u_int32_t); 100 101 u_int64_t mips3_ld(u_int64_t *); 102 void mips3_sd(u_int64_t *, u_int64_t); 103 104 /* 105 * A vector with an entry for each mips-ISA-level dependent 106 * locore function, and macros which jump through it. 107 * XXX the macro names are chosen to be compatible with the old 108 * Sprite coding-convention names used in 4.4bsd/pmax. 109 */ 110 typedef struct { 111 void (*flushCache)(void); 112 void (*flushDCache)(vaddr_t addr, vsize_t len); 113 void (*flushICache)(vaddr_t addr, vsize_t len); 114 void (*setTLBpid)(int pid); 115 void (*TBIAP)(int); 116 void (*TBIS)(vaddr_t); 117 int (*tlbUpdate)(u_int highreg, u_int lowreg); 118 void (*wbflush)(void); 119 } mips_locore_jumpvec_t; 120 121 /* Override writebuffer-drain method. */ 122 void mips_set_wbflush(void (*)(void)); 123 124 125 /* stacktrace() -- print a stack backtrace to the console */ 126 void stacktrace(void); 127 /* logstacktrace() -- log a stack traceback to msgbuf */ 128 void logstacktrace(void); 129 130 /* 131 * The "active" locore-fuction vector, and 132 133 */ 134 extern mips_locore_jumpvec_t mips_locore_jumpvec; 135 extern mips_locore_jumpvec_t r2000_locore_vec; 136 extern mips_locore_jumpvec_t r4000_locore_vec; 137 extern long *mips_locoresw[]; 138 139 #if defined(MIPS3) && !defined (MIPS1) 140 #if defined(MIPS3_5200) 141 #define MachFlushCache mips3_FlushCache_2way 142 #define MachFlushDCache mips3_FlushDCache_2way 143 #define MachHitFlushDCache mips3_HitFlushDCache_2way 144 #define MachFlushICache mips3_FlushICache_2way 145 #else 146 #define MachFlushCache mips3_FlushCache 147 #if defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_4100) 148 #define MachFlushDCache mips3_FlushDCache /* VR4100 */ 149 #elif !defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_L2CACHE_PRESENT) 150 #define MachFlushDCache mips3_FlushDCache 151 #else 152 #define MachFlushDCache (*(mips_locore_jumpvec.flushDCache)) 153 #endif 154 #define MachHitFlushDCache mips3_HitFlushDCache 155 #define MachFlushICache mips3_FlushICache 156 #endif 157 #define MachSetPID mips3_SetPID 158 #define MIPS_TBIAP() mips3_TBIAP(mips_num_tlb_entries) 159 #define MIPS_TBIS mips3_TBIS 160 #define MachTLBUpdate mips3_TLBUpdate 161 #define wbflush() mips3_wbflush() 162 #define proc_trampoline mips3_proc_trampoline 163 #endif 164 165 #if !defined(MIPS3) && defined (MIPS1) 166 #define MachFlushCache mips1_FlushCache 167 #define MachFlushDCache mips1_FlushDCache 168 #define MachFlushICache mips1_FlushICache 169 #define MachSetPID mips1_SetPID 170 #define MIPS_TBIAP() mips1_TBIAP(mips_num_tlb_entries) 171 #define MIPS_TBIS mips1_TBIS 172 #define MachTLBUpdate mips1_TLBUpdate 173 #define wbflush() mips1_wbflush() 174 #define proc_trampoline mips1_proc_trampoline 175 #endif 176 177 178 179 #if defined(MIPS3) && defined (MIPS1) 180 #define MachFlushCache (*(mips_locore_jumpvec.flushCache)) 181 #define MachFlushDCache (*(mips_locore_jumpvec.flushDCache)) 182 #define MachFlushICache (*(mips_locore_jumpvec.flushICache)) 183 #define MachSetPID (*(mips_locore_jumpvec.setTLBpid)) 184 #define MIPS_TBIAP() (*(mips_locore_jumpvec.TBIAP))(mips_num_tlb_entries) 185 #define MIPS_TBIS (*(mips_locore_jumpvec.TBIS)) 186 #define MachTLBUpdate (*(mips_locore_jumpvec.tlbUpdate)) 187 #define MachHitFlushDCache mips3_HitFlushDCache 188 #define wbflush() (*(mips_locore_jumpvec.wbflush))() 189 #define proc_trampoline (mips_locoresw[1]) 190 #endif 191 192 #define CPU_IDLE (mips_locoresw[2]) 193 194 /* cpu_switch_resume is called inside locore.S */ 195 196 /* 197 * CPU identification, from PRID register. 198 */ 199 typedef int mips_prid_t; 200 201 #define MIPS_PRID_REV(x) (((x) >> 0) & 0x00ff) 202 #define MIPS_PRID_IMPL(x) (((x) >> 8) & 0x00ff) 203 204 /* pre-MIPS32 */ 205 #define MIPS_PRID_RSVD(x) (((x) >> 16) & 0xffff) 206 #define MIPS_PRID_REV_MIN(x) ((MIPS_PRID_REV(x) >> 0) & 0x0f) 207 #define MIPS_PRID_REV_MAJ(x) ((MIPS_PRID_REV(x) >> 4) & 0x0f) 208 209 /* MIPS32 */ 210 #define MIPS_PRID_CID(x) (((x) >> 16) & 0x00ff) /* Company ID */ 211 #define MIPS_PRID_CID_PREHISTORIC 0x00 /* Not MIPS32 */ 212 #define MIPS_PRID_CID_MTI 0x01 /* MIPS Technologies, Inc. */ 213 214 #ifdef _KERNEL 215 216 /* 217 * Global variables used to communicate CPU type, and parameters 218 * such as cache size, from locore to higher-level code (e.g., pmap). 219 */ 220 221 extern mips_prid_t cpu_id; 222 extern mips_prid_t fpu_id; 223 extern int mips_num_tlb_entries; 224 extern u_int mips_L1DCacheSize; 225 extern u_int mips_L1ICacheSize; 226 extern u_int mips_L1DCacheLSize; 227 extern u_int mips_L1ICacheLSize; 228 extern int mips_L2CachePresent; 229 extern u_int mips_L2CacheLSize; 230 extern u_int mips_CacheAliasMask; 231 extern u_int mips_CachePreferMask; 232 233 #define mips_indexof(addr) (((int)(addr)) & mips_CacheAliasMask) 234 235 #ifdef MIPS3 236 extern int mips3_L1TwoWayCache; 237 extern int mips3_cacheflush_bug; 238 #endif /* MIPS3 */ 239 240 void mips_pagecopy(caddr_t dst, caddr_t src); 241 void mips_pagezero(caddr_t dst); 242 243 /* 244 * trapframe argument passed to trap() 245 */ 246 struct trapframe { 247 mips_reg_t tf_regs[17]; 248 mips_reg_t tf_ra; 249 mips_reg_t tf_sr; 250 mips_reg_t tf_mullo; 251 mips_reg_t tf_mulhi; 252 mips_reg_t tf_epc; /* may be changed by trap() call */ 253 }; 254 255 /* 256 * Stack frame for kernel traps. four args passed in registers. 257 * A trapframe is pointed to by the 5th arg, and a dummy sixth argument 258 * is used to avoid alignment problems 259 */ 260 261 struct kernframe { 262 register_t cf_args[4 + 1]; 263 register_t cf_pad; /* (for 8 word alignment) */ 264 register_t cf_sp; 265 register_t cf_ra; 266 struct trapframe cf_frame; 267 }; 268 269 #endif 270 271 #endif /* _MIPS_LOCORE_H */ 272
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