locore.h revision 1.55
1 /* $NetBSD: locore.h,v 1.55 2001/08/15 02:45:08 simonb Exp $ */ 2 3 /* 4 * Copyright 1996 The Board of Trustees of The Leland Stanford 5 * Junior University. All Rights Reserved. 6 * 7 * Permission to use, copy, modify, and distribute this 8 * software and its documentation for any purpose and without 9 * fee is hereby granted, provided that the above copyright 10 * notice appear in all copies. Stanford University 11 * makes no representations about the suitability of this 12 * software for any purpose. It is provided "as is" without 13 * express or implied warranty. 14 */ 15 16 /* 17 * Jump table for MIPS cpu locore functions that are implemented 18 * differently on different generations, or instruction-level 19 * archtecture (ISA) level, the Mips family. 20 * The following functions must be provided for each mips ISA level: 21 * 22 * 23 * MachFlushCache 24 * MachFlushDCache 25 * MachFlushICache 26 * wbflush 27 * proc_trampoline() 28 * cpu_switch_resume() 29 * 30 * We currently provide support for MIPS I and MIPS III. 31 */ 32 33 #ifndef _MIPS_LOCORE_H 34 #define _MIPS_LOCORE_H 35 36 #ifndef _LKM 37 #include "opt_cputype.h" 38 #include "opt_mips_cache.h" 39 #endif 40 41 struct tlb; 42 43 /* 44 * locore service routine for exception vectors. Used outside locore 45 * only to print them by name in stack tracebacks 46 */ 47 48 u_int32_t mips_cp0_cause_read(void); 49 void mips_cp0_cause_write(u_int32_t); 50 u_int32_t mips_cp0_status_read(void); 51 void mips_cp0_status_write(u_int32_t); 52 53 int mips1_icsize(void); 54 int mips1_dcsize(void); 55 void mips1_FlushCache(void); 56 void mips1_FlushDCache(vaddr_t, vsize_t); 57 void mips1_FlushICache(vaddr_t, vsize_t); 58 59 void mips1_SetPID(int); 60 void mips1_TBIA(int); 61 void mips1_TBIAP(int); 62 void mips1_TBIS(vaddr_t); 63 int mips1_TLBUpdate(u_int, u_int); 64 void mips1_wbflush(void); 65 void mips1_proc_trampoline(void); 66 void mips1_cpu_switch_resume(void); 67 68 void mips3_ConfigCache(int); 69 void mips3_FlushCache(void); 70 void mips3_FlushDCache(vaddr_t, vsize_t); 71 void mips3_FlushICache(vaddr_t, vsize_t); 72 void mips3_HitFlushDCache(vaddr_t, vsize_t); 73 74 void mips3_SetPID(int); 75 void mips3_TBIA(int); 76 void mips3_TBIAP(int); 77 void mips3_TBIS(vaddr_t); 78 int mips3_TLBUpdate(u_int, u_int); 79 void mips3_TLBRead(int, struct tlb *); 80 void mips3_wbflush(void); 81 void mips3_proc_trampoline(void); 82 void mips3_cpu_switch_resume(void); 83 84 void mips3_FlushCache_2way(void); 85 void mips3_FlushDCache_2way(vaddr_t, vaddr_t); 86 void mips3_FlushICache_2way(vaddr_t, vaddr_t); 87 void mips3_HitFlushDCache_2way(vaddr_t, vsize_t); 88 89 u_int32_t mips3_cp0_compare_read(void); 90 void mips3_cp0_compare_write(u_int32_t); 91 92 u_int32_t mips3_cp0_config_read(void); 93 void mips3_cp0_count_write(u_int32_t); 94 95 u_int32_t mips3_cp0_count_read(void); 96 void mips3_cp0_config_write(u_int32_t); 97 98 u_int32_t mips3_cp0_wired_read(void); 99 void mips3_cp0_wired_write(u_int32_t); 100 101 u_int64_t mips3_ld(u_int64_t *); 102 void mips3_sd(u_int64_t *, u_int64_t); 103 104 /* 105 * A vector with an entry for each mips-ISA-level dependent 106 * locore function, and macros which jump through it. 107 * XXX the macro names are chosen to be compatible with the old 108 * Sprite coding-convention names used in 4.4bsd/pmax. 109 */ 110 typedef struct { 111 void (*flushCache)(void); 112 void (*flushDCache)(vaddr_t addr, vsize_t len); 113 void (*flushICache)(vaddr_t addr, vsize_t len); 114 void (*hitflushDCache)(vaddr_t, vsize_t); 115 void (*setTLBpid)(int pid); 116 void (*TBIAP)(int); 117 void (*TBIS)(vaddr_t); 118 int (*tlbUpdate)(u_int highreg, u_int lowreg); 119 void (*wbflush)(void); 120 } mips_locore_jumpvec_t; 121 122 /* Override writebuffer-drain method. */ 123 void mips_set_wbflush(void (*)(void)); 124 125 126 /* stacktrace() -- print a stack backtrace to the console */ 127 void stacktrace(void); 128 /* logstacktrace() -- log a stack traceback to msgbuf */ 129 void logstacktrace(void); 130 131 /* 132 * The "active" locore-fuction vector, and 133 */ 134 extern mips_locore_jumpvec_t mips_locore_jumpvec; 135 extern mips_locore_jumpvec_t r2000_locore_vec; 136 extern mips_locore_jumpvec_t r4000_locore_vec; 137 extern long *mips_locoresw[]; 138 139 /* 140 * Always indirect to get the cache ops. There are just too many 141 * combinations to try and worry about. 142 */ 143 #define MachFlushCache (*(mips_locore_jumpvec.flushCache)) 144 #define MachFlushDCache (*(mips_locore_jumpvec.flushDCache)) 145 #define MachFlushICache (*(mips_locore_jumpvec.flushICache)) 146 #define MachHitFlushDCache (*(mips_locore_jumpvec.hitflushDCache)) 147 148 #if defined(MIPS3) && !defined(MIPS1) 149 #define MachSetPID mips3_SetPID 150 #define MIPS_TBIAP() mips3_TBIAP(mips_num_tlb_entries) 151 #define MIPS_TBIS mips3_TBIS 152 #define MachTLBUpdate mips3_TLBUpdate 153 #define wbflush() mips3_wbflush() 154 #define proc_trampoline mips3_proc_trampoline 155 #endif 156 157 #if !defined(MIPS3) && defined(MIPS1) 158 #define MachSetPID mips1_SetPID 159 #define MIPS_TBIAP() mips1_TBIAP(mips_num_tlb_entries) 160 #define MIPS_TBIS mips1_TBIS 161 #define MachTLBUpdate mips1_TLBUpdate 162 #define wbflush() mips1_wbflush() 163 #define proc_trampoline mips1_proc_trampoline 164 #endif 165 166 #if defined(MIPS3) && defined(MIPS1) 167 #define MachSetPID (*(mips_locore_jumpvec.setTLBpid)) 168 #define MIPS_TBIAP() (*(mips_locore_jumpvec.TBIAP))(mips_num_tlb_entries) 169 #define MIPS_TBIS (*(mips_locore_jumpvec.TBIS)) 170 #define MachTLBUpdate (*(mips_locore_jumpvec.tlbUpdate)) 171 #define wbflush() (*(mips_locore_jumpvec.wbflush))() 172 #define proc_trampoline (mips_locoresw[1]) 173 #endif 174 175 #define CPU_IDLE (mips_locoresw[2]) 176 177 /* cpu_switch_resume is called inside locore.S */ 178 179 /* 180 * CPU identification, from PRID register. 181 */ 182 typedef int mips_prid_t; 183 184 #define MIPS_PRID_REV(x) (((x) >> 0) & 0x00ff) 185 #define MIPS_PRID_IMPL(x) (((x) >> 8) & 0x00ff) 186 187 /* pre-MIPS32 */ 188 #define MIPS_PRID_RSVD(x) (((x) >> 16) & 0xffff) 189 #define MIPS_PRID_REV_MIN(x) ((MIPS_PRID_REV(x) >> 0) & 0x0f) 190 #define MIPS_PRID_REV_MAJ(x) ((MIPS_PRID_REV(x) >> 4) & 0x0f) 191 192 /* MIPS32 */ 193 #define MIPS_PRID_CID(x) (((x) >> 16) & 0x00ff) /* Company ID */ 194 #define MIPS_PRID_CID_PREHISTORIC 0x00 /* Not MIPS32 */ 195 #define MIPS_PRID_CID_MTI 0x01 /* MIPS Technologies, Inc. */ 196 #define MIPS_PRID_CID_ALCHEMY 0x03 /* Alchemy Semiconductor */ 197 #define MIPS_PRID_CID_SIBYTE 0x04 /* SiByte */ 198 199 #ifdef _KERNEL 200 201 /* 202 * Global variables used to communicate CPU type, and parameters 203 * such as cache size, from locore to higher-level code (e.g., pmap). 204 */ 205 206 extern mips_prid_t cpu_id; 207 extern mips_prid_t fpu_id; 208 extern int mips_num_tlb_entries; 209 extern u_int mips_L1DCacheSize; 210 extern u_int mips_L1ICacheSize; 211 extern u_int mips_L1DCacheLSize; 212 extern u_int mips_L1ICacheLSize; 213 extern int mips_L2CachePresent; 214 extern u_int mips_L2CacheLSize; 215 extern u_int mips_CacheAliasMask; 216 extern u_int mips_CachePreferMask; 217 218 #define mips_indexof(addr) (((int)(addr)) & mips_CacheAliasMask) 219 220 #ifdef MIPS3 221 extern int mips3_L1TwoWayCache; 222 extern int mips3_cacheflush_bug; 223 #endif /* MIPS3 */ 224 225 void mips_pagecopy(caddr_t dst, caddr_t src); 226 void mips_pagezero(caddr_t dst); 227 228 /* 229 * trapframe argument passed to trap() 230 */ 231 struct trapframe { 232 mips_reg_t tf_regs[17]; 233 mips_reg_t tf_ra; 234 mips_reg_t tf_sr; 235 mips_reg_t tf_mullo; 236 mips_reg_t tf_mulhi; 237 mips_reg_t tf_epc; /* may be changed by trap() call */ 238 }; 239 240 /* 241 * Stack frame for kernel traps. four args passed in registers. 242 * A trapframe is pointed to by the 5th arg, and a dummy sixth argument 243 * is used to avoid alignment problems 244 */ 245 246 struct kernframe { 247 register_t cf_args[4 + 1]; 248 register_t cf_pad; /* (for 8 word alignment) */ 249 register_t cf_sp; 250 register_t cf_ra; 251 struct trapframe cf_frame; 252 }; 253 254 #endif 255 256 #endif /* _MIPS_LOCORE_H */ 257
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