locore.h revision 1.58
1 /* $NetBSD: locore.h,v 1.58 2001/11/14 18:15:20 thorpej Exp $ */ 2 3 /* 4 * Copyright 1996 The Board of Trustees of The Leland Stanford 5 * Junior University. All Rights Reserved. 6 * 7 * Permission to use, copy, modify, and distribute this 8 * software and its documentation for any purpose and without 9 * fee is hereby granted, provided that the above copyright 10 * notice appear in all copies. Stanford University 11 * makes no representations about the suitability of this 12 * software for any purpose. It is provided "as is" without 13 * express or implied warranty. 14 */ 15 16 /* 17 * Jump table for MIPS cpu locore functions that are implemented 18 * differently on different generations, or instruction-level 19 * archtecture (ISA) level, the Mips family. 20 * 21 * We currently provide support for MIPS I and MIPS III. 22 */ 23 24 #ifndef _MIPS_LOCORE_H 25 #define _MIPS_LOCORE_H 26 27 #ifndef _LKM 28 #include "opt_cputype.h" 29 #include "opt_mips_cache.h" 30 #endif 31 32 struct tlb; 33 34 /* 35 * locore service routine for exception vectors. Used outside locore 36 * only to print them by name in stack tracebacks 37 */ 38 39 u_int32_t mips_cp0_cause_read(void); 40 void mips_cp0_cause_write(u_int32_t); 41 u_int32_t mips_cp0_status_read(void); 42 void mips_cp0_status_write(u_int32_t); 43 44 void mips1_SetPID(int); 45 void mips1_TBIA(int); 46 void mips1_TBIAP(int); 47 void mips1_TBIS(vaddr_t); 48 int mips1_TLBUpdate(u_int, u_int); 49 void mips1_wbflush(void); 50 void mips1_proc_trampoline(void); 51 void mips1_cpu_switch_resume(void); 52 53 uint32_t tx3900_cp0_config_read(void); 54 55 void mips3_SetPID(int); 56 void mips3_TBIA(int); 57 void mips3_TBIAP(int); 58 void mips3_TBIS(vaddr_t); 59 int mips3_TLBUpdate(u_int, u_int); 60 void mips3_TLBRead(int, struct tlb *); 61 void mips3_wbflush(void); 62 void mips3_proc_trampoline(void); 63 void mips3_cpu_switch_resume(void); 64 65 u_int32_t mips3_cp0_compare_read(void); 66 void mips3_cp0_compare_write(u_int32_t); 67 68 u_int32_t mips3_cp0_config_read(void); 69 void mips3_cp0_config_write(u_int32_t); 70 71 u_int32_t mips3_cp0_count_read(void); 72 void mips3_cp0_count_write(u_int32_t); 73 74 u_int32_t mips3_cp0_wired_read(void); 75 void mips3_cp0_wired_write(u_int32_t); 76 77 u_int64_t mips3_ld(u_int64_t *); 78 void mips3_sd(u_int64_t *, u_int64_t); 79 80 /* 81 * A vector with an entry for each mips-ISA-level dependent 82 * locore function, and macros which jump through it. 83 * 84 * XXX the macro names are chosen to be compatible with the old 85 * XXX Sprite coding-convention names used in 4.4bsd/pmax. 86 */ 87 typedef struct { 88 void (*setTLBpid)(int pid); 89 void (*TBIAP)(int); 90 void (*TBIS)(vaddr_t); 91 int (*tlbUpdate)(u_int highreg, u_int lowreg); 92 void (*wbflush)(void); 93 } mips_locore_jumpvec_t; 94 95 /* Override writebuffer-drain method. */ 96 void mips_set_wbflush(void (*)(void)); 97 98 /* stacktrace() -- print a stack backtrace to the console */ 99 void stacktrace(void); 100 /* logstacktrace() -- log a stack traceback to msgbuf */ 101 void logstacktrace(void); 102 103 /* 104 * The "active" locore-fuction vector, and 105 */ 106 extern mips_locore_jumpvec_t mips_locore_jumpvec; 107 extern mips_locore_jumpvec_t r2000_locore_vec; 108 extern mips_locore_jumpvec_t r4000_locore_vec; 109 extern long *mips_locoresw[]; 110 111 #if defined(MIPS3) && !defined(MIPS1) 112 #define MachSetPID mips3_SetPID 113 #define MIPS_TBIAP() mips3_TBIAP(mips_num_tlb_entries) 114 #define MIPS_TBIS mips3_TBIS 115 #define MachTLBUpdate mips3_TLBUpdate 116 #define wbflush() mips3_wbflush() 117 #define proc_trampoline mips3_proc_trampoline 118 #endif 119 120 #if !defined(MIPS3) && defined(MIPS1) 121 #define MachSetPID mips1_SetPID 122 #define MIPS_TBIAP() mips1_TBIAP(mips_num_tlb_entries) 123 #define MIPS_TBIS mips1_TBIS 124 #define MachTLBUpdate mips1_TLBUpdate 125 #define wbflush() mips1_wbflush() 126 #define proc_trampoline mips1_proc_trampoline 127 #endif 128 129 #if defined(MIPS3) && defined(MIPS1) 130 #define MachSetPID (*(mips_locore_jumpvec.setTLBpid)) 131 #define MIPS_TBIAP() (*(mips_locore_jumpvec.TBIAP))(mips_num_tlb_entries) 132 #define MIPS_TBIS (*(mips_locore_jumpvec.TBIS)) 133 #define MachTLBUpdate (*(mips_locore_jumpvec.tlbUpdate)) 134 #define wbflush() (*(mips_locore_jumpvec.wbflush))() 135 #define proc_trampoline (mips_locoresw[1]) 136 #endif 137 138 #define CPU_IDLE (mips_locoresw[2]) 139 140 /* cpu_switch_resume is called inside locore.S */ 141 142 /* 143 * CPU identification, from PRID register. 144 */ 145 typedef int mips_prid_t; 146 147 #define MIPS_PRID_REV(x) (((x) >> 0) & 0x00ff) 148 #define MIPS_PRID_IMPL(x) (((x) >> 8) & 0x00ff) 149 150 /* pre-MIPS32 */ 151 #define MIPS_PRID_RSVD(x) (((x) >> 16) & 0xffff) 152 #define MIPS_PRID_REV_MIN(x) ((MIPS_PRID_REV(x) >> 0) & 0x0f) 153 #define MIPS_PRID_REV_MAJ(x) ((MIPS_PRID_REV(x) >> 4) & 0x0f) 154 155 /* MIPS32 */ 156 #define MIPS_PRID_CID(x) (((x) >> 16) & 0x00ff) /* Company ID */ 157 #define MIPS_PRID_CID_PREHISTORIC 0x00 /* Not MIPS32 */ 158 #define MIPS_PRID_CID_MTI 0x01 /* MIPS Technologies, Inc. */ 159 #define MIPS_PRID_CID_ALCHEMY 0x03 /* Alchemy Semiconductor */ 160 #define MIPS_PRID_CID_SIBYTE 0x04 /* SiByte */ 161 162 #ifdef _KERNEL 163 164 /* 165 * Global variables used to communicate CPU type, and parameters 166 * such as cache size, from locore to higher-level code (e.g., pmap). 167 */ 168 169 extern mips_prid_t cpu_id; 170 extern mips_prid_t fpu_id; 171 extern int mips_num_tlb_entries; 172 173 void mips_pagecopy(caddr_t dst, caddr_t src); 174 void mips_pagezero(caddr_t dst); 175 176 /* 177 * trapframe argument passed to trap() 178 */ 179 struct trapframe { 180 mips_reg_t tf_regs[17]; 181 mips_reg_t tf_ra; 182 mips_reg_t tf_sr; 183 mips_reg_t tf_mullo; 184 mips_reg_t tf_mulhi; 185 mips_reg_t tf_epc; /* may be changed by trap() call */ 186 u_int32_t tf_ppl; /* previous priority level */ 187 int32_t tf_pad; /* for 8 byte aligned */ 188 }; 189 190 /* 191 * Stack frame for kernel traps. four args passed in registers. 192 * A trapframe is pointed to by the 5th arg, and a dummy sixth argument 193 * is used to avoid alignment problems 194 */ 195 196 struct kernframe { 197 register_t cf_args[4 + 1]; 198 register_t cf_pad; /* (for 8 word alignment) */ 199 register_t cf_sp; 200 register_t cf_ra; 201 struct trapframe cf_frame; 202 }; 203 204 #endif 205 206 #endif /* _MIPS_LOCORE_H */ 207
Indexes created Tue Sep 30 20:09:53 GMT 2025