locore.h revision 1.59
1 /* $NetBSD: locore.h,v 1.59 2002/03/05 15:36:51 simonb Exp $ */ 2 3 /* 4 * Copyright 1996 The Board of Trustees of The Leland Stanford 5 * Junior University. All Rights Reserved. 6 * 7 * Permission to use, copy, modify, and distribute this 8 * software and its documentation for any purpose and without 9 * fee is hereby granted, provided that the above copyright 10 * notice appear in all copies. Stanford University 11 * makes no representations about the suitability of this 12 * software for any purpose. It is provided "as is" without 13 * express or implied warranty. 14 */ 15 16 /* 17 * Jump table for MIPS cpu locore functions that are implemented 18 * differently on different generations, or instruction-level 19 * archtecture (ISA) level, the Mips family. 20 * 21 * We currently provide support for MIPS I and MIPS III. 22 */ 23 24 #ifndef _MIPS_LOCORE_H 25 #define _MIPS_LOCORE_H 26 27 #ifndef _LKM 28 #include "opt_cputype.h" 29 #include "opt_mips_cache.h" 30 #endif 31 32 #include <mips/cpuregs.h> 33 34 struct tlb; 35 36 /* 37 * locore service routine for exception vectors. Used outside locore 38 * only to print them by name in stack tracebacks 39 */ 40 41 uint32_t mips_cp0_cause_read(void); 42 void mips_cp0_cause_write(uint32_t); 43 uint32_t mips_cp0_status_read(void); 44 void mips_cp0_status_write(uint32_t); 45 46 #ifdef MIPS1 47 void mips1_SetPID(int); 48 void mips1_TBIA(int); 49 void mips1_TBIAP(int); 50 void mips1_TBIS(vaddr_t); 51 int mips1_TLBUpdate(u_int, u_int); 52 void mips1_wbflush(void); 53 void mips1_proc_trampoline(void); 54 void mips1_cpu_switch_resume(void); 55 56 uint32_t tx3900_cp0_config_read(void); 57 #endif 58 59 #if defined(MIPS3) || defined(MIPS4) 60 void mips3_SetPID(int); 61 void mips3_TBIA(int); 62 void mips3_TBIAP(int); 63 void mips3_TBIS(vaddr_t); 64 int mips3_TLBUpdate(u_int, u_int); 65 void mips3_TLBRead(int, struct tlb *); 66 void mips3_wbflush(void); 67 void mips3_proc_trampoline(void); 68 void mips3_cpu_switch_resume(void); 69 70 #ifdef MIPS3_5900 71 void mips5900_SetPID(int); 72 void mips5900_TBIA(int); 73 void mips5900_TBIAP(int); 74 void mips5900_TBIS(vaddr_t); 75 int mips5900_TLBUpdate(u_int, u_int); 76 void mips5900_TLBRead(int, struct tlb *); 77 void mips5900_wbflush(void); 78 void mips5900_proc_trampoline(void); 79 void mips5900_cpu_switch_resume(void); 80 #endif 81 #endif 82 83 #ifdef MIPS32 84 void mips32_SetPID(int); 85 void mips32_TBIA(int); 86 void mips32_TBIAP(int); 87 void mips32_TBIS(vaddr_t); 88 int mips32_TLBUpdate(u_int, u_int); 89 void mips32_TLBRead(int, struct tlb *); 90 void mips32_wbflush(void); 91 void mips32_proc_trampoline(void); 92 void mips32_cpu_switch_resume(void); 93 #endif 94 95 #ifdef MIPS64 96 void mips64_SetPID(int); 97 void mips64_TBIA(int); 98 void mips64_TBIAP(int); 99 void mips64_TBIS(vaddr_t); 100 int mips64_TLBUpdate(u_int, u_int); 101 void mips64_TLBRead(int, struct tlb *); 102 void mips64_wbflush(void); 103 void mips64_proc_trampoline(void); 104 void mips64_cpu_switch_resume(void); 105 #endif 106 107 uint32_t mips3_cp0_compare_read(void); 108 void mips3_cp0_compare_write(uint32_t); 109 110 uint32_t mips3_cp0_config_read(void); 111 void mips3_cp0_config_write(uint32_t); 112 uint32_t mipsNN_cp0_config1_read(void); 113 void mipsNN_cp0_config1_write(uint32_t); 114 115 uint32_t mips3_cp0_count_read(void); 116 void mips3_cp0_count_write(uint32_t); 117 118 uint32_t mips3_cp0_wired_read(void); 119 void mips3_cp0_wired_write(uint32_t); 120 121 uint64_t mips3_ld(uint64_t *); 122 void mips3_sd(uint64_t *, uint64_t); 123 124 static inline uint32_t mips3_lw_a64(uint64_t addr) 125 __attribute__((__unused__)); 126 static inline void mips3_sw_a64(uint64_t addr, uint32_t val) 127 __attribute__ ((__unused__)); 128 129 static inline uint32_t 130 mips3_lw_a64(uint64_t addr) 131 { 132 uint32_t addrlo, addrhi; 133 uint32_t rv; 134 uint32_t sr; 135 136 sr = mips_cp0_status_read(); 137 mips_cp0_status_write(sr | MIPS3_SR_KX); 138 139 addrlo = addr & 0xffffffff; 140 addrhi = addr >> 32; 141 __asm__ __volatile__ (" \n\ 142 .set push \n\ 143 .set mips3 \n\ 144 .set noreorder \n\ 145 .set noat \n\ 146 dsll32 $3, %1, 0 \n\ 147 dsll32 $1, %2, 0 \n\ 148 dsrl32 $3, $3, 0 \n\ 149 or $1, $1, $3 \n\ 150 lw %0, 0($1) \n\ 151 .set pop \n\ 152 " : "=r"(rv) : "r"(addrlo), "r"(addrhi) : "$1", "$3" ); 153 154 mips_cp0_status_write(sr); 155 156 return (rv); 157 } 158 159 static inline void 160 mips3_sw_a64(uint64_t addr, uint32_t val) 161 { 162 uint32_t addrlo, addrhi; 163 uint32_t sr; 164 165 sr = mips_cp0_status_read(); 166 mips_cp0_status_write(sr | MIPS3_SR_KX); 167 168 addrlo = addr & 0xffffffff; 169 addrhi = addr >> 32; 170 __asm__ __volatile__ (" \n\ 171 .set push \n\ 172 .set mips3 \n\ 173 .set noreorder \n\ 174 .set noat \n\ 175 dsll32 $3, %1, 0 \n\ 176 dsll32 $1, %2, 0 \n\ 177 dsrl32 $3, $3, 0 \n\ 178 or $1, $1, $3 \n\ 179 sw %0, 0($1) \n\ 180 .set pop \n\ 181 " : : "r"(val), "r"(addrlo), "r"(addrhi) : "$1", "$3" ); 182 183 mips_cp0_status_write(sr); 184 } 185 186 /* 187 * A vector with an entry for each mips-ISA-level dependent 188 * locore function, and macros which jump through it. 189 * 190 * XXX the macro names are chosen to be compatible with the old 191 * XXX Sprite coding-convention names used in 4.4bsd/pmax. 192 */ 193 typedef struct { 194 void (*setTLBpid)(int pid); 195 void (*TBIAP)(int); 196 void (*TBIS)(vaddr_t); 197 int (*tlbUpdate)(u_int highreg, u_int lowreg); 198 void (*wbflush)(void); 199 } mips_locore_jumpvec_t; 200 201 /* Override writebuffer-drain method. */ 202 void mips_set_wbflush(void (*)(void)); 203 204 /* stacktrace() -- print a stack backtrace to the console */ 205 void stacktrace(void); 206 /* logstacktrace() -- log a stack traceback to msgbuf */ 207 void logstacktrace(void); 208 209 /* 210 * The "active" locore-fuction vector, and 211 */ 212 extern mips_locore_jumpvec_t mips_locore_jumpvec; 213 extern long *mips_locoresw[]; 214 215 #if defined(MIPS1) && !defined(MIPS3) && !defined(MIPS32) && !defined(MIPS64) 216 #define MachSetPID mips1_SetPID 217 #define MIPS_TBIAP() mips1_TBIAP(mips_num_tlb_entries) 218 #define MIPS_TBIS mips1_TBIS 219 #define MachTLBUpdate mips1_TLBUpdate 220 #define wbflush() mips1_wbflush() 221 #define proc_trampoline mips1_proc_trampoline 222 #elif !defined(MIPS1) && defined(MIPS3) && !defined(MIPS32) && !defined(MIPS64) 223 #define MachSetPID mips3_SetPID 224 #define MIPS_TBIAP() mips3_TBIAP(mips_num_tlb_entries) 225 #define MIPS_TBIS mips3_TBIS 226 #define MachTLBUpdate mips3_TLBUpdate 227 #define proc_trampoline mips3_proc_trampoline 228 #define wbflush() mips3_wbflush() 229 #elif !defined(MIPS1) && !defined(MIPS3) && defined(MIPS32) && !defined(MIPS64) 230 #define MachSetPID mips32_SetPID 231 #define MIPS_TBIAP() mips32_TBIAP(mips_num_tlb_entries) 232 #define MIPS_TBIS mips32_TBIS 233 #define MachTLBUpdate mips32_TLBUpdate 234 #define proc_trampoline mips32_proc_trampoline 235 #define wbflush() mips32_wbflush() 236 #elif !defined(MIPS1) && !defined(MIPS3) && !defined(MIPS32) && defined(MIPS64) 237 /* all common with mips3 */ 238 #define MachSetPID mips64_SetPID 239 #define MIPS_TBIAP() mips64_TBIAP(mips_num_tlb_entries) 240 #define MIPS_TBIS mips64_TBIS 241 #define MachTLBUpdate mips64_TLBUpdate 242 #define proc_trampoline mips64_proc_trampoline 243 #define wbflush() mips64_wbflush() 244 #else 245 #define MachSetPID (*(mips_locore_jumpvec.setTLBpid)) 246 #define MIPS_TBIAP() (*(mips_locore_jumpvec.TBIAP))(mips_num_tlb_entries) 247 #define MIPS_TBIS (*(mips_locore_jumpvec.TBIS)) 248 #define MachTLBUpdate (*(mips_locore_jumpvec.tlbUpdate)) 249 #define wbflush() (*(mips_locore_jumpvec.wbflush))() 250 #define proc_trampoline (mips_locoresw[1]) 251 #endif 252 253 #define CPU_IDLE (mips_locoresw[2]) 254 255 /* cpu_switch_resume is called inside locore.S */ 256 257 /* 258 * CPU identification, from PRID register. 259 */ 260 typedef int mips_prid_t; 261 262 #define MIPS_PRID_REV(x) (((x) >> 0) & 0x00ff) 263 #define MIPS_PRID_IMPL(x) (((x) >> 8) & 0x00ff) 264 265 /* pre-MIPS32/64 */ 266 #define MIPS_PRID_RSVD(x) (((x) >> 16) & 0xffff) 267 #define MIPS_PRID_REV_MIN(x) ((MIPS_PRID_REV(x) >> 0) & 0x0f) 268 #define MIPS_PRID_REV_MAJ(x) ((MIPS_PRID_REV(x) >> 4) & 0x0f) 269 270 /* MIPS32/64 */ 271 #define MIPS_PRID_CID(x) (((x) >> 16) & 0x00ff) /* Company ID */ 272 #define MIPS_PRID_CID_PREHISTORIC 0x00 /* Not MIPS32/64 */ 273 #define MIPS_PRID_CID_MTI 0x01 /* MIPS Technologies, Inc. */ 274 #define MIPS_PRID_CID_BROADCOM 0x02 /* Broadcom */ 275 #define MIPS_PRID_CID_ALCHEMY 0x03 /* Alchemy Semiconductor */ 276 #define MIPS_PRID_CID_SIBYTE 0x04 /* SiByte */ 277 #define MIPS_PRID_CID_SANDCRAFT 0x05 /* SandCraft */ 278 #define MIPS_PRID_COPTS(x) (((x) >> 24) & 0x00ff) /* Company Options */ 279 280 #ifdef _KERNEL 281 /* 282 * Global variables used to communicate CPU type, and parameters 283 * such as cache size, from locore to higher-level code (e.g., pmap). 284 */ 285 286 extern mips_prid_t cpu_id; 287 extern mips_prid_t fpu_id; 288 extern int mips_num_tlb_entries; 289 290 void mips_pagecopy(caddr_t dst, caddr_t src); 291 void mips_pagezero(caddr_t dst); 292 293 #ifdef __HAVE_MIPS_MACHDEP_CACHE_CONFIG 294 void mips_machdep_cache_config(void); 295 #endif 296 297 /* 298 * trapframe argument passed to trap() 299 */ 300 struct trapframe { 301 mips_reg_t tf_regs[17]; 302 mips_reg_t tf_ra; 303 mips_reg_t tf_sr; 304 mips_reg_t tf_mullo; 305 mips_reg_t tf_mulhi; 306 mips_reg_t tf_epc; /* may be changed by trap() call */ 307 u_int32_t tf_ppl; /* previous priority level */ 308 int32_t tf_pad; /* for 8 byte aligned */ 309 }; 310 311 /* 312 * Stack frame for kernel traps. four args passed in registers. 313 * A trapframe is pointed to by the 5th arg, and a dummy sixth argument 314 * is used to avoid alignment problems 315 */ 316 317 struct kernframe { 318 register_t cf_args[4 + 1]; 319 register_t cf_pad; /* (for 8 word alignment) */ 320 register_t cf_sp; 321 register_t cf_ra; 322 struct trapframe cf_frame; 323 }; 324 #endif 325 #endif /* _MIPS_LOCORE_H */ 326
Indexes created Wed Oct 01 15:09:59 GMT 2025