locore.h revision 1.67
1 /* $NetBSD: locore.h,v 1.67 2003/10/29 23:39:16 simonb Exp $ */ 2 3 /* 4 * Copyright 1996 The Board of Trustees of The Leland Stanford 5 * Junior University. All Rights Reserved. 6 * 7 * Permission to use, copy, modify, and distribute this 8 * software and its documentation for any purpose and without 9 * fee is hereby granted, provided that the above copyright 10 * notice appear in all copies. Stanford University 11 * makes no representations about the suitability of this 12 * software for any purpose. It is provided "as is" without 13 * express or implied warranty. 14 */ 15 16 /* 17 * Jump table for MIPS cpu locore functions that are implemented 18 * differently on different generations, or instruction-level 19 * archtecture (ISA) level, the Mips family. 20 * 21 * We currently provide support for MIPS I and MIPS III. 22 */ 23 24 #ifndef _MIPS_LOCORE_H 25 #define _MIPS_LOCORE_H 26 27 #ifndef _LKM 28 #include "opt_cputype.h" 29 #endif 30 31 #include <mips/cpuregs.h> 32 33 struct tlb; 34 35 uint32_t mips_cp0_cause_read(void); 36 void mips_cp0_cause_write(uint32_t); 37 uint32_t mips_cp0_status_read(void); 38 void mips_cp0_status_write(uint32_t); 39 40 #ifdef MIPS1 41 void mips1_SetPID(int); 42 void mips1_TBIA(int); 43 void mips1_TBIAP(int); 44 void mips1_TBIS(vaddr_t); 45 int mips1_TLBUpdate(u_int, u_int); 46 void mips1_wbflush(void); 47 void mips1_proc_trampoline(void); 48 void mips1_cpu_switch_resume(void); 49 50 uint32_t tx3900_cp0_config_read(void); 51 #endif 52 53 #if defined(MIPS3) || defined(MIPS4) 54 void mips3_SetPID(int); 55 void mips3_TBIA(int); 56 void mips3_TBIAP(int); 57 void mips3_TBIS(vaddr_t); 58 int mips3_TLBUpdate(u_int, u_int); 59 void mips3_TLBRead(int, struct tlb *); 60 void mips3_wbflush(void); 61 void mips3_proc_trampoline(void); 62 void mips3_cpu_switch_resume(void); 63 void mips3_pagezero(caddr_t dst); 64 65 #ifdef MIPS3_5900 66 void mips5900_SetPID(int); 67 void mips5900_TBIA(int); 68 void mips5900_TBIAP(int); 69 void mips5900_TBIS(vaddr_t); 70 int mips5900_TLBUpdate(u_int, u_int); 71 void mips5900_TLBRead(int, struct tlb *); 72 void mips5900_wbflush(void); 73 void mips5900_proc_trampoline(void); 74 void mips5900_cpu_switch_resume(void); 75 void mips5900_pagezero(caddr_t dst); 76 #endif 77 #endif 78 79 #ifdef MIPS32 80 void mips32_SetPID(int); 81 void mips32_TBIA(int); 82 void mips32_TBIAP(int); 83 void mips32_TBIS(vaddr_t); 84 int mips32_TLBUpdate(u_int, u_int); 85 void mips32_TLBRead(int, struct tlb *); 86 void mips32_wbflush(void); 87 void mips32_proc_trampoline(void); 88 void mips32_cpu_switch_resume(void); 89 #endif 90 91 #ifdef MIPS64 92 void mips64_SetPID(int); 93 void mips64_TBIA(int); 94 void mips64_TBIAP(int); 95 void mips64_TBIS(vaddr_t); 96 int mips64_TLBUpdate(u_int, u_int); 97 void mips64_TLBRead(int, struct tlb *); 98 void mips64_wbflush(void); 99 void mips64_proc_trampoline(void); 100 void mips64_cpu_switch_resume(void); 101 void mips64_pagezero(caddr_t dst); 102 #endif 103 104 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64) 105 uint32_t mips3_cp0_compare_read(void); 106 void mips3_cp0_compare_write(uint32_t); 107 108 uint32_t mips3_cp0_config_read(void); 109 void mips3_cp0_config_write(uint32_t); 110 #if defined(MIPS32) || defined(MIPS64) 111 uint32_t mipsNN_cp0_config1_read(void); 112 void mipsNN_cp0_config1_write(uint32_t); 113 uint32_t mipsNN_cp0_config2_read(void); 114 uint32_t mipsNN_cp0_config3_read(void); 115 #endif 116 117 uint32_t mips3_cp0_count_read(void); 118 void mips3_cp0_count_write(uint32_t); 119 120 uint32_t mips3_cp0_wired_read(void); 121 void mips3_cp0_wired_write(uint32_t); 122 123 uint64_t mips3_ld(uint64_t *); 124 void mips3_sd(uint64_t *, uint64_t); 125 #endif /* MIPS3 || MIPS4 || MIPS32 || MIPS64 */ 126 127 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS64) 128 static inline uint32_t mips3_lw_a64(uint64_t addr) 129 __attribute__((__unused__)); 130 static inline void mips3_sw_a64(uint64_t addr, uint32_t val) 131 __attribute__ ((__unused__)); 132 133 static inline uint32_t 134 mips3_lw_a64(uint64_t addr) 135 { 136 uint32_t addrlo, addrhi; 137 uint32_t rv; 138 uint32_t sr; 139 140 sr = mips_cp0_status_read(); 141 mips_cp0_status_write(sr | MIPS3_SR_KX); 142 143 addrlo = addr & 0xffffffff; 144 addrhi = addr >> 32; 145 __asm__ __volatile__ (" \n\ 146 .set push \n\ 147 .set mips3 \n\ 148 .set noreorder \n\ 149 .set noat \n\ 150 dsll32 $3, %1, 0 \n\ 151 dsll32 $1, %2, 0 \n\ 152 dsrl32 $3, $3, 0 \n\ 153 or $1, $1, $3 \n\ 154 lw %0, 0($1) \n\ 155 .set pop \n\ 156 " : "=r"(rv) : "r"(addrlo), "r"(addrhi) : "$1", "$3" ); 157 158 mips_cp0_status_write(sr); 159 160 return (rv); 161 } 162 163 static inline void 164 mips3_sw_a64(uint64_t addr, uint32_t val) 165 { 166 uint32_t addrlo, addrhi; 167 uint32_t sr; 168 169 sr = mips_cp0_status_read(); 170 mips_cp0_status_write(sr | MIPS3_SR_KX); 171 172 addrlo = addr & 0xffffffff; 173 addrhi = addr >> 32; 174 __asm__ __volatile__ (" \n\ 175 .set push \n\ 176 .set mips3 \n\ 177 .set noreorder \n\ 178 .set noat \n\ 179 dsll32 $3, %1, 0 \n\ 180 dsll32 $1, %2, 0 \n\ 181 dsrl32 $3, $3, 0 \n\ 182 or $1, $1, $3 \n\ 183 sw %0, 0($1) \n\ 184 .set pop \n\ 185 " : : "r"(val), "r"(addrlo), "r"(addrhi) : "$1", "$3" ); 186 187 mips_cp0_status_write(sr); 188 } 189 #endif /* MIPS3 || MIPS4 || MIPS64 */ 190 191 /* 192 * A vector with an entry for each mips-ISA-level dependent 193 * locore function, and macros which jump through it. 194 * 195 * XXX the macro names are chosen to be compatible with the old 196 * XXX Sprite coding-convention names used in 4.4bsd/pmax. 197 */ 198 typedef struct { 199 void (*setTLBpid)(int pid); 200 void (*TBIAP)(int); 201 void (*TBIS)(vaddr_t); 202 int (*tlbUpdate)(u_int highreg, u_int lowreg); 203 void (*wbflush)(void); 204 } mips_locore_jumpvec_t; 205 206 void mips_set_wbflush(void (*)(void)); 207 void mips_wait_idle(void); 208 209 void stacktrace(void); 210 void logstacktrace(void); 211 212 /* 213 * The "active" locore-fuction vector, and 214 */ 215 extern mips_locore_jumpvec_t mips_locore_jumpvec; 216 extern long *mips_locoresw[]; 217 218 #if defined(MIPS1) && !defined(MIPS3) && !defined(MIPS32) && !defined(MIPS64) 219 #define MachSetPID mips1_SetPID 220 #define MIPS_TBIAP() mips1_TBIAP(mips_num_tlb_entries) 221 #define MIPS_TBIS mips1_TBIS 222 #define MachTLBUpdate mips1_TLBUpdate 223 #define wbflush() mips1_wbflush() 224 #define proc_trampoline mips1_proc_trampoline 225 #elif !defined(MIPS1) && defined(MIPS3) && !defined(MIPS32) && !defined(MIPS64) && !defined(MIPS3_5900) 226 #define MachSetPID mips3_SetPID 227 #define MIPS_TBIAP() mips3_TBIAP(mips_num_tlb_entries) 228 #define MIPS_TBIS mips3_TBIS 229 #define MachTLBUpdate mips3_TLBUpdate 230 #define proc_trampoline mips3_proc_trampoline 231 #define wbflush() mips3_wbflush() 232 #elif !defined(MIPS1) && !defined(MIPS3) && defined(MIPS32) && !defined(MIPS64) 233 #define MachSetPID mips32_SetPID 234 #define MIPS_TBIAP() mips32_TBIAP(mips_num_tlb_entries) 235 #define MIPS_TBIS mips32_TBIS 236 #define MachTLBUpdate mips32_TLBUpdate 237 #define proc_trampoline mips32_proc_trampoline 238 #define wbflush() mips32_wbflush() 239 #elif !defined(MIPS1) && !defined(MIPS3) && !defined(MIPS32) && defined(MIPS64) 240 /* all common with mips3 */ 241 #define MachSetPID mips64_SetPID 242 #define MIPS_TBIAP() mips64_TBIAP(mips_num_tlb_entries) 243 #define MIPS_TBIS mips64_TBIS 244 #define MachTLBUpdate mips64_TLBUpdate 245 #define proc_trampoline mips64_proc_trampoline 246 #define wbflush() mips64_wbflush() 247 #elif !defined(MIPS1) && defined(MIPS3) && !defined(MIPS32) && !defined(MIPS64) && defined(MIPS3_5900) 248 #define MachSetPID mips5900_SetPID 249 #define MIPS_TBIAP() mips5900_TBIAP(mips_num_tlb_entries) 250 #define MIPS_TBIS mips5900_TBIS 251 #define MachTLBUpdate mips5900_TLBUpdate 252 #define proc_trampoline mips5900_proc_trampoline 253 #define wbflush() mips5900_wbflush() 254 #else 255 #define MachSetPID (*(mips_locore_jumpvec.setTLBpid)) 256 #define MIPS_TBIAP() (*(mips_locore_jumpvec.TBIAP))(mips_num_tlb_entries) 257 #define MIPS_TBIS (*(mips_locore_jumpvec.TBIS)) 258 #define MachTLBUpdate (*(mips_locore_jumpvec.tlbUpdate)) 259 #define wbflush() (*(mips_locore_jumpvec.wbflush))() 260 #define proc_trampoline (mips_locoresw[1]) 261 #endif 262 263 #define CPU_IDLE (mips_locoresw[2]) 264 265 /* cpu_switch_resume is called inside locore.S */ 266 267 /* 268 * CPU identification, from PRID register. 269 */ 270 typedef int mips_prid_t; 271 272 #define MIPS_PRID_REV(x) (((x) >> 0) & 0x00ff) 273 #define MIPS_PRID_IMPL(x) (((x) >> 8) & 0x00ff) 274 275 /* pre-MIPS32/64 */ 276 #define MIPS_PRID_RSVD(x) (((x) >> 16) & 0xffff) 277 #define MIPS_PRID_REV_MIN(x) ((MIPS_PRID_REV(x) >> 0) & 0x0f) 278 #define MIPS_PRID_REV_MAJ(x) ((MIPS_PRID_REV(x) >> 4) & 0x0f) 279 280 /* MIPS32/64 */ 281 #define MIPS_PRID_CID(x) (((x) >> 16) & 0x00ff) /* Company ID */ 282 #define MIPS_PRID_CID_PREHISTORIC 0x00 /* Not MIPS32/64 */ 283 #define MIPS_PRID_CID_MTI 0x01 /* MIPS Technologies, Inc. */ 284 #define MIPS_PRID_CID_BROADCOM 0x02 /* Broadcom */ 285 #define MIPS_PRID_CID_ALCHEMY 0x03 /* Alchemy Semiconductor */ 286 #define MIPS_PRID_CID_SIBYTE 0x04 /* SiByte */ 287 #define MIPS_PRID_CID_SANDCRAFT 0x05 /* SandCraft */ 288 #define MIPS_PRID_CID_PHILIPS 0x06 /* Philips */ 289 #define MIPS_PRID_CID_TOSHIBA 0x07 /* Toshiba */ 290 #define MIPS_PRID_CID_LSI 0x08 /* LSI */ 291 /* 0x09 unannounced */ 292 /* 0x0a unannounced */ 293 #define MIPS_PRID_CID_LEXRA 0x0b /* Lexra */ 294 #define MIPS_PRID_COPTS(x) (((x) >> 24) & 0x00ff) /* Company Options */ 295 296 #ifdef _KERNEL 297 /* 298 * Global variables used to communicate CPU type, and parameters 299 * such as cache size, from locore to higher-level code (e.g., pmap). 300 */ 301 302 extern mips_prid_t cpu_id; 303 extern mips_prid_t fpu_id; 304 extern int mips_num_tlb_entries; 305 306 void mips_pagecopy(caddr_t dst, caddr_t src); 307 void mips_pagezero(caddr_t dst); 308 309 #ifdef __HAVE_MIPS_MACHDEP_CACHE_CONFIG 310 void mips_machdep_cache_config(void); 311 #endif 312 313 /* 314 * trapframe argument passed to trap() 315 */ 316 317 #define TF_AST 0 318 #define TF_V0 1 319 #define TF_V1 2 320 #define TF_A0 3 321 #define TF_A1 4 322 #define TF_A2 5 323 #define TF_A3 6 324 #define TF_T0 7 325 #define TF_T1 8 326 #define TF_T2 9 327 #define TF_T3 10 328 329 #if defined(__mips_n32) || defined(__mips_n64) 330 #define TF_A4 11 331 #define TF_A5 12 332 #define TF_A6 13 333 #define TF_A7 14 334 #else 335 #define TF_T4 11 336 #define TF_T5 12 337 #define TF_T6 13 338 #define TF_T7 14 339 #endif /* __mips_n32 || __mips_n64 */ 340 341 #define TF_TA0 11 342 #define TF_TA1 12 343 #define TF_TA2 13 344 #define TF_TA3 14 345 346 #define TF_T8 15 347 #define TF_T9 16 348 349 #define TF_RA 17 350 #define TF_SR 18 351 #define TF_MULLO 19 352 #define TF_MULHI 20 353 #define TF_EPC 21 /* may be changed by trap() call */ 354 355 #define TF_NREGS 22 356 357 struct trapframe { 358 mips_reg_t tf_regs[TF_NREGS]; 359 u_int32_t tf_ppl; /* previous priority level */ 360 int32_t tf_pad; /* for 8 byte aligned */ 361 }; 362 363 /* 364 * Stack frame for kernel traps. four args passed in registers. 365 * A trapframe is pointed to by the 5th arg, and a dummy sixth argument 366 * is used to avoid alignment problems 367 */ 368 369 struct kernframe { 370 register_t cf_args[4 + 1]; 371 register_t cf_pad; /* (for 8 word alignment) */ 372 register_t cf_sp; 373 register_t cf_ra; 374 struct trapframe cf_frame; 375 }; 376 #endif /* _KERNEL */ 377 #endif /* _MIPS_LOCORE_H */ 378
Indexes created Tue Sep 30 06:09:59 GMT 2025