locore.h revision 1.73
1 /* $NetBSD: locore.h,v 1.73 2005/12/24 23:24:01 perry Exp $ */ 2 3 /* 4 * Copyright 1996 The Board of Trustees of The Leland Stanford 5 * Junior University. All Rights Reserved. 6 * 7 * Permission to use, copy, modify, and distribute this 8 * software and its documentation for any purpose and without 9 * fee is hereby granted, provided that the above copyright 10 * notice appear in all copies. Stanford University 11 * makes no representations about the suitability of this 12 * software for any purpose. It is provided "as is" without 13 * express or implied warranty. 14 */ 15 16 /* 17 * Jump table for MIPS CPU locore functions that are implemented 18 * differently on different generations, or instruction-level 19 * archtecture (ISA) level, the Mips family. 20 * 21 * We currently provide support for MIPS I and MIPS III. 22 */ 23 24 #ifndef _MIPS_LOCORE_H 25 #define _MIPS_LOCORE_H 26 27 #ifndef _LKM 28 #include "opt_cputype.h" 29 #endif 30 31 #include <mips/cpuregs.h> 32 33 struct tlb; 34 35 uint32_t mips_cp0_cause_read(void); 36 void mips_cp0_cause_write(uint32_t); 37 uint32_t mips_cp0_status_read(void); 38 void mips_cp0_status_write(uint32_t); 39 40 #ifdef MIPS1 41 void mips1_SetPID(int); 42 void mips1_TBIA(int); 43 void mips1_TBIAP(int); 44 void mips1_TBIS(vaddr_t); 45 int mips1_TLBUpdate(u_int, u_int); 46 void mips1_wbflush(void); 47 void mips1_proc_trampoline(void); 48 void mips1_cpu_switch_resume(void); 49 50 uint32_t tx3900_cp0_config_read(void); 51 #endif 52 53 #if defined(MIPS3) || defined(MIPS4) 54 void mips3_SetPID(int); 55 void mips3_TBIA(int); 56 void mips3_TBIAP(int); 57 void mips3_TBIS(vaddr_t); 58 int mips3_TLBUpdate(u_int, u_int); 59 void mips3_TLBRead(int, struct tlb *); 60 void mips3_TLBWriteIndexedVPS(int, struct tlb *); 61 void mips3_wbflush(void); 62 void mips3_proc_trampoline(void); 63 void mips3_cpu_switch_resume(void); 64 void mips3_pagezero(caddr_t dst); 65 66 #ifdef MIPS3_5900 67 void mips5900_SetPID(int); 68 void mips5900_TBIA(int); 69 void mips5900_TBIAP(int); 70 void mips5900_TBIS(vaddr_t); 71 int mips5900_TLBUpdate(u_int, u_int); 72 void mips5900_TLBRead(int, struct tlb *); 73 void mips5900_TLBWriteIndexedVPS(int, struct tlb *); 74 void mips5900_wbflush(void); 75 void mips5900_proc_trampoline(void); 76 void mips5900_cpu_switch_resume(void); 77 void mips5900_pagezero(caddr_t dst); 78 #endif 79 #endif 80 81 #ifdef MIPS32 82 void mips32_SetPID(int); 83 void mips32_TBIA(int); 84 void mips32_TBIAP(int); 85 void mips32_TBIS(vaddr_t); 86 int mips32_TLBUpdate(u_int, u_int); 87 void mips32_TLBRead(int, struct tlb *); 88 void mips32_TLBWriteIndexedVPS(int, struct tlb *); 89 void mips32_wbflush(void); 90 void mips32_proc_trampoline(void); 91 void mips32_cpu_switch_resume(void); 92 #endif 93 94 #ifdef MIPS64 95 void mips64_SetPID(int); 96 void mips64_TBIA(int); 97 void mips64_TBIAP(int); 98 void mips64_TBIS(vaddr_t); 99 int mips64_TLBUpdate(u_int, u_int); 100 void mips64_TLBRead(int, struct tlb *); 101 void mips64_TLBWriteIndexedVPS(int, struct tlb *); 102 void mips64_wbflush(void); 103 void mips64_proc_trampoline(void); 104 void mips64_cpu_switch_resume(void); 105 void mips64_pagezero(caddr_t dst); 106 #endif 107 108 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64) 109 uint32_t mips3_cp0_compare_read(void); 110 void mips3_cp0_compare_write(uint32_t); 111 112 uint32_t mips3_cp0_config_read(void); 113 void mips3_cp0_config_write(uint32_t); 114 #if defined(MIPS32) || defined(MIPS64) 115 uint32_t mipsNN_cp0_config1_read(void); 116 void mipsNN_cp0_config1_write(uint32_t); 117 uint32_t mipsNN_cp0_config2_read(void); 118 uint32_t mipsNN_cp0_config3_read(void); 119 #endif 120 121 uint32_t mips3_cp0_count_read(void); 122 void mips3_cp0_count_write(uint32_t); 123 124 uint32_t mips3_cp0_wired_read(void); 125 void mips3_cp0_wired_write(uint32_t); 126 void mips3_cp0_pg_mask_write(uint32_t); 127 128 uint64_t mips3_ld(uint64_t *); 129 void mips3_sd(uint64_t *, uint64_t); 130 #endif /* MIPS3 || MIPS4 || MIPS32 || MIPS64 */ 131 132 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS64) 133 static inline uint32_t mips3_lw_a64(uint64_t addr) 134 __attribute__((__unused__)); 135 static inline void mips3_sw_a64(uint64_t addr, uint32_t val) 136 __attribute__ ((__unused__)); 137 138 static inline uint32_t 139 mips3_lw_a64(uint64_t addr) 140 { 141 uint32_t addrlo, addrhi; 142 uint32_t rv; 143 uint32_t sr; 144 145 sr = mips_cp0_status_read(); 146 mips_cp0_status_write(sr | MIPS3_SR_KX); 147 148 addrlo = addr & 0xffffffff; 149 addrhi = addr >> 32; 150 __asm volatile (" \n\ 151 .set push \n\ 152 .set mips3 \n\ 153 .set noreorder \n\ 154 .set noat \n\ 155 dsll32 $3, %1, 0 \n\ 156 dsll32 $1, %2, 0 \n\ 157 dsrl32 $3, $3, 0 \n\ 158 or $1, $1, $3 \n\ 159 lw %0, 0($1) \n\ 160 .set pop \n\ 161 " : "=r"(rv) : "r"(addrlo), "r"(addrhi) : "$1", "$3" ); 162 163 mips_cp0_status_write(sr); 164 165 return (rv); 166 } 167 168 static inline void 169 mips3_sw_a64(uint64_t addr, uint32_t val) 170 { 171 uint32_t addrlo, addrhi; 172 uint32_t sr; 173 174 sr = mips_cp0_status_read(); 175 mips_cp0_status_write(sr | MIPS3_SR_KX); 176 177 addrlo = addr & 0xffffffff; 178 addrhi = addr >> 32; 179 __asm volatile (" \n\ 180 .set push \n\ 181 .set mips3 \n\ 182 .set noreorder \n\ 183 .set noat \n\ 184 dsll32 $3, %1, 0 \n\ 185 dsll32 $1, %2, 0 \n\ 186 dsrl32 $3, $3, 0 \n\ 187 or $1, $1, $3 \n\ 188 sw %0, 0($1) \n\ 189 .set pop \n\ 190 " : : "r"(val), "r"(addrlo), "r"(addrhi) : "$1", "$3" ); 191 192 mips_cp0_status_write(sr); 193 } 194 #endif /* MIPS3 || MIPS4 || MIPS64 */ 195 196 /* 197 * A vector with an entry for each mips-ISA-level dependent 198 * locore function, and macros which jump through it. 199 * 200 * XXX the macro names are chosen to be compatible with the old 201 * XXX Sprite coding-convention names used in 4.4bsd/pmax. 202 */ 203 typedef struct { 204 void (*setTLBpid)(int pid); 205 void (*TBIAP)(int); 206 void (*TBIS)(vaddr_t); 207 int (*tlbUpdate)(u_int highreg, u_int lowreg); 208 void (*wbflush)(void); 209 } mips_locore_jumpvec_t; 210 211 void mips_set_wbflush(void (*)(void)); 212 void mips_wait_idle(void); 213 214 void stacktrace(void); 215 void logstacktrace(void); 216 217 /* 218 * The "active" locore-fuction vector, and 219 */ 220 extern mips_locore_jumpvec_t mips_locore_jumpvec; 221 extern long *mips_locoresw[]; 222 223 #if defined(MIPS1) && !defined(MIPS3) && !defined(MIPS32) && !defined(MIPS64) 224 #define MachSetPID mips1_SetPID 225 #define MIPS_TBIAP() mips1_TBIAP(mips_num_tlb_entries) 226 #define MIPS_TBIS mips1_TBIS 227 #define MachTLBUpdate mips1_TLBUpdate 228 #define wbflush() mips1_wbflush() 229 #define proc_trampoline mips1_proc_trampoline 230 #elif !defined(MIPS1) && defined(MIPS3) && !defined(MIPS32) && !defined(MIPS64) && !defined(MIPS3_5900) 231 #define MachSetPID mips3_SetPID 232 #define MIPS_TBIAP() mips3_TBIAP(mips_num_tlb_entries) 233 #define MIPS_TBIS mips3_TBIS 234 #define MachTLBUpdate mips3_TLBUpdate 235 #define MachTLBWriteIndexedVPS mips3_TLBWriteIndexedVPS 236 #define proc_trampoline mips3_proc_trampoline 237 #define wbflush() mips3_wbflush() 238 #elif !defined(MIPS1) && !defined(MIPS3) && defined(MIPS32) && !defined(MIPS64) 239 #define MachSetPID mips32_SetPID 240 #define MIPS_TBIAP() mips32_TBIAP(mips_num_tlb_entries) 241 #define MIPS_TBIS mips32_TBIS 242 #define MachTLBUpdate mips32_TLBUpdate 243 #define MachTLBWriteIndexedVPS mips32_TLBWriteIndexedVPS 244 #define proc_trampoline mips32_proc_trampoline 245 #define wbflush() mips32_wbflush() 246 #elif !defined(MIPS1) && !defined(MIPS3) && !defined(MIPS32) && defined(MIPS64) 247 /* all common with mips3 */ 248 #define MachSetPID mips64_SetPID 249 #define MIPS_TBIAP() mips64_TBIAP(mips_num_tlb_entries) 250 #define MIPS_TBIS mips64_TBIS 251 #define MachTLBUpdate mips64_TLBUpdate 252 #define MachTLBWriteIndexedVPS mips64_TLBWriteIndexedVPS 253 #define proc_trampoline mips64_proc_trampoline 254 #define wbflush() mips64_wbflush() 255 #elif !defined(MIPS1) && defined(MIPS3) && !defined(MIPS32) && !defined(MIPS64) && defined(MIPS3_5900) 256 #define MachSetPID mips5900_SetPID 257 #define MIPS_TBIAP() mips5900_TBIAP(mips_num_tlb_entries) 258 #define MIPS_TBIS mips5900_TBIS 259 #define MachTLBUpdate mips5900_TLBUpdate 260 #define MachTLBWriteIndexedVPS mips5900_TLBWriteIndexedVPS 261 #define proc_trampoline mips5900_proc_trampoline 262 #define wbflush() mips5900_wbflush() 263 #else 264 #define MachSetPID (*(mips_locore_jumpvec.setTLBpid)) 265 #define MIPS_TBIAP() (*(mips_locore_jumpvec.TBIAP))(mips_num_tlb_entries) 266 #define MIPS_TBIS (*(mips_locore_jumpvec.TBIS)) 267 #define MachTLBUpdate (*(mips_locore_jumpvec.tlbUpdate)) 268 #define wbflush() (*(mips_locore_jumpvec.wbflush))() 269 #define proc_trampoline (mips_locoresw[1]) 270 #endif 271 272 #define CPU_IDLE (mips_locoresw[2]) 273 274 /* cpu_switch_resume is called inside locore.S */ 275 276 /* 277 * CPU identification, from PRID register. 278 */ 279 typedef int mips_prid_t; 280 281 #define MIPS_PRID_REV(x) (((x) >> 0) & 0x00ff) 282 #define MIPS_PRID_IMPL(x) (((x) >> 8) & 0x00ff) 283 284 /* pre-MIPS32/64 */ 285 #define MIPS_PRID_RSVD(x) (((x) >> 16) & 0xffff) 286 #define MIPS_PRID_REV_MIN(x) ((MIPS_PRID_REV(x) >> 0) & 0x0f) 287 #define MIPS_PRID_REV_MAJ(x) ((MIPS_PRID_REV(x) >> 4) & 0x0f) 288 289 /* MIPS32/64 */ 290 #define MIPS_PRID_CID(x) (((x) >> 16) & 0x00ff) /* Company ID */ 291 #define MIPS_PRID_CID_PREHISTORIC 0x00 /* Not MIPS32/64 */ 292 #define MIPS_PRID_CID_MTI 0x01 /* MIPS Technologies, Inc. */ 293 #define MIPS_PRID_CID_BROADCOM 0x02 /* Broadcom */ 294 #define MIPS_PRID_CID_ALCHEMY 0x03 /* Alchemy Semiconductor */ 295 #define MIPS_PRID_CID_SIBYTE 0x04 /* SiByte */ 296 #define MIPS_PRID_CID_SANDCRAFT 0x05 /* SandCraft */ 297 #define MIPS_PRID_CID_PHILIPS 0x06 /* Philips */ 298 #define MIPS_PRID_CID_TOSHIBA 0x07 /* Toshiba */ 299 #define MIPS_PRID_CID_LSI 0x08 /* LSI */ 300 /* 0x09 unannounced */ 301 /* 0x0a unannounced */ 302 #define MIPS_PRID_CID_LEXRA 0x0b /* Lexra */ 303 #define MIPS_PRID_COPTS(x) (((x) >> 24) & 0x00ff) /* Company Options */ 304 305 #ifdef _KERNEL 306 /* 307 * Global variables used to communicate CPU type, and parameters 308 * such as cache size, from locore to higher-level code (e.g., pmap). 309 */ 310 311 extern mips_prid_t cpu_id; 312 extern mips_prid_t fpu_id; 313 extern int mips_num_tlb_entries; 314 315 void mips_pagecopy(caddr_t dst, caddr_t src); 316 void mips_pagezero(caddr_t dst); 317 318 #ifdef __HAVE_MIPS_MACHDEP_CACHE_CONFIG 319 void mips_machdep_cache_config(void); 320 #endif 321 322 /* 323 * trapframe argument passed to trap() 324 */ 325 326 #define TF_AST 0 327 #define TF_V0 1 328 #define TF_V1 2 329 #define TF_A0 3 330 #define TF_A1 4 331 #define TF_A2 5 332 #define TF_A3 6 333 #define TF_T0 7 334 #define TF_T1 8 335 #define TF_T2 9 336 #define TF_T3 10 337 338 #if defined(__mips_n32) || defined(__mips_n64) 339 #define TF_A4 11 340 #define TF_A5 12 341 #define TF_A6 13 342 #define TF_A7 14 343 #else 344 #define TF_T4 11 345 #define TF_T5 12 346 #define TF_T6 13 347 #define TF_T7 14 348 #endif /* __mips_n32 || __mips_n64 */ 349 350 #define TF_TA0 11 351 #define TF_TA1 12 352 #define TF_TA2 13 353 #define TF_TA3 14 354 355 #define TF_T8 15 356 #define TF_T9 16 357 358 #define TF_RA 17 359 #define TF_SR 18 360 #define TF_MULLO 19 361 #define TF_MULHI 20 362 #define TF_EPC 21 /* may be changed by trap() call */ 363 364 #define TF_NREGS 22 365 366 struct trapframe { 367 mips_reg_t tf_regs[TF_NREGS]; 368 u_int32_t tf_ppl; /* previous priority level */ 369 int32_t tf_pad; /* for 8 byte aligned */ 370 }; 371 372 /* 373 * Stack frame for kernel traps. four args passed in registers. 374 * A trapframe is pointed to by the 5th arg, and a dummy sixth argument 375 * is used to avoid alignment problems 376 */ 377 378 struct kernframe { 379 register_t cf_args[4 + 1]; 380 register_t cf_pad; /* (for 8 word alignment) */ 381 register_t cf_sp; 382 register_t cf_ra; 383 struct trapframe cf_frame; 384 }; 385 #endif /* _KERNEL */ 386 #endif /* _MIPS_LOCORE_H */ 387
Indexes created Tue Sep 30 11:09:46 GMT 2025