locore.h revision 1.78.36.1.2.11
1 /* $NetBSD: locore.h,v 1.78.36.1.2.11 2010/02/01 04:16:19 matt Exp $ */ 2 3 /* 4 * Copyright 1996 The Board of Trustees of The Leland Stanford 5 * Junior University. All Rights Reserved. 6 * 7 * Permission to use, copy, modify, and distribute this 8 * software and its documentation for any purpose and without 9 * fee is hereby granted, provided that the above copyright 10 * notice appear in all copies. Stanford University 11 * makes no representations about the suitability of this 12 * software for any purpose. It is provided "as is" without 13 * express or implied warranty. 14 */ 15 16 /* 17 * Jump table for MIPS CPU locore functions that are implemented 18 * differently on different generations, or instruction-level 19 * archtecture (ISA) level, the Mips family. 20 * 21 * We currently provide support for MIPS I and MIPS III. 22 */ 23 24 #ifndef _MIPS_LOCORE_H 25 #define _MIPS_LOCORE_H 26 27 #ifndef _LKM 28 #include "opt_cputype.h" 29 #endif 30 31 #include <mips/cpuregs.h> 32 #include <mips/reg.h> 33 34 struct tlbmask; 35 36 uint32_t mips_cp0_cause_read(void); 37 void mips_cp0_cause_write(uint32_t); 38 uint32_t mips_cp0_status_read(void); 39 void mips_cp0_status_write(uint32_t); 40 41 int _splraise(int); 42 int _spllower(int); 43 int _splset(int); 44 int _splget(void); 45 void _splnone(void); 46 void _setsoftintr(int); 47 void _clrsoftintr(int); 48 49 #ifdef MIPS1 50 void mips1_tlb_set_asid(uint32_t); 51 void mips1_tlb_invalidate_all(size_t); 52 void mips1_tlb_invalidate_asids(size_t, uint32_t, uint32_t); 53 void mips1_tlb_invalidate_addr(vaddr_t); 54 int mips1_tlb_update(vaddr_t, uint32_t); 55 void mips1_tlb_read_indexed(size_t, struct tlbmask *); 56 void mips1_wbflush(void); 57 void mips1_lwp_trampoline(void); 58 void mips1_setfunc_trampoline(void); 59 void mips1_cpu_switch_resume(void); 60 61 uint32_t tx3900_cp0_config_read(void); 62 #endif 63 64 #if defined(MIPS3) || defined(MIPS4) 65 void mips3_tlb_set_asid(uint32_t); 66 void mips3_tlb_invalidate_all(size_t); 67 void mips3_tlb_invalidate_asids(size_t, uint32_t, uint32_t); 68 void mips3_tlb_invalidate_addr(vaddr_t); 69 int mips3_tlb_update(vaddr_t, uint32_t); 70 void mips3_tlb_read_indexed(size_t, struct tlbmask *); 71 void mips3_tlb_write_indexed_VPS(size_t, struct tlbmask *); 72 void mips3_wbflush(void); 73 void mips3_lwp_trampoline(void); 74 void mips3_setfunc_trampoline(void); 75 void mips3_cpu_switch_resume(void); 76 void mips3_pagezero(void *dst); 77 78 #ifdef MIPS3_5900 79 void mips5900_tlb_set_asid(uint32_t); 80 void mips5900_tlb_invalidate_all(size_t); 81 void mips5900_tlb_invalidate_asids(size_t, uint32_t, uint32_t); 82 void mips5900_tlb_invalidate_addr(vaddr_t); 83 int mips5900_tlb_update(vaddr_t, uint32_t); 84 void mips5900_tlb_read_indexed(size_t, struct tlbmask *); 85 void mips5900_tlb_write_indexed_VPS(size_t, struct tlbmask *); 86 void mips5900_wbflush(void); 87 void mips5900_lwp_trampoline(void); 88 void mips5900_setfunc_trampoline(void); 89 void mips5900_cpu_switch_resume(void); 90 void mips5900_pagezero(void *dst); 91 #endif 92 #endif 93 94 #ifdef MIPS32 95 void mips32_tlb_set_asid(uint32_t); 96 void mips32_tlb_invalidate_all(size_t); 97 void mips32_tlb_invalidate_asids(size_t, uint32_t, uint32_t); 98 void mips32_tlb_invalidate_addr(vaddr_t); 99 int mips32_tlb_update(vaddr_t, uint32_t); 100 void mips32_tlb_read_indexed(size_t, struct tlbmask *); 101 void mips32_tlb_write_indexed_VPS(size_t, struct tlbmask *); 102 void mips32_wbflush(void); 103 void mips32_lwp_trampoline(void); 104 void mips32_setfunc_trampoline(void); 105 void mips32_cpu_switch_resume(void); 106 #endif 107 108 #ifdef MIPS64 109 void mips64_tlb_set_asid(uint32_t); 110 void mips64_tlb_invalidate_all(size_t); 111 void mips64_tlb_invalidate_asids(size_t, uint32_t, uint32_t); 112 void mips64_tlb_invalidate_addr(vaddr_t); 113 int mips64_tlb_update(vaddr_t, uint32_t); 114 void mips64_tlb_read_indexed(size_t, struct tlbmask *); 115 void mips64_tlb_write_indexed_VPS(size_t, struct tlbmask *); 116 void mips64_wbflush(void); 117 void mips64_lwp_trampoline(void); 118 void mips64_setfunc_trampoline(void); 119 void mips64_cpu_switch_resume(void); 120 void mips64_pagezero(void *dst); 121 #endif 122 123 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64) 124 uint32_t mips3_cp0_compare_read(void); 125 void mips3_cp0_compare_write(uint32_t); 126 127 uint32_t mips3_cp0_config_read(void); 128 void mips3_cp0_config_write(uint32_t); 129 #if defined(MIPS32) || defined(MIPS64) 130 uint32_t mipsNN_cp0_config1_read(void); 131 void mipsNN_cp0_config1_write(uint32_t); 132 uint32_t mipsNN_cp0_config2_read(void); 133 uint32_t mipsNN_cp0_config3_read(void); 134 #endif 135 136 uint32_t mips3_cp0_count_read(void); 137 void mips3_cp0_count_write(uint32_t); 138 139 uint32_t mips3_cp0_wired_read(void); 140 void mips3_cp0_wired_write(uint32_t); 141 void mips3_cp0_pg_mask_write(uint32_t); 142 143 #if defined(__GNUC__) && !defined(__mips_o32) 144 static inline uint64_t 145 mips3_ld(const volatile uint64_t *va) 146 { 147 uint64_t rv; 148 #if defined(__mips_o32) 149 uint32_t sr; 150 151 sr = mips_cp0_status_read(); 152 mips_cp0_status_write(sr & ~MIPS_SR_INT_IE); 153 154 __asm volatile( 155 ".set push \n\t" 156 ".set mips3 \n\t" 157 ".set noreorder \n\t" 158 ".set noat \n\t" 159 "ld %M0,0(%1) \n\t" 160 "dsll32 %L0,%M0,0 \n\t" 161 "dsra32 %M0,%M0,0 \n\t" /* high word */ 162 "dsra32 %L0,%L0,0 \n\t" /* low word */ 163 "ld %0,0(%1) \n\t" 164 ".set pop" 165 : "=d"(rv) 166 : "r"(va)); 167 168 mips_cp0_status_write(sr); 169 #elif defined(_LP64) 170 rv = *va; 171 #else 172 __asm volatile("ld %0,0(%1)" : "=d"(rv) : "r"(va)); 173 #endif 174 175 return rv; 176 } 177 static inline void 178 mips3_sd(volatile uint64_t *va, uint64_t v) 179 { 180 #if defined(__mips_o32) 181 uint32_t sr; 182 183 sr = mips_cp0_status_read(); 184 mips_cp0_status_write(sr & ~MIPS_SR_INT_IE); 185 186 __asm volatile( 187 ".set push \n\t" 188 ".set mips3 \n\t" 189 ".set noreorder \n\t" 190 ".set noat \n\t" 191 "dsll32 %M0,%M0,0 \n\t" 192 "dsll32 %L0,%L0,0 \n\t" 193 "dsrl32 %L0,%L0,0 \n\t" 194 "or %0,%L0,%M0 \n\t" 195 "sd %0,0(%1) \n\t" 196 ".set pop" 197 : "=d"(v) : "0"(v), "r"(va)); 198 199 mips_cp0_status_write(sr); 200 #elif defined(_LP64) 201 *va = v; 202 #else 203 __asm volatile("sd %0,0(%1)" :: "r"(v), "r"(va)); 204 #endif 205 } 206 #else 207 uint64_t mips3_ld(volatile uint64_t *va); 208 void mips3_sd(volatile uint64_t *, uint64_t); 209 #endif /* __GNUC__ */ 210 #endif /* MIPS3 || MIPS4 || MIPS32 || MIPS64 */ 211 212 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS64) 213 static __inline uint32_t mips3_lw_a64(uint64_t addr) 214 __attribute__((__unused__)); 215 static __inline void mips3_sw_a64(uint64_t addr, uint32_t val) 216 __attribute__ ((__unused__)); 217 218 static __inline uint32_t 219 mips3_lw_a64(uint64_t addr) 220 { 221 uint32_t rv; 222 #if defined(__mips_o32) 223 uint32_t sr; 224 225 sr = mips_cp0_status_read(); 226 mips_cp0_status_write((sr & ~MIPS_SR_INT_IE) | MIPS3_SR_KX); 227 228 __asm volatile ( 229 ".set push \n\t" 230 ".set mips3 \n\t" 231 ".set noreorder \n\t" 232 ".set noat \n\t" 233 "dsll32 %M1,%M1,0 \n\t" 234 "dsll32 %L1,%L1,0 \n\t" 235 "dsrl32 %L1,%L1,0 \n\t" 236 "or %1,%M1,%L1 \n\t" 237 "lw %0, 0(%1) \n\t" 238 ".set pop" 239 : "=r"(rv), "=d"(addr) 240 : "1"(addr) 241 ); 242 243 mips_cp0_status_write(sr); 244 #elif defined(_LP64) 245 rv = *(const uint32_t *)addr; 246 #else 247 __asm volatile("lw %0, 0(%1)" : "=r"(rv) : "d"(addr)); 248 #endif 249 return (rv); 250 } 251 252 static __inline void 253 mips3_sw_a64(uint64_t addr, uint32_t val) 254 { 255 #if defined(__mips_o32) 256 uint32_t sr; 257 258 sr = mips_cp0_status_read(); 259 mips_cp0_status_write((sr & ~MIPS_SR_INT_IE) | MIPS3_SR_KX); 260 261 __asm volatile ( 262 ".set push \n\t" 263 ".set mips3 \n\t" 264 ".set noreorder \n\t" 265 ".set noat \n\t" 266 "dsll32 %M0,%M0,0 \n\t" 267 "dsll32 %L0,%L0,0 \n\t" 268 "dsrl32 %L0,%L0,0 \n\t" 269 "or %0,%M0,%L0 \n\t" 270 "sw %1, 0(%0) \n\t" 271 ".set pop" 272 : "=d"(addr): "r"(val), "0"(addr) 273 ); 274 275 mips_cp0_status_write(sr); 276 #elif defined(_LP64) 277 *(uint32_t *)addr = val; 278 #else 279 __asm volatile("sw %1, 0(%0)" :: "d"(addr), "r"(val)); 280 #endif 281 } 282 #endif /* MIPS3 || MIPS4 || MIPS64 */ 283 284 /* 285 * A vector with an entry for each mips-ISA-level dependent 286 * locore function, and macros which jump through it. 287 * 288 * XXX the macro names are chosen to be compatible with the old 289 * XXX Sprite coding-convention names used in 4.4bsd/pmax. 290 */ 291 typedef struct { 292 void (*ljv_tlb_set_asid)(uint32_t pid); 293 void (*ljv_tlb_invalidate_asids)(size_t, uint32_t, uint32_t); 294 void (*ljv_tlb_invalidate_addr)(vaddr_t); 295 int (*ljv_tlb_update)(vaddr_t, uint32_t); 296 void (*ljv_tlb_read_indexed)(size_t, struct tlbmask *); 297 void (*ljv_wbflush)(void); 298 } mips_locore_jumpvec_t; 299 300 void mips_set_wbflush(void (*)(void)); 301 void mips_wait_idle(void); 302 303 void stacktrace(void); 304 void logstacktrace(void); 305 306 struct locoresw { 307 uintptr_t lsw_cpu_switch_resume; 308 uintptr_t lsw_lwp_trampoline; 309 void (*lsw_cpu_idle)(void); 310 uintptr_t lsw_setfunc_trampoline; 311 void (*lsw_boot_secondary_processors)(void); 312 }; 313 314 struct mips_vmfreelist { 315 paddr_t fl_start; 316 paddr_t fl_end; 317 int fl_freelist; 318 }; 319 320 /* 321 * The "active" locore-fuction vector, and 322 */ 323 extern mips_locore_jumpvec_t mips_locore_jumpvec; 324 extern struct locoresw mips_locoresw; 325 326 #if defined(MIPS1) && !defined(MIPS3) && !defined(MIPS32) && !defined(MIPS64) 327 #define tlb_set_asid mips1_tlb_set_asid 328 #define tlb_invalidate_asids(asid_lo, asid_hi) \ 329 mips1_tlb_invalidate_asids(mips_options.mips_num_tlb_entries, asid_lo, asid_hi) 330 #define tlb_invalidate_addr mips1_tlb_invalidate_addr 331 #define tlb_invalidate_asid mips1_tlb_invalidate_asid 332 #define tlb_update mips1_tlb_update 333 #define tlb_read_indexed mips1_tlb_read_indexed 334 #define wbflush() mips1_wbflush() 335 #define lwp_trampoline mips1_lwp_trampoline 336 #define setfunc_trampoline mips1_setfunc_trampoline 337 #elif !defined(MIPS1) && defined(MIPS3) && !defined(MIPS32) && !defined(MIPS64) && !defined(MIPS3_5900) 338 #define tlb_set_asid mips3_tlb_set_asid 339 #define tlb_invalidate_asids(asid_lo, asid_hi) \ 340 mips3_tlb_invalidate_asids(mips_options.mips_num_tlb_entries, asid_lo, asid_hi) 341 #define tlb_invalidate_addr mips3_tlb_invalidate_addr 342 #define tlb_invalidate_asid mips3_tlb_invalidate_asid 343 #define tlb_update mips3_tlb_update 344 #define tlb_read_indexed mips3_tlb_read_indexed 345 #define tlb_write_indexed_VPS mips3_tlb_write_indexed_VPS 346 #define lwp_trampoline mips3_lwp_trampoline 347 #define setfunc_trampoline mips3_setfunc_trampoline 348 #define wbflush() mips3_wbflush() 349 #elif !defined(MIPS1) && !defined(MIPS3) && defined(MIPS32) && !defined(MIPS64) 350 #define tlb_set_asid mips32_tlb_set_asid 351 #define tlb_invalidate_asids(asid_lo, asid_hi) \ 352 mips32_tlb_invalidate_asids(mips_options.mips_num_tlb_entries, asid_lo, asid_hi) 353 #define tlb_invalidate_addr mips32_tlb_invalidate_addr 354 #define tlb_invalidate_asid mips32_tlb_invalidate_asid 355 #define tlb_update mips32_tlb_update 356 #define tlb_read_indexed mips32_tlb_read_indexed 357 #define tlb_write_indexed_VPS mips32_tlb_write_indexed_VPS 358 #define lwp_trampoline mips32_lwp_trampoline 359 #define setfunc_trampoline mips32_setfunc_trampoline 360 #define wbflush() mips32_wbflush() 361 #elif !defined(MIPS1) && !defined(MIPS3) && !defined(MIPS32) && defined(MIPS64) 362 /* all common with mips3 */ 363 #define tlb_set_asid mips64_tlb_set_asid 364 #define tlb_invalidate_asids(asid_lo, asid_hi) \ 365 mips64_tlb_invalidate_asids(mips_options.mips_num_tlb_entries, asid_lo, asid_hi) 366 #define tlb_invalidate_addr mips64_tlb_invalidate_addr 367 #define tlb_invalidate_asid mips64_tlb_invalidate_asid 368 #define tlb_update mips64_tlb_update 369 #define tlb_read_indexed mips64_tlb_read_indexed 370 #define tlb_write_indexed_VPS mips64_tlb_write_indexed_VPS 371 #define lwp_trampoline mips64_lwp_trampoline 372 #define setfunc_trampoline mips64_setfunc_trampoline 373 #define wbflush() mips64_wbflush() 374 #elif !defined(MIPS1) && defined(MIPS3) && !defined(MIPS32) && !defined(MIPS64) && defined(MIPS3_5900) 375 #define tlb_set_asid mips5900_tlb_set_asid 376 #define tlb_invalidate_asids(asid_lo, asid_hi) \ 377 mips5900_tlb_invalidate_asids(mips_options.mips_num_tlb_entries, asid_lo, asid_hi) 378 #define tlb_invalidate_addr mips5900_tlb_invalidate_addr 379 #define tlb_invalidate_asid mips5900_tlb_invalidate_asid 380 #define tlb_update mips5900_tlb_update 381 #define tlb_read_indexed mips5900_tlb_read_indexed 382 #define tlb_write_indexed_VPS mips5900_tlb_write_indexed_VPS 383 #define lwp_trampoline mips5900_lwp_trampoline 384 #define setfunc_trampoline mips5900_setfunc_trampoline 385 #define wbflush() mips5900_wbflush() 386 #else 387 #define tlb_set_asid (*(mips_locore_jumpvec.ljv_tlb_set_asid)) 388 #define tlb_invalidate_asids(asid_lo, asid_hi) \ 389 (*(mips_locore_jumpvec.ljv_tlb_invalidate_asids))(mips_options.mips_num_tlb_entries, asid_lo, asid_hi) 390 #define tlb_invalidate_addr (*(mips_locore_jumpvec.ljv_tlb_invalidate_addr)) 391 #define tlb_update (*(mips_locore_jumpvec.ljv_tlb_update)) 392 #define tlb_read_indexed (*(mips_locore_jumpvec.ljv_tlb_read_indexed)) 393 #define wbflush() (*(mips_locore_jumpvec.ljv_wbflush))() 394 #define lwp_trampoline mips_locoresw.lsw_lwp_trampoline 395 #define setfunc_trampoline mips_locoresw.lsw_setfunc_trampoline 396 #endif 397 398 #define CPU_IDLE mips_locoresw.lsw_cpu_idle 399 400 /* cpu_switch_resume is called inside locore.S */ 401 402 /* 403 * CPU identification, from PRID register. 404 */ 405 typedef int mips_prid_t; 406 407 #define MIPS_PRID_REV(x) (((x) >> 0) & 0x00ff) 408 #define MIPS_PRID_IMPL(x) (((x) >> 8) & 0x00ff) 409 410 /* pre-MIPS32/64 */ 411 #define MIPS_PRID_RSVD(x) (((x) >> 16) & 0xffff) 412 #define MIPS_PRID_REV_MIN(x) ((MIPS_PRID_REV(x) >> 0) & 0x0f) 413 #define MIPS_PRID_REV_MAJ(x) ((MIPS_PRID_REV(x) >> 4) & 0x0f) 414 415 /* MIPS32/64 */ 416 #define MIPS_PRID_CID(x) (((x) >> 16) & 0x00ff) /* Company ID */ 417 #define MIPS_PRID_CID_PREHISTORIC 0x00 /* Not MIPS32/64 */ 418 #define MIPS_PRID_CID_MTI 0x01 /* MIPS Technologies, Inc. */ 419 #define MIPS_PRID_CID_BROADCOM 0x02 /* Broadcom */ 420 #define MIPS_PRID_CID_ALCHEMY 0x03 /* Alchemy Semiconductor */ 421 #define MIPS_PRID_CID_SIBYTE 0x04 /* SiByte */ 422 #define MIPS_PRID_CID_SANDCRAFT 0x05 /* SandCraft */ 423 #define MIPS_PRID_CID_PHILIPS 0x06 /* Philips */ 424 #define MIPS_PRID_CID_TOSHIBA 0x07 /* Toshiba */ 425 #define MIPS_PRID_CID_LSI 0x08 /* LSI */ 426 /* 0x09 unannounced */ 427 /* 0x0a unannounced */ 428 #define MIPS_PRID_CID_LEXRA 0x0b /* Lexra */ 429 #define MIPS_PRID_CID_RMI 0x0c /* RMI / NetLogic */ 430 #define MIPS_PRID_COPTS(x) (((x) >> 24) & 0x00ff) /* Company Options */ 431 432 #ifdef _KERNEL 433 /* 434 * Global variables used to communicate CPU type, and parameters 435 * such as cache size, from locore to higher-level code (e.g., pmap). 436 */ 437 void mips_pagecopy(void *dst, void *src); 438 void mips_pagezero(void *dst); 439 440 #ifdef __HAVE_MIPS_MACHDEP_CACHE_CONFIG 441 void mips_machdep_cache_config(void); 442 #endif 443 444 /* 445 * trapframe argument passed to trap() 446 */ 447 448 #if 0 449 #define TF_AST 0 /* really zero */ 450 #define TF_V0 _R_V0 451 #define TF_V1 _R_V1 452 #define TF_A0 _R_A0 453 #define TF_A1 _R_A1 454 #define TF_A2 _R_A2 455 #define TF_A3 _R_A3 456 #define TF_T0 _R_T0 457 #define TF_T1 _R_T1 458 #define TF_T2 _R_T2 459 #define TF_T3 _R_T3 460 461 #if defined(__mips_n32) || defined(__mips_n64) 462 #define TF_A4 _R_A4 463 #define TF_A5 _R_A5 464 #define TF_A6 _R_A6 465 #define TF_A7 _R_A7 466 #else 467 #define TF_T4 _R_T4 468 #define TF_T5 _R_T5 469 #define TF_T6 _R_T6 470 #define TF_T7 _R_T7 471 #endif /* __mips_n32 || __mips_n64 */ 472 473 #define TF_TA0 _R_TA0 474 #define TF_TA1 _R_TA1 475 #define TF_TA2 _R_TA2 476 #define TF_TA3 _R_TA3 477 478 #define TF_T8 _R_T8 479 #define TF_T9 _R_T9 480 481 #define TF_RA _R_RA 482 #define TF_SR _R_SR 483 #define TF_MULLO _R_MULLO 484 #define TF_MULHI _R_MULLO 485 #define TF_EPC _R_PC /* may be changed by trap() call */ 486 487 #define TF_NREGS (sizeof(struct reg) / sizeof(mips_reg_t)) 488 #endif 489 490 struct trapframe { 491 struct reg tf_registers; 492 #define tf_regs tf_registers.r_regs 493 uint32_t tf_ppl; /* previous priority level */ 494 mips_reg_t tf_pad; /* for 8 byte aligned */ 495 }; 496 497 CTASSERT(sizeof(struct trapframe) % (4*sizeof(mips_reg_t)) == 0); 498 499 /* 500 * Stack frame for kernel traps. four args passed in registers. 501 * A trapframe is pointed to by the 5th arg, and a dummy sixth argument 502 * is used to avoid alignment problems 503 */ 504 505 struct kernframe { 506 #if defined(__mips_o32) || defined(__mips_o64) 507 register_t cf_args[4 + 1]; 508 #if defined(__mips_o32) 509 register_t cf_pad; /* (for 8 byte alignment) */ 510 #endif 511 #endif 512 #if defined(__mips_n32) || defined(__mips_n64) 513 register_t cf_pad[2]; /* for 16 byte alignment */ 514 #endif 515 register_t cf_sp; 516 register_t cf_ra; 517 struct trapframe cf_frame; 518 }; 519 520 CTASSERT(sizeof(struct kernframe) % (2*sizeof(mips_reg_t)) == 0); 521 522 #endif /* _KERNEL */ 523 #endif /* _MIPS_LOCORE_H */ 524
Indexes created Sat Oct 18 23:09:54 GMT 2025