locore.h revision 1.78.36.1.2.12
1 /* $NetBSD: locore.h,v 1.78.36.1.2.12 2010/02/05 07:36:51 matt Exp $ */ 2 3 /* 4 * Copyright 1996 The Board of Trustees of The Leland Stanford 5 * Junior University. All Rights Reserved. 6 * 7 * Permission to use, copy, modify, and distribute this 8 * software and its documentation for any purpose and without 9 * fee is hereby granted, provided that the above copyright 10 * notice appear in all copies. Stanford University 11 * makes no representations about the suitability of this 12 * software for any purpose. It is provided "as is" without 13 * express or implied warranty. 14 */ 15 16 /* 17 * Jump table for MIPS CPU locore functions that are implemented 18 * differently on different generations, or instruction-level 19 * archtecture (ISA) level, the Mips family. 20 * 21 * We currently provide support for MIPS I and MIPS III. 22 */ 23 24 #ifndef _MIPS_LOCORE_H 25 #define _MIPS_LOCORE_H 26 27 #ifndef _LKM 28 #include "opt_cputype.h" 29 #endif 30 31 #include <mips/cpuregs.h> 32 #include <mips/reg.h> 33 34 struct tlbmask; 35 36 uint32_t mips_cp0_cause_read(void); 37 void mips_cp0_cause_write(uint32_t); 38 uint32_t mips_cp0_status_read(void); 39 void mips_cp0_status_write(uint32_t); 40 41 int _splraise(int); 42 int _spllower(int); 43 int _splset(int); 44 int _splget(void); 45 void _splnone(void); 46 void _setsoftintr(uint32_t); 47 void _clrsoftintr(uint32_t); 48 void softint_process(uint32_t); 49 void softint_fast_dispatch(struct lwp *, int); 50 51 #ifdef MIPS1 52 void mips1_tlb_set_asid(uint32_t); 53 void mips1_tlb_invalidate_all(size_t); 54 void mips1_tlb_invalidate_asids(size_t, uint32_t, uint32_t); 55 void mips1_tlb_invalidate_addr(vaddr_t); 56 int mips1_tlb_update(vaddr_t, uint32_t); 57 void mips1_tlb_read_indexed(size_t, struct tlbmask *); 58 void mips1_wbflush(void); 59 void mips1_lwp_trampoline(void); 60 void mips1_setfunc_trampoline(void); 61 void mips1_cpu_switch_resume(void); 62 63 uint32_t tx3900_cp0_config_read(void); 64 #endif 65 66 #if defined(MIPS3) || defined(MIPS4) 67 void mips3_tlb_set_asid(uint32_t); 68 void mips3_tlb_invalidate_all(size_t); 69 void mips3_tlb_invalidate_asids(size_t, uint32_t, uint32_t); 70 void mips3_tlb_invalidate_addr(vaddr_t); 71 int mips3_tlb_update(vaddr_t, uint32_t); 72 void mips3_tlb_read_indexed(size_t, struct tlbmask *); 73 void mips3_tlb_write_indexed_VPS(size_t, struct tlbmask *); 74 void mips3_wbflush(void); 75 void mips3_lwp_trampoline(void); 76 void mips3_setfunc_trampoline(void); 77 void mips3_cpu_switch_resume(void); 78 void mips3_pagezero(void *dst); 79 80 #ifdef MIPS3_5900 81 void mips5900_tlb_set_asid(uint32_t); 82 void mips5900_tlb_invalidate_all(size_t); 83 void mips5900_tlb_invalidate_asids(size_t, uint32_t, uint32_t); 84 void mips5900_tlb_invalidate_addr(vaddr_t); 85 int mips5900_tlb_update(vaddr_t, uint32_t); 86 void mips5900_tlb_read_indexed(size_t, struct tlbmask *); 87 void mips5900_tlb_write_indexed_VPS(size_t, struct tlbmask *); 88 void mips5900_wbflush(void); 89 void mips5900_lwp_trampoline(void); 90 void mips5900_setfunc_trampoline(void); 91 void mips5900_cpu_switch_resume(void); 92 void mips5900_pagezero(void *dst); 93 #endif 94 #endif 95 96 #ifdef MIPS32 97 void mips32_tlb_set_asid(uint32_t); 98 void mips32_tlb_invalidate_all(size_t); 99 void mips32_tlb_invalidate_asids(size_t, uint32_t, uint32_t); 100 void mips32_tlb_invalidate_addr(vaddr_t); 101 int mips32_tlb_update(vaddr_t, uint32_t); 102 void mips32_tlb_read_indexed(size_t, struct tlbmask *); 103 void mips32_tlb_write_indexed_VPS(size_t, struct tlbmask *); 104 void mips32_wbflush(void); 105 void mips32_lwp_trampoline(void); 106 void mips32_setfunc_trampoline(void); 107 void mips32_cpu_switch_resume(void); 108 #endif 109 110 #ifdef MIPS64 111 void mips64_tlb_set_asid(uint32_t); 112 void mips64_tlb_invalidate_all(size_t); 113 void mips64_tlb_invalidate_asids(size_t, uint32_t, uint32_t); 114 void mips64_tlb_invalidate_addr(vaddr_t); 115 int mips64_tlb_update(vaddr_t, uint32_t); 116 void mips64_tlb_read_indexed(size_t, struct tlbmask *); 117 void mips64_tlb_write_indexed_VPS(size_t, struct tlbmask *); 118 void mips64_wbflush(void); 119 void mips64_lwp_trampoline(void); 120 void mips64_setfunc_trampoline(void); 121 void mips64_cpu_switch_resume(void); 122 void mips64_pagezero(void *dst); 123 #endif 124 125 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64) 126 uint32_t mips3_cp0_compare_read(void); 127 void mips3_cp0_compare_write(uint32_t); 128 129 uint32_t mips3_cp0_config_read(void); 130 void mips3_cp0_config_write(uint32_t); 131 #if defined(MIPS32) || defined(MIPS64) 132 uint32_t mipsNN_cp0_config1_read(void); 133 void mipsNN_cp0_config1_write(uint32_t); 134 uint32_t mipsNN_cp0_config2_read(void); 135 uint32_t mipsNN_cp0_config3_read(void); 136 #endif 137 138 uint32_t mips3_cp0_count_read(void); 139 void mips3_cp0_count_write(uint32_t); 140 141 uint32_t mips3_cp0_wired_read(void); 142 void mips3_cp0_wired_write(uint32_t); 143 void mips3_cp0_pg_mask_write(uint32_t); 144 145 #if defined(__GNUC__) && !defined(__mips_o32) 146 static inline uint64_t 147 mips3_ld(const volatile uint64_t *va) 148 { 149 uint64_t rv; 150 #if defined(__mips_o32) 151 uint32_t sr; 152 153 sr = mips_cp0_status_read(); 154 mips_cp0_status_write(sr & ~MIPS_SR_INT_IE); 155 156 __asm volatile( 157 ".set push \n\t" 158 ".set mips3 \n\t" 159 ".set noreorder \n\t" 160 ".set noat \n\t" 161 "ld %M0,0(%1) \n\t" 162 "dsll32 %L0,%M0,0 \n\t" 163 "dsra32 %M0,%M0,0 \n\t" /* high word */ 164 "dsra32 %L0,%L0,0 \n\t" /* low word */ 165 "ld %0,0(%1) \n\t" 166 ".set pop" 167 : "=d"(rv) 168 : "r"(va)); 169 170 mips_cp0_status_write(sr); 171 #elif defined(_LP64) 172 rv = *va; 173 #else 174 __asm volatile("ld %0,0(%1)" : "=d"(rv) : "r"(va)); 175 #endif 176 177 return rv; 178 } 179 static inline void 180 mips3_sd(volatile uint64_t *va, uint64_t v) 181 { 182 #if defined(__mips_o32) 183 uint32_t sr; 184 185 sr = mips_cp0_status_read(); 186 mips_cp0_status_write(sr & ~MIPS_SR_INT_IE); 187 188 __asm volatile( 189 ".set push \n\t" 190 ".set mips3 \n\t" 191 ".set noreorder \n\t" 192 ".set noat \n\t" 193 "dsll32 %M0,%M0,0 \n\t" 194 "dsll32 %L0,%L0,0 \n\t" 195 "dsrl32 %L0,%L0,0 \n\t" 196 "or %0,%L0,%M0 \n\t" 197 "sd %0,0(%1) \n\t" 198 ".set pop" 199 : "=d"(v) : "0"(v), "r"(va)); 200 201 mips_cp0_status_write(sr); 202 #elif defined(_LP64) 203 *va = v; 204 #else 205 __asm volatile("sd %0,0(%1)" :: "r"(v), "r"(va)); 206 #endif 207 } 208 #else 209 uint64_t mips3_ld(volatile uint64_t *va); 210 void mips3_sd(volatile uint64_t *, uint64_t); 211 #endif /* __GNUC__ */ 212 #endif /* MIPS3 || MIPS4 || MIPS32 || MIPS64 */ 213 214 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS64) 215 static __inline uint32_t mips3_lw_a64(uint64_t addr) 216 __attribute__((__unused__)); 217 static __inline void mips3_sw_a64(uint64_t addr, uint32_t val) 218 __attribute__ ((__unused__)); 219 220 static __inline uint32_t 221 mips3_lw_a64(uint64_t addr) 222 { 223 uint32_t rv; 224 #if defined(__mips_o32) 225 uint32_t sr; 226 227 sr = mips_cp0_status_read(); 228 mips_cp0_status_write((sr & ~MIPS_SR_INT_IE) | MIPS3_SR_KX); 229 230 __asm volatile ( 231 ".set push \n\t" 232 ".set mips3 \n\t" 233 ".set noreorder \n\t" 234 ".set noat \n\t" 235 "dsll32 %M1,%M1,0 \n\t" 236 "dsll32 %L1,%L1,0 \n\t" 237 "dsrl32 %L1,%L1,0 \n\t" 238 "or %1,%M1,%L1 \n\t" 239 "lw %0, 0(%1) \n\t" 240 ".set pop" 241 : "=r"(rv), "=d"(addr) 242 : "1"(addr) 243 ); 244 245 mips_cp0_status_write(sr); 246 #elif defined(_LP64) 247 rv = *(const uint32_t *)addr; 248 #else 249 __asm volatile("lw %0, 0(%1)" : "=r"(rv) : "d"(addr)); 250 #endif 251 return (rv); 252 } 253 254 static __inline void 255 mips3_sw_a64(uint64_t addr, uint32_t val) 256 { 257 #if defined(__mips_o32) 258 uint32_t sr; 259 260 sr = mips_cp0_status_read(); 261 mips_cp0_status_write((sr & ~MIPS_SR_INT_IE) | MIPS3_SR_KX); 262 263 __asm volatile ( 264 ".set push \n\t" 265 ".set mips3 \n\t" 266 ".set noreorder \n\t" 267 ".set noat \n\t" 268 "dsll32 %M0,%M0,0 \n\t" 269 "dsll32 %L0,%L0,0 \n\t" 270 "dsrl32 %L0,%L0,0 \n\t" 271 "or %0,%M0,%L0 \n\t" 272 "sw %1, 0(%0) \n\t" 273 ".set pop" 274 : "=d"(addr): "r"(val), "0"(addr) 275 ); 276 277 mips_cp0_status_write(sr); 278 #elif defined(_LP64) 279 *(uint32_t *)addr = val; 280 #else 281 __asm volatile("sw %1, 0(%0)" :: "d"(addr), "r"(val)); 282 #endif 283 } 284 #endif /* MIPS3 || MIPS4 || MIPS64 */ 285 286 /* 287 * A vector with an entry for each mips-ISA-level dependent 288 * locore function, and macros which jump through it. 289 * 290 * XXX the macro names are chosen to be compatible with the old 291 * XXX Sprite coding-convention names used in 4.4bsd/pmax. 292 */ 293 typedef struct { 294 void (*ljv_tlb_set_asid)(uint32_t pid); 295 void (*ljv_tlb_invalidate_asids)(size_t, uint32_t, uint32_t); 296 void (*ljv_tlb_invalidate_addr)(vaddr_t); 297 int (*ljv_tlb_update)(vaddr_t, uint32_t); 298 void (*ljv_tlb_read_indexed)(size_t, struct tlbmask *); 299 void (*ljv_wbflush)(void); 300 } mips_locore_jumpvec_t; 301 302 void mips_set_wbflush(void (*)(void)); 303 void mips_wait_idle(void); 304 305 void stacktrace(void); 306 void logstacktrace(void); 307 308 struct locoresw { 309 uintptr_t lsw_cpu_switch_resume; 310 uintptr_t lsw_lwp_trampoline; 311 void (*lsw_cpu_idle)(void); 312 uintptr_t lsw_setfunc_trampoline; 313 void (*lsw_boot_secondary_processors)(void); 314 }; 315 316 struct mips_vmfreelist { 317 paddr_t fl_start; 318 paddr_t fl_end; 319 int fl_freelist; 320 }; 321 322 /* 323 * The "active" locore-fuction vector, and 324 */ 325 extern mips_locore_jumpvec_t mips_locore_jumpvec; 326 extern struct locoresw mips_locoresw; 327 328 #if defined(MIPS1) && !defined(MIPS3) && !defined(MIPS32) && !defined(MIPS64) 329 #define tlb_set_asid mips1_tlb_set_asid 330 #define tlb_invalidate_asids(asid_lo, asid_hi) \ 331 mips1_tlb_invalidate_asids(mips_options.mips_num_tlb_entries, asid_lo, asid_hi) 332 #define tlb_invalidate_addr mips1_tlb_invalidate_addr 333 #define tlb_invalidate_asid mips1_tlb_invalidate_asid 334 #define tlb_update mips1_tlb_update 335 #define tlb_read_indexed mips1_tlb_read_indexed 336 #define wbflush() mips1_wbflush() 337 #define lwp_trampoline mips1_lwp_trampoline 338 #define setfunc_trampoline mips1_setfunc_trampoline 339 #elif !defined(MIPS1) && defined(MIPS3) && !defined(MIPS32) && !defined(MIPS64) && !defined(MIPS3_5900) 340 #define tlb_set_asid mips3_tlb_set_asid 341 #define tlb_invalidate_asids(asid_lo, asid_hi) \ 342 mips3_tlb_invalidate_asids(mips_options.mips_num_tlb_entries, asid_lo, asid_hi) 343 #define tlb_invalidate_addr mips3_tlb_invalidate_addr 344 #define tlb_invalidate_asid mips3_tlb_invalidate_asid 345 #define tlb_update mips3_tlb_update 346 #define tlb_read_indexed mips3_tlb_read_indexed 347 #define tlb_write_indexed_VPS mips3_tlb_write_indexed_VPS 348 #define lwp_trampoline mips3_lwp_trampoline 349 #define setfunc_trampoline mips3_setfunc_trampoline 350 #define wbflush() mips3_wbflush() 351 #elif !defined(MIPS1) && !defined(MIPS3) && defined(MIPS32) && !defined(MIPS64) 352 #define tlb_set_asid mips32_tlb_set_asid 353 #define tlb_invalidate_asids(asid_lo, asid_hi) \ 354 mips32_tlb_invalidate_asids(mips_options.mips_num_tlb_entries, asid_lo, asid_hi) 355 #define tlb_invalidate_addr mips32_tlb_invalidate_addr 356 #define tlb_invalidate_asid mips32_tlb_invalidate_asid 357 #define tlb_update mips32_tlb_update 358 #define tlb_read_indexed mips32_tlb_read_indexed 359 #define tlb_write_indexed_VPS mips32_tlb_write_indexed_VPS 360 #define lwp_trampoline mips32_lwp_trampoline 361 #define setfunc_trampoline mips32_setfunc_trampoline 362 #define wbflush() mips32_wbflush() 363 #elif !defined(MIPS1) && !defined(MIPS3) && !defined(MIPS32) && defined(MIPS64) 364 /* all common with mips3 */ 365 #define tlb_set_asid mips64_tlb_set_asid 366 #define tlb_invalidate_asids(asid_lo, asid_hi) \ 367 mips64_tlb_invalidate_asids(mips_options.mips_num_tlb_entries, asid_lo, asid_hi) 368 #define tlb_invalidate_addr mips64_tlb_invalidate_addr 369 #define tlb_invalidate_asid mips64_tlb_invalidate_asid 370 #define tlb_update mips64_tlb_update 371 #define tlb_read_indexed mips64_tlb_read_indexed 372 #define tlb_write_indexed_VPS mips64_tlb_write_indexed_VPS 373 #define lwp_trampoline mips64_lwp_trampoline 374 #define setfunc_trampoline mips64_setfunc_trampoline 375 #define wbflush() mips64_wbflush() 376 #elif !defined(MIPS1) && defined(MIPS3) && !defined(MIPS32) && !defined(MIPS64) && defined(MIPS3_5900) 377 #define tlb_set_asid mips5900_tlb_set_asid 378 #define tlb_invalidate_asids(asid_lo, asid_hi) \ 379 mips5900_tlb_invalidate_asids(mips_options.mips_num_tlb_entries, asid_lo, asid_hi) 380 #define tlb_invalidate_addr mips5900_tlb_invalidate_addr 381 #define tlb_invalidate_asid mips5900_tlb_invalidate_asid 382 #define tlb_update mips5900_tlb_update 383 #define tlb_read_indexed mips5900_tlb_read_indexed 384 #define tlb_write_indexed_VPS mips5900_tlb_write_indexed_VPS 385 #define lwp_trampoline mips5900_lwp_trampoline 386 #define setfunc_trampoline mips5900_setfunc_trampoline 387 #define wbflush() mips5900_wbflush() 388 #else 389 #define tlb_set_asid (*(mips_locore_jumpvec.ljv_tlb_set_asid)) 390 #define tlb_invalidate_asids(asid_lo, asid_hi) \ 391 (*(mips_locore_jumpvec.ljv_tlb_invalidate_asids))(mips_options.mips_num_tlb_entries, asid_lo, asid_hi) 392 #define tlb_invalidate_addr (*(mips_locore_jumpvec.ljv_tlb_invalidate_addr)) 393 #define tlb_update (*(mips_locore_jumpvec.ljv_tlb_update)) 394 #define tlb_read_indexed (*(mips_locore_jumpvec.ljv_tlb_read_indexed)) 395 #define wbflush() (*(mips_locore_jumpvec.ljv_wbflush))() 396 #define lwp_trampoline mips_locoresw.lsw_lwp_trampoline 397 #define setfunc_trampoline mips_locoresw.lsw_setfunc_trampoline 398 #endif 399 400 #define CPU_IDLE mips_locoresw.lsw_cpu_idle 401 402 /* cpu_switch_resume is called inside locore.S */ 403 404 /* 405 * CPU identification, from PRID register. 406 */ 407 typedef int mips_prid_t; 408 409 #define MIPS_PRID_REV(x) (((x) >> 0) & 0x00ff) 410 #define MIPS_PRID_IMPL(x) (((x) >> 8) & 0x00ff) 411 412 /* pre-MIPS32/64 */ 413 #define MIPS_PRID_RSVD(x) (((x) >> 16) & 0xffff) 414 #define MIPS_PRID_REV_MIN(x) ((MIPS_PRID_REV(x) >> 0) & 0x0f) 415 #define MIPS_PRID_REV_MAJ(x) ((MIPS_PRID_REV(x) >> 4) & 0x0f) 416 417 /* MIPS32/64 */ 418 #define MIPS_PRID_CID(x) (((x) >> 16) & 0x00ff) /* Company ID */ 419 #define MIPS_PRID_CID_PREHISTORIC 0x00 /* Not MIPS32/64 */ 420 #define MIPS_PRID_CID_MTI 0x01 /* MIPS Technologies, Inc. */ 421 #define MIPS_PRID_CID_BROADCOM 0x02 /* Broadcom */ 422 #define MIPS_PRID_CID_ALCHEMY 0x03 /* Alchemy Semiconductor */ 423 #define MIPS_PRID_CID_SIBYTE 0x04 /* SiByte */ 424 #define MIPS_PRID_CID_SANDCRAFT 0x05 /* SandCraft */ 425 #define MIPS_PRID_CID_PHILIPS 0x06 /* Philips */ 426 #define MIPS_PRID_CID_TOSHIBA 0x07 /* Toshiba */ 427 #define MIPS_PRID_CID_LSI 0x08 /* LSI */ 428 /* 0x09 unannounced */ 429 /* 0x0a unannounced */ 430 #define MIPS_PRID_CID_LEXRA 0x0b /* Lexra */ 431 #define MIPS_PRID_CID_RMI 0x0c /* RMI / NetLogic */ 432 #define MIPS_PRID_COPTS(x) (((x) >> 24) & 0x00ff) /* Company Options */ 433 434 #ifdef _KERNEL 435 /* 436 * Global variables used to communicate CPU type, and parameters 437 * such as cache size, from locore to higher-level code (e.g., pmap). 438 */ 439 void mips_pagecopy(void *dst, void *src); 440 void mips_pagezero(void *dst); 441 442 #ifdef __HAVE_MIPS_MACHDEP_CACHE_CONFIG 443 void mips_machdep_cache_config(void); 444 #endif 445 446 /* 447 * trapframe argument passed to trap() 448 */ 449 450 #if 0 451 #define TF_AST 0 /* really zero */ 452 #define TF_V0 _R_V0 453 #define TF_V1 _R_V1 454 #define TF_A0 _R_A0 455 #define TF_A1 _R_A1 456 #define TF_A2 _R_A2 457 #define TF_A3 _R_A3 458 #define TF_T0 _R_T0 459 #define TF_T1 _R_T1 460 #define TF_T2 _R_T2 461 #define TF_T3 _R_T3 462 463 #if defined(__mips_n32) || defined(__mips_n64) 464 #define TF_A4 _R_A4 465 #define TF_A5 _R_A5 466 #define TF_A6 _R_A6 467 #define TF_A7 _R_A7 468 #else 469 #define TF_T4 _R_T4 470 #define TF_T5 _R_T5 471 #define TF_T6 _R_T6 472 #define TF_T7 _R_T7 473 #endif /* __mips_n32 || __mips_n64 */ 474 475 #define TF_TA0 _R_TA0 476 #define TF_TA1 _R_TA1 477 #define TF_TA2 _R_TA2 478 #define TF_TA3 _R_TA3 479 480 #define TF_T8 _R_T8 481 #define TF_T9 _R_T9 482 483 #define TF_RA _R_RA 484 #define TF_SR _R_SR 485 #define TF_MULLO _R_MULLO 486 #define TF_MULHI _R_MULLO 487 #define TF_EPC _R_PC /* may be changed by trap() call */ 488 489 #define TF_NREGS (sizeof(struct reg) / sizeof(mips_reg_t)) 490 #endif 491 492 struct trapframe { 493 struct reg tf_registers; 494 #define tf_regs tf_registers.r_regs 495 uint32_t tf_ppl; /* previous priority level */ 496 mips_reg_t tf_pad; /* for 8 byte aligned */ 497 }; 498 499 CTASSERT(sizeof(struct trapframe) % (4*sizeof(mips_reg_t)) == 0); 500 501 /* 502 * Stack frame for kernel traps. four args passed in registers. 503 * A trapframe is pointed to by the 5th arg, and a dummy sixth argument 504 * is used to avoid alignment problems 505 */ 506 507 struct kernframe { 508 #if defined(__mips_o32) || defined(__mips_o64) 509 register_t cf_args[4 + 1]; 510 #if defined(__mips_o32) 511 register_t cf_pad; /* (for 8 byte alignment) */ 512 #endif 513 #endif 514 #if defined(__mips_n32) || defined(__mips_n64) 515 register_t cf_pad[2]; /* for 16 byte alignment */ 516 #endif 517 register_t cf_sp; 518 register_t cf_ra; 519 struct trapframe cf_frame; 520 }; 521 522 CTASSERT(sizeof(struct kernframe) % (2*sizeof(mips_reg_t)) == 0); 523 524 #endif /* _KERNEL */ 525 #endif /* _MIPS_LOCORE_H */ 526
Indexes created Sun Oct 19 19:09:49 GMT 2025