locore.h revision 1.78.36.1.2.13
1 /* $NetBSD: locore.h,v 1.78.36.1.2.13 2010/02/15 07:36:03 matt Exp $ */ 2 3 /* 4 * Copyright 1996 The Board of Trustees of The Leland Stanford 5 * Junior University. All Rights Reserved. 6 * 7 * Permission to use, copy, modify, and distribute this 8 * software and its documentation for any purpose and without 9 * fee is hereby granted, provided that the above copyright 10 * notice appear in all copies. Stanford University 11 * makes no representations about the suitability of this 12 * software for any purpose. It is provided "as is" without 13 * express or implied warranty. 14 */ 15 16 /* 17 * Jump table for MIPS CPU locore functions that are implemented 18 * differently on different generations, or instruction-level 19 * archtecture (ISA) level, the Mips family. 20 * 21 * We currently provide support for MIPS I and MIPS III. 22 */ 23 24 #ifndef _MIPS_LOCORE_H 25 #define _MIPS_LOCORE_H 26 27 #ifndef _LKM 28 #include "opt_cputype.h" 29 #endif 30 31 #include <mips/cpuregs.h> 32 #include <mips/reg.h> 33 34 struct tlbmask; 35 36 uint32_t mips_cp0_cause_read(void); 37 void mips_cp0_cause_write(uint32_t); 38 uint32_t mips_cp0_status_read(void); 39 void mips_cp0_status_write(uint32_t); 40 41 void softint_process(uint32_t); 42 void softint_fast_dispatch(struct lwp *, int); 43 44 #ifdef MIPS1 45 void mips1_tlb_set_asid(uint32_t); 46 void mips1_tlb_invalidate_all(size_t); 47 void mips1_tlb_invalidate_asids(size_t, uint32_t, uint32_t); 48 void mips1_tlb_invalidate_addr(vaddr_t); 49 int mips1_tlb_update(vaddr_t, uint32_t); 50 void mips1_tlb_read_indexed(size_t, struct tlbmask *); 51 void mips1_wbflush(void); 52 void mips1_lwp_trampoline(void); 53 void mips1_setfunc_trampoline(void); 54 void mips1_cpu_switch_resume(void); 55 56 uint32_t tx3900_cp0_config_read(void); 57 #endif 58 59 #if defined(MIPS3) || defined(MIPS4) 60 void mips3_tlb_set_asid(uint32_t); 61 void mips3_tlb_invalidate_all(size_t); 62 void mips3_tlb_invalidate_asids(size_t, uint32_t, uint32_t); 63 void mips3_tlb_invalidate_addr(vaddr_t); 64 int mips3_tlb_update(vaddr_t, uint32_t); 65 void mips3_tlb_read_indexed(size_t, struct tlbmask *); 66 void mips3_tlb_write_indexed_VPS(size_t, struct tlbmask *); 67 void mips3_wbflush(void); 68 void mips3_lwp_trampoline(void); 69 void mips3_setfunc_trampoline(void); 70 void mips3_cpu_switch_resume(void); 71 void mips3_pagezero(void *dst); 72 73 #ifdef MIPS3_5900 74 void mips5900_tlb_set_asid(uint32_t); 75 void mips5900_tlb_invalidate_all(size_t); 76 void mips5900_tlb_invalidate_asids(size_t, uint32_t, uint32_t); 77 void mips5900_tlb_invalidate_addr(vaddr_t); 78 int mips5900_tlb_update(vaddr_t, uint32_t); 79 void mips5900_tlb_read_indexed(size_t, struct tlbmask *); 80 void mips5900_tlb_write_indexed_VPS(size_t, struct tlbmask *); 81 void mips5900_wbflush(void); 82 void mips5900_lwp_trampoline(void); 83 void mips5900_setfunc_trampoline(void); 84 void mips5900_cpu_switch_resume(void); 85 void mips5900_pagezero(void *dst); 86 #endif 87 #endif 88 89 #ifdef MIPS32 90 void mips32_tlb_set_asid(uint32_t); 91 void mips32_tlb_invalidate_all(size_t); 92 void mips32_tlb_invalidate_asids(size_t, uint32_t, uint32_t); 93 void mips32_tlb_invalidate_addr(vaddr_t); 94 int mips32_tlb_update(vaddr_t, uint32_t); 95 void mips32_tlb_read_indexed(size_t, struct tlbmask *); 96 void mips32_tlb_write_indexed_VPS(size_t, struct tlbmask *); 97 void mips32_wbflush(void); 98 void mips32_lwp_trampoline(void); 99 void mips32_setfunc_trampoline(void); 100 void mips32_cpu_switch_resume(void); 101 #endif 102 103 #ifdef MIPS64 104 void mips64_tlb_set_asid(uint32_t); 105 void mips64_tlb_invalidate_all(size_t); 106 void mips64_tlb_invalidate_asids(size_t, uint32_t, uint32_t); 107 void mips64_tlb_invalidate_addr(vaddr_t); 108 int mips64_tlb_update(vaddr_t, uint32_t); 109 void mips64_tlb_read_indexed(size_t, struct tlbmask *); 110 void mips64_tlb_write_indexed_VPS(size_t, struct tlbmask *); 111 void mips64_wbflush(void); 112 void mips64_lwp_trampoline(void); 113 void mips64_setfunc_trampoline(void); 114 void mips64_cpu_switch_resume(void); 115 void mips64_pagezero(void *dst); 116 #endif 117 118 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64) 119 uint32_t mips3_cp0_compare_read(void); 120 void mips3_cp0_compare_write(uint32_t); 121 122 uint32_t mips3_cp0_config_read(void); 123 void mips3_cp0_config_write(uint32_t); 124 #if defined(MIPS32) || defined(MIPS64) 125 uint32_t mipsNN_cp0_config1_read(void); 126 void mipsNN_cp0_config1_write(uint32_t); 127 uint32_t mipsNN_cp0_config2_read(void); 128 uint32_t mipsNN_cp0_config3_read(void); 129 #endif 130 131 uint32_t mips3_cp0_count_read(void); 132 void mips3_cp0_count_write(uint32_t); 133 134 uint32_t mips3_cp0_wired_read(void); 135 void mips3_cp0_wired_write(uint32_t); 136 void mips3_cp0_pg_mask_write(uint32_t); 137 138 #if defined(__GNUC__) && !defined(__mips_o32) 139 static inline uint64_t 140 mips3_ld(const volatile uint64_t *va) 141 { 142 uint64_t rv; 143 #if defined(__mips_o32) 144 uint32_t sr; 145 146 sr = mips_cp0_status_read(); 147 mips_cp0_status_write(sr & ~MIPS_SR_INT_IE); 148 149 __asm volatile( 150 ".set push \n\t" 151 ".set mips3 \n\t" 152 ".set noreorder \n\t" 153 ".set noat \n\t" 154 "ld %M0,0(%1) \n\t" 155 "dsll32 %L0,%M0,0 \n\t" 156 "dsra32 %M0,%M0,0 \n\t" /* high word */ 157 "dsra32 %L0,%L0,0 \n\t" /* low word */ 158 "ld %0,0(%1) \n\t" 159 ".set pop" 160 : "=d"(rv) 161 : "r"(va)); 162 163 mips_cp0_status_write(sr); 164 #elif defined(_LP64) 165 rv = *va; 166 #else 167 __asm volatile("ld %0,0(%1)" : "=d"(rv) : "r"(va)); 168 #endif 169 170 return rv; 171 } 172 static inline void 173 mips3_sd(volatile uint64_t *va, uint64_t v) 174 { 175 #if defined(__mips_o32) 176 uint32_t sr; 177 178 sr = mips_cp0_status_read(); 179 mips_cp0_status_write(sr & ~MIPS_SR_INT_IE); 180 181 __asm volatile( 182 ".set push \n\t" 183 ".set mips3 \n\t" 184 ".set noreorder \n\t" 185 ".set noat \n\t" 186 "dsll32 %M0,%M0,0 \n\t" 187 "dsll32 %L0,%L0,0 \n\t" 188 "dsrl32 %L0,%L0,0 \n\t" 189 "or %0,%L0,%M0 \n\t" 190 "sd %0,0(%1) \n\t" 191 ".set pop" 192 : "=d"(v) : "0"(v), "r"(va)); 193 194 mips_cp0_status_write(sr); 195 #elif defined(_LP64) 196 *va = v; 197 #else 198 __asm volatile("sd %0,0(%1)" :: "r"(v), "r"(va)); 199 #endif 200 } 201 #else 202 uint64_t mips3_ld(volatile uint64_t *va); 203 void mips3_sd(volatile uint64_t *, uint64_t); 204 #endif /* __GNUC__ */ 205 #endif /* MIPS3 || MIPS4 || MIPS32 || MIPS64 */ 206 207 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS64) 208 static __inline uint32_t mips3_lw_a64(uint64_t addr) 209 __attribute__((__unused__)); 210 static __inline void mips3_sw_a64(uint64_t addr, uint32_t val) 211 __attribute__ ((__unused__)); 212 213 static __inline uint32_t 214 mips3_lw_a64(uint64_t addr) 215 { 216 uint32_t rv; 217 #if defined(__mips_o32) 218 uint32_t sr; 219 220 sr = mips_cp0_status_read(); 221 mips_cp0_status_write((sr & ~MIPS_SR_INT_IE) | MIPS3_SR_KX); 222 223 __asm volatile ( 224 ".set push \n\t" 225 ".set mips3 \n\t" 226 ".set noreorder \n\t" 227 ".set noat \n\t" 228 "dsll32 %M1,%M1,0 \n\t" 229 "dsll32 %L1,%L1,0 \n\t" 230 "dsrl32 %L1,%L1,0 \n\t" 231 "or %1,%M1,%L1 \n\t" 232 "lw %0, 0(%1) \n\t" 233 ".set pop" 234 : "=r"(rv), "=d"(addr) 235 : "1"(addr) 236 ); 237 238 mips_cp0_status_write(sr); 239 #elif defined(_LP64) 240 rv = *(const uint32_t *)addr; 241 #else 242 __asm volatile("lw %0, 0(%1)" : "=r"(rv) : "d"(addr)); 243 #endif 244 return (rv); 245 } 246 247 static __inline void 248 mips3_sw_a64(uint64_t addr, uint32_t val) 249 { 250 #if defined(__mips_o32) 251 uint32_t sr; 252 253 sr = mips_cp0_status_read(); 254 mips_cp0_status_write((sr & ~MIPS_SR_INT_IE) | MIPS3_SR_KX); 255 256 __asm volatile ( 257 ".set push \n\t" 258 ".set mips3 \n\t" 259 ".set noreorder \n\t" 260 ".set noat \n\t" 261 "dsll32 %M0,%M0,0 \n\t" 262 "dsll32 %L0,%L0,0 \n\t" 263 "dsrl32 %L0,%L0,0 \n\t" 264 "or %0,%M0,%L0 \n\t" 265 "sw %1, 0(%0) \n\t" 266 ".set pop" 267 : "=d"(addr): "r"(val), "0"(addr) 268 ); 269 270 mips_cp0_status_write(sr); 271 #elif defined(_LP64) 272 *(uint32_t *)addr = val; 273 #else 274 __asm volatile("sw %1, 0(%0)" :: "d"(addr), "r"(val)); 275 #endif 276 } 277 #endif /* MIPS3 || MIPS4 || MIPS64 */ 278 279 /* 280 * A vector with an entry for each mips-ISA-level dependent 281 * locore function, and macros which jump through it. 282 * 283 * XXX the macro names are chosen to be compatible with the old 284 * XXX Sprite coding-convention names used in 4.4bsd/pmax. 285 */ 286 typedef struct { 287 void (*ljv_tlb_set_asid)(uint32_t pid); 288 void (*ljv_tlb_invalidate_asids)(size_t, uint32_t, uint32_t); 289 void (*ljv_tlb_invalidate_addr)(vaddr_t); 290 int (*ljv_tlb_update)(vaddr_t, uint32_t); 291 void (*ljv_tlb_read_indexed)(size_t, struct tlbmask *); 292 void (*ljv_wbflush)(void); 293 } mips_locore_jumpvec_t; 294 295 void mips_set_wbflush(void (*)(void)); 296 void mips_wait_idle(void); 297 298 void stacktrace(void); 299 void logstacktrace(void); 300 301 struct locoresw { 302 uintptr_t lsw_cpu_switch_resume; 303 uintptr_t lsw_lwp_trampoline; 304 void (*lsw_cpu_idle)(void); 305 uintptr_t lsw_setfunc_trampoline; 306 void (*lsw_boot_secondary_processors)(void); 307 }; 308 309 struct mips_vmfreelist { 310 paddr_t fl_start; 311 paddr_t fl_end; 312 int fl_freelist; 313 }; 314 315 /* 316 * The "active" locore-fuction vector, and 317 */ 318 extern mips_locore_jumpvec_t mips_locore_jumpvec; 319 extern struct locoresw mips_locoresw; 320 321 #if defined(MIPS1) && !defined(MIPS3) && !defined(MIPS32) && !defined(MIPS64) 322 #define tlb_set_asid mips1_tlb_set_asid 323 #define tlb_invalidate_asids(asid_lo, asid_hi) \ 324 mips1_tlb_invalidate_asids(mips_options.mips_num_tlb_entries, asid_lo, asid_hi) 325 #define tlb_invalidate_addr mips1_tlb_invalidate_addr 326 #define tlb_invalidate_asid mips1_tlb_invalidate_asid 327 #define tlb_update mips1_tlb_update 328 #define tlb_read_indexed mips1_tlb_read_indexed 329 #define wbflush() mips1_wbflush() 330 #define lwp_trampoline mips1_lwp_trampoline 331 #define setfunc_trampoline mips1_setfunc_trampoline 332 #elif !defined(MIPS1) && defined(MIPS3) && !defined(MIPS32) && !defined(MIPS64) && !defined(MIPS3_5900) 333 #define tlb_set_asid mips3_tlb_set_asid 334 #define tlb_invalidate_asids(asid_lo, asid_hi) \ 335 mips3_tlb_invalidate_asids(mips_options.mips_num_tlb_entries, asid_lo, asid_hi) 336 #define tlb_invalidate_addr mips3_tlb_invalidate_addr 337 #define tlb_invalidate_asid mips3_tlb_invalidate_asid 338 #define tlb_update mips3_tlb_update 339 #define tlb_read_indexed mips3_tlb_read_indexed 340 #define tlb_write_indexed_VPS mips3_tlb_write_indexed_VPS 341 #define lwp_trampoline mips3_lwp_trampoline 342 #define setfunc_trampoline mips3_setfunc_trampoline 343 #define wbflush() mips3_wbflush() 344 #elif !defined(MIPS1) && !defined(MIPS3) && defined(MIPS32) && !defined(MIPS64) 345 #define tlb_set_asid mips32_tlb_set_asid 346 #define tlb_invalidate_asids(asid_lo, asid_hi) \ 347 mips32_tlb_invalidate_asids(mips_options.mips_num_tlb_entries, asid_lo, asid_hi) 348 #define tlb_invalidate_addr mips32_tlb_invalidate_addr 349 #define tlb_invalidate_asid mips32_tlb_invalidate_asid 350 #define tlb_update mips32_tlb_update 351 #define tlb_read_indexed mips32_tlb_read_indexed 352 #define tlb_write_indexed_VPS mips32_tlb_write_indexed_VPS 353 #define lwp_trampoline mips32_lwp_trampoline 354 #define setfunc_trampoline mips32_setfunc_trampoline 355 #define wbflush() mips32_wbflush() 356 #elif !defined(MIPS1) && !defined(MIPS3) && !defined(MIPS32) && defined(MIPS64) 357 /* all common with mips3 */ 358 #define tlb_set_asid mips64_tlb_set_asid 359 #define tlb_invalidate_asids(asid_lo, asid_hi) \ 360 mips64_tlb_invalidate_asids(mips_options.mips_num_tlb_entries, asid_lo, asid_hi) 361 #define tlb_invalidate_addr mips64_tlb_invalidate_addr 362 #define tlb_invalidate_asid mips64_tlb_invalidate_asid 363 #define tlb_update mips64_tlb_update 364 #define tlb_read_indexed mips64_tlb_read_indexed 365 #define tlb_write_indexed_VPS mips64_tlb_write_indexed_VPS 366 #define lwp_trampoline mips64_lwp_trampoline 367 #define setfunc_trampoline mips64_setfunc_trampoline 368 #define wbflush() mips64_wbflush() 369 #elif !defined(MIPS1) && defined(MIPS3) && !defined(MIPS32) && !defined(MIPS64) && defined(MIPS3_5900) 370 #define tlb_set_asid mips5900_tlb_set_asid 371 #define tlb_invalidate_asids(asid_lo, asid_hi) \ 372 mips5900_tlb_invalidate_asids(mips_options.mips_num_tlb_entries, asid_lo, asid_hi) 373 #define tlb_invalidate_addr mips5900_tlb_invalidate_addr 374 #define tlb_invalidate_asid mips5900_tlb_invalidate_asid 375 #define tlb_update mips5900_tlb_update 376 #define tlb_read_indexed mips5900_tlb_read_indexed 377 #define tlb_write_indexed_VPS mips5900_tlb_write_indexed_VPS 378 #define lwp_trampoline mips5900_lwp_trampoline 379 #define setfunc_trampoline mips5900_setfunc_trampoline 380 #define wbflush() mips5900_wbflush() 381 #else 382 #define tlb_set_asid (*(mips_locore_jumpvec.ljv_tlb_set_asid)) 383 #define tlb_invalidate_asids(asid_lo, asid_hi) \ 384 (*(mips_locore_jumpvec.ljv_tlb_invalidate_asids))(mips_options.mips_num_tlb_entries, asid_lo, asid_hi) 385 #define tlb_invalidate_addr (*(mips_locore_jumpvec.ljv_tlb_invalidate_addr)) 386 #define tlb_update (*(mips_locore_jumpvec.ljv_tlb_update)) 387 #define tlb_read_indexed (*(mips_locore_jumpvec.ljv_tlb_read_indexed)) 388 #define wbflush() (*(mips_locore_jumpvec.ljv_wbflush))() 389 #define lwp_trampoline mips_locoresw.lsw_lwp_trampoline 390 #define setfunc_trampoline mips_locoresw.lsw_setfunc_trampoline 391 #endif 392 393 #define CPU_IDLE mips_locoresw.lsw_cpu_idle 394 395 /* cpu_switch_resume is called inside locore.S */ 396 397 /* 398 * CPU identification, from PRID register. 399 */ 400 typedef int mips_prid_t; 401 402 #define MIPS_PRID_REV(x) (((x) >> 0) & 0x00ff) 403 #define MIPS_PRID_IMPL(x) (((x) >> 8) & 0x00ff) 404 405 /* pre-MIPS32/64 */ 406 #define MIPS_PRID_RSVD(x) (((x) >> 16) & 0xffff) 407 #define MIPS_PRID_REV_MIN(x) ((MIPS_PRID_REV(x) >> 0) & 0x0f) 408 #define MIPS_PRID_REV_MAJ(x) ((MIPS_PRID_REV(x) >> 4) & 0x0f) 409 410 /* MIPS32/64 */ 411 #define MIPS_PRID_CID(x) (((x) >> 16) & 0x00ff) /* Company ID */ 412 #define MIPS_PRID_CID_PREHISTORIC 0x00 /* Not MIPS32/64 */ 413 #define MIPS_PRID_CID_MTI 0x01 /* MIPS Technologies, Inc. */ 414 #define MIPS_PRID_CID_BROADCOM 0x02 /* Broadcom */ 415 #define MIPS_PRID_CID_ALCHEMY 0x03 /* Alchemy Semiconductor */ 416 #define MIPS_PRID_CID_SIBYTE 0x04 /* SiByte */ 417 #define MIPS_PRID_CID_SANDCRAFT 0x05 /* SandCraft */ 418 #define MIPS_PRID_CID_PHILIPS 0x06 /* Philips */ 419 #define MIPS_PRID_CID_TOSHIBA 0x07 /* Toshiba */ 420 #define MIPS_PRID_CID_LSI 0x08 /* LSI */ 421 /* 0x09 unannounced */ 422 /* 0x0a unannounced */ 423 #define MIPS_PRID_CID_LEXRA 0x0b /* Lexra */ 424 #define MIPS_PRID_CID_RMI 0x0c /* RMI / NetLogic */ 425 #define MIPS_PRID_COPTS(x) (((x) >> 24) & 0x00ff) /* Company Options */ 426 427 #ifdef _KERNEL 428 /* 429 * Global variables used to communicate CPU type, and parameters 430 * such as cache size, from locore to higher-level code (e.g., pmap). 431 */ 432 void mips_pagecopy(void *dst, void *src); 433 void mips_pagezero(void *dst); 434 435 #ifdef __HAVE_MIPS_MACHDEP_CACHE_CONFIG 436 void mips_machdep_cache_config(void); 437 #endif 438 439 /* 440 * trapframe argument passed to trap() 441 */ 442 443 #if 0 444 #define TF_AST 0 /* really zero */ 445 #define TF_V0 _R_V0 446 #define TF_V1 _R_V1 447 #define TF_A0 _R_A0 448 #define TF_A1 _R_A1 449 #define TF_A2 _R_A2 450 #define TF_A3 _R_A3 451 #define TF_T0 _R_T0 452 #define TF_T1 _R_T1 453 #define TF_T2 _R_T2 454 #define TF_T3 _R_T3 455 456 #if defined(__mips_n32) || defined(__mips_n64) 457 #define TF_A4 _R_A4 458 #define TF_A5 _R_A5 459 #define TF_A6 _R_A6 460 #define TF_A7 _R_A7 461 #else 462 #define TF_T4 _R_T4 463 #define TF_T5 _R_T5 464 #define TF_T6 _R_T6 465 #define TF_T7 _R_T7 466 #endif /* __mips_n32 || __mips_n64 */ 467 468 #define TF_TA0 _R_TA0 469 #define TF_TA1 _R_TA1 470 #define TF_TA2 _R_TA2 471 #define TF_TA3 _R_TA3 472 473 #define TF_T8 _R_T8 474 #define TF_T9 _R_T9 475 476 #define TF_RA _R_RA 477 #define TF_SR _R_SR 478 #define TF_MULLO _R_MULLO 479 #define TF_MULHI _R_MULLO 480 #define TF_EPC _R_PC /* may be changed by trap() call */ 481 482 #define TF_NREGS (sizeof(struct reg) / sizeof(mips_reg_t)) 483 #endif 484 485 struct trapframe { 486 struct reg tf_registers; 487 #define tf_regs tf_registers.r_regs 488 uint32_t tf_ppl; /* previous priority level */ 489 mips_reg_t tf_pad; /* for 8 byte aligned */ 490 }; 491 492 CTASSERT(sizeof(struct trapframe) % (4*sizeof(mips_reg_t)) == 0); 493 494 /* 495 * Stack frame for kernel traps. four args passed in registers. 496 * A trapframe is pointed to by the 5th arg, and a dummy sixth argument 497 * is used to avoid alignment problems 498 */ 499 500 struct kernframe { 501 #if defined(__mips_o32) || defined(__mips_o64) 502 register_t cf_args[4 + 1]; 503 #if defined(__mips_o32) 504 register_t cf_pad; /* (for 8 byte alignment) */ 505 #endif 506 #endif 507 #if defined(__mips_n32) || defined(__mips_n64) 508 register_t cf_pad[2]; /* for 16 byte alignment */ 509 #endif 510 register_t cf_sp; 511 register_t cf_ra; 512 struct trapframe cf_frame; 513 }; 514 515 CTASSERT(sizeof(struct kernframe) % (2*sizeof(mips_reg_t)) == 0); 516 517 #endif /* _KERNEL */ 518 #endif /* _MIPS_LOCORE_H */ 519
Indexes created Sun Oct 19 02:09:48 GMT 2025