locore.h revision 1.78.36.1.2.14
1 /* $NetBSD: locore.h,v 1.78.36.1.2.14 2010/02/23 20:33:47 matt Exp $ */ 2 3 /* 4 * This file should not be included by MI code!!! 5 */ 6 7 /* 8 * Copyright 1996 The Board of Trustees of The Leland Stanford 9 * Junior University. All Rights Reserved. 10 * 11 * Permission to use, copy, modify, and distribute this 12 * software and its documentation for any purpose and without 13 * fee is hereby granted, provided that the above copyright 14 * notice appear in all copies. Stanford University 15 * makes no representations about the suitability of this 16 * software for any purpose. It is provided "as is" without 17 * express or implied warranty. 18 */ 19 20 /* 21 * Jump table for MIPS CPU locore functions that are implemented 22 * differently on different generations, or instruction-level 23 * archtecture (ISA) level, the Mips family. 24 * 25 * We currently provide support for MIPS I and MIPS III. 26 */ 27 28 #ifndef _MIPS_LOCORE_H 29 #define _MIPS_LOCORE_H 30 31 #ifndef _LKM 32 #include "opt_cputype.h" 33 #endif 34 35 #include <mips/cpuregs.h> 36 #include <mips/reg.h> 37 38 struct tlbmask; 39 40 uint32_t mips_cp0_cause_read(void); 41 void mips_cp0_cause_write(uint32_t); 42 uint32_t mips_cp0_status_read(void); 43 void mips_cp0_status_write(uint32_t); 44 45 void softint_process(uint32_t); 46 void softint_fast_dispatch(struct lwp *, int); 47 48 #ifdef MIPS1 49 void mips1_tlb_set_asid(uint32_t); 50 void mips1_tlb_invalidate_all(void); 51 void mips1_tlb_invalidate_globals(void); 52 void mips1_tlb_invalidate_asids(uint32_t, uint32_t); 53 void mips1_tlb_invalidate_addr(vaddr_t); 54 int mips1_tlb_update(vaddr_t, uint32_t); 55 void mips1_tlb_read_indexed(size_t, struct tlbmask *); 56 void mips1_wbflush(void); 57 void mips1_lwp_trampoline(void); 58 void mips1_setfunc_trampoline(void); 59 void mips1_cpu_switch_resume(void); 60 61 uint32_t tx3900_cp0_config_read(void); 62 #endif 63 64 #if defined(MIPS3) || defined(MIPS4) 65 void mips3_tlb_set_asid(uint32_t); 66 void mips3_tlb_invalidate_all(void); 67 void mips3_tlb_invalidate_globals(void); 68 void mips3_tlb_invalidate_asids(uint32_t, uint32_t); 69 void mips3_tlb_invalidate_addr(vaddr_t); 70 int mips3_tlb_update(vaddr_t, uint32_t); 71 void mips3_tlb_read_indexed(size_t, struct tlbmask *); 72 void mips3_tlb_write_indexed_VPS(size_t, struct tlbmask *); 73 void mips3_wbflush(void); 74 void mips3_lwp_trampoline(void); 75 void mips3_setfunc_trampoline(void); 76 void mips3_cpu_switch_resume(void); 77 void mips3_pagezero(void *dst); 78 79 #ifdef MIPS3_5900 80 void mips5900_tlb_set_asid(uint32_t); 81 void mips5900_tlb_invalidate_all(void); 82 void mips5900_tlb_invalidate_globals(void); 83 void mips5900_tlb_invalidate_asids(uint32_t, uint32_t); 84 void mips5900_tlb_invalidate_addr(vaddr_t); 85 int mips5900_tlb_update(vaddr_t, uint32_t); 86 void mips5900_tlb_read_indexed(size_t, struct tlbmask *); 87 void mips5900_tlb_write_indexed_VPS(size_t, struct tlbmask *); 88 void mips5900_wbflush(void); 89 void mips5900_lwp_trampoline(void); 90 void mips5900_setfunc_trampoline(void); 91 void mips5900_cpu_switch_resume(void); 92 void mips5900_pagezero(void *dst); 93 #endif 94 #endif 95 96 #ifdef MIPS32 97 void mips32_tlb_set_asid(uint32_t); 98 void mips32_tlb_invalidate_all(void); 99 void mips32_tlb_invalidate_globals(void); 100 void mips32_tlb_invalidate_asids(uint32_t, uint32_t); 101 void mips32_tlb_invalidate_addr(vaddr_t); 102 int mips32_tlb_update(vaddr_t, uint32_t); 103 void mips32_tlb_read_indexed(size_t, struct tlbmask *); 104 void mips32_tlb_write_indexed_VPS(size_t, struct tlbmask *); 105 void mips32_wbflush(void); 106 void mips32_lwp_trampoline(void); 107 void mips32_setfunc_trampoline(void); 108 void mips32_cpu_switch_resume(void); 109 #endif 110 111 #ifdef MIPS64 112 void mips64_tlb_set_asid(uint32_t); 113 void mips64_tlb_invalidate_all(void); 114 void mips64_tlb_invalidate_globals(void); 115 void mips64_tlb_invalidate_asids(uint32_t, uint32_t); 116 void mips64_tlb_invalidate_addr(vaddr_t); 117 int mips64_tlb_update(vaddr_t, uint32_t); 118 void mips64_tlb_read_indexed(size_t, struct tlbmask *); 119 void mips64_tlb_write_indexed_VPS(size_t, struct tlbmask *); 120 void mips64_wbflush(void); 121 void mips64_lwp_trampoline(void); 122 void mips64_setfunc_trampoline(void); 123 void mips64_cpu_switch_resume(void); 124 void mips64_pagezero(void *dst); 125 #endif 126 127 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64) 128 uint32_t mips3_cp0_compare_read(void); 129 void mips3_cp0_compare_write(uint32_t); 130 131 uint32_t mips3_cp0_config_read(void); 132 void mips3_cp0_config_write(uint32_t); 133 #if defined(MIPS32) || defined(MIPS64) 134 uint32_t mipsNN_cp0_config1_read(void); 135 void mipsNN_cp0_config1_write(uint32_t); 136 uint32_t mipsNN_cp0_config2_read(void); 137 uint32_t mipsNN_cp0_config3_read(void); 138 #endif 139 140 uint32_t mips3_cp0_count_read(void); 141 void mips3_cp0_count_write(uint32_t); 142 143 uint32_t mips3_cp0_wired_read(void); 144 void mips3_cp0_wired_write(uint32_t); 145 void mips3_cp0_pg_mask_write(uint32_t); 146 147 #if defined(__GNUC__) && !defined(__mips_o32) 148 static inline uint64_t 149 mips3_ld(const volatile uint64_t *va) 150 { 151 uint64_t rv; 152 #if defined(__mips_o32) 153 uint32_t sr; 154 155 sr = mips_cp0_status_read(); 156 mips_cp0_status_write(sr & ~MIPS_SR_INT_IE); 157 158 __asm volatile( 159 ".set push \n\t" 160 ".set mips3 \n\t" 161 ".set noreorder \n\t" 162 ".set noat \n\t" 163 "ld %M0,0(%1) \n\t" 164 "dsll32 %L0,%M0,0 \n\t" 165 "dsra32 %M0,%M0,0 \n\t" /* high word */ 166 "dsra32 %L0,%L0,0 \n\t" /* low word */ 167 "ld %0,0(%1) \n\t" 168 ".set pop" 169 : "=d"(rv) 170 : "r"(va)); 171 172 mips_cp0_status_write(sr); 173 #elif defined(_LP64) 174 rv = *va; 175 #else 176 __asm volatile("ld %0,0(%1)" : "=d"(rv) : "r"(va)); 177 #endif 178 179 return rv; 180 } 181 static inline void 182 mips3_sd(volatile uint64_t *va, uint64_t v) 183 { 184 #if defined(__mips_o32) 185 uint32_t sr; 186 187 sr = mips_cp0_status_read(); 188 mips_cp0_status_write(sr & ~MIPS_SR_INT_IE); 189 190 __asm volatile( 191 ".set push \n\t" 192 ".set mips3 \n\t" 193 ".set noreorder \n\t" 194 ".set noat \n\t" 195 "dsll32 %M0,%M0,0 \n\t" 196 "dsll32 %L0,%L0,0 \n\t" 197 "dsrl32 %L0,%L0,0 \n\t" 198 "or %0,%L0,%M0 \n\t" 199 "sd %0,0(%1) \n\t" 200 ".set pop" 201 : "=d"(v) : "0"(v), "r"(va)); 202 203 mips_cp0_status_write(sr); 204 #elif defined(_LP64) 205 *va = v; 206 #else 207 __asm volatile("sd %0,0(%1)" :: "r"(v), "r"(va)); 208 #endif 209 } 210 #else 211 uint64_t mips3_ld(volatile uint64_t *va); 212 void mips3_sd(volatile uint64_t *, uint64_t); 213 #endif /* __GNUC__ */ 214 #endif /* MIPS3 || MIPS4 || MIPS32 || MIPS64 */ 215 216 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS64) 217 static __inline uint32_t mips3_lw_a64(uint64_t addr) 218 __attribute__((__unused__)); 219 static __inline void mips3_sw_a64(uint64_t addr, uint32_t val) 220 __attribute__ ((__unused__)); 221 222 static __inline uint32_t 223 mips3_lw_a64(uint64_t addr) 224 { 225 uint32_t rv; 226 #if defined(__mips_o32) 227 uint32_t sr; 228 229 sr = mips_cp0_status_read(); 230 mips_cp0_status_write((sr & ~MIPS_SR_INT_IE) | MIPS3_SR_KX); 231 232 __asm volatile ( 233 ".set push \n\t" 234 ".set mips3 \n\t" 235 ".set noreorder \n\t" 236 ".set noat \n\t" 237 "dsll32 %M1,%M1,0 \n\t" 238 "dsll32 %L1,%L1,0 \n\t" 239 "dsrl32 %L1,%L1,0 \n\t" 240 "or %1,%M1,%L1 \n\t" 241 "lw %0, 0(%1) \n\t" 242 ".set pop" 243 : "=r"(rv), "=d"(addr) 244 : "1"(addr) 245 ); 246 247 mips_cp0_status_write(sr); 248 #elif defined(_LP64) 249 rv = *(const uint32_t *)addr; 250 #else 251 __asm volatile("lw %0, 0(%1)" : "=r"(rv) : "d"(addr)); 252 #endif 253 return (rv); 254 } 255 256 static __inline void 257 mips3_sw_a64(uint64_t addr, uint32_t val) 258 { 259 #if defined(__mips_o32) 260 uint32_t sr; 261 262 sr = mips_cp0_status_read(); 263 mips_cp0_status_write((sr & ~MIPS_SR_INT_IE) | MIPS3_SR_KX); 264 265 __asm volatile ( 266 ".set push \n\t" 267 ".set mips3 \n\t" 268 ".set noreorder \n\t" 269 ".set noat \n\t" 270 "dsll32 %M0,%M0,0 \n\t" 271 "dsll32 %L0,%L0,0 \n\t" 272 "dsrl32 %L0,%L0,0 \n\t" 273 "or %0,%M0,%L0 \n\t" 274 "sw %1, 0(%0) \n\t" 275 ".set pop" 276 : "=d"(addr): "r"(val), "0"(addr) 277 ); 278 279 mips_cp0_status_write(sr); 280 #elif defined(_LP64) 281 *(uint32_t *)addr = val; 282 #else 283 __asm volatile("sw %1, 0(%0)" :: "d"(addr), "r"(val)); 284 #endif 285 } 286 #endif /* MIPS3 || MIPS4 || MIPS64 */ 287 288 /* 289 * A vector with an entry for each mips-ISA-level dependent 290 * locore function, and macros which jump through it. 291 */ 292 typedef struct { 293 void (*ljv_tlb_set_asid)(uint32_t pid); 294 void (*ljv_tlb_invalidate_asids)(uint32_t, uint32_t); 295 void (*ljv_tlb_invalidate_addr)(vaddr_t); 296 void (*ljv_tlb_invalidate_globals)(void); 297 void (*ljv_tlb_invalidate_all)(void); 298 int (*ljv_tlb_update)(vaddr_t, uint32_t); 299 void (*ljv_tlb_read_indexed)(size_t, struct tlbmask *); 300 void (*ljv_wbflush)(void); 301 } mips_locore_jumpvec_t; 302 303 void mips_set_wbflush(void (*)(void)); 304 void mips_wait_idle(void); 305 306 void stacktrace(void); 307 void logstacktrace(void); 308 309 struct locoresw { 310 uintptr_t lsw_cpu_switch_resume; 311 uintptr_t lsw_lwp_trampoline; 312 void (*lsw_cpu_idle)(void); 313 uintptr_t lsw_setfunc_trampoline; 314 void (*lsw_boot_secondary_processors)(void); 315 int (*lsw_send_ipi)(struct cpu_info *, int); 316 void (*lsw_cpu_offline_md)(void); 317 }; 318 319 struct mips_vmfreelist { 320 paddr_t fl_start; 321 paddr_t fl_end; 322 int fl_freelist; 323 }; 324 325 /* 326 * The "active" locore-fuction vector, and 327 */ 328 extern mips_locore_jumpvec_t mips_locore_jumpvec; 329 extern struct locoresw mips_locoresw; 330 331 #if defined(MIPS1) && !defined(MIPS3) && !defined(MIPS32) && !defined(MIPS64) 332 #define tlb_set_asid mips1_tlb_set_asid 333 #define tlb_invalidate_asids mips1_tlb_invalidate_asids 334 #define tlb_invalidate_addr mips1_tlb_invalidate_addr 335 #define tlb_invalidate_globals mips1_tlb_invalidate_globals 336 #define tlb_invalidate_all mips1_tlb_invalidate_all 337 #define tlb_update mips1_tlb_update 338 #define tlb_read_indexed mips1_tlb_read_indexed 339 #define wbflush mips1_wbflush 340 #define lwp_trampoline mips1_lwp_trampoline 341 #define setfunc_trampoline mips1_setfunc_trampoline 342 #elif !defined(MIPS1) && defined(MIPS3) && !defined(MIPS32) && !defined(MIPS64) && !defined(MIPS3_5900) 343 #define tlb_set_asid mips3_tlb_set_asid 344 #define tlb_invalidate_asids mips3_tlb_invalidate_asids 345 #define tlb_invalidate_addr mips3_tlb_invalidate_addr 346 #define tlb_invalidate_globals mips3_tlb_invalidate_globals 347 #define tlb_invalidate_all mips3_tlb_invalidate_all 348 #define tlb_update mips3_tlb_update 349 #define tlb_read_indexed mips3_tlb_read_indexed 350 #define tlb_write_indexed_VPS mips3_tlb_write_indexed_VPS 351 #define lwp_trampoline mips3_lwp_trampoline 352 #define setfunc_trampoline mips3_setfunc_trampoline 353 #define wbflush mips3_wbflush 354 #elif !defined(MIPS1) && !defined(MIPS3) && defined(MIPS32) && !defined(MIPS64) 355 #define tlb_set_asid mips32_tlb_set_asid 356 #define tlb_invalidate_asids mips32_tlb_invalidate_asids 357 #define tlb_invalidate_addr mips32_tlb_invalidate_addr 358 #define tlb_invalidate_globals mips32_tlb_invalidate_globals 359 #define tlb_invalidate_all mips32_tlb_invalidate_all 360 #define tlb_update mips32_tlb_update 361 #define tlb_read_indexed mips32_tlb_read_indexed 362 #define tlb_write_indexed_VPS mips32_tlb_write_indexed_VPS 363 #define lwp_trampoline mips32_lwp_trampoline 364 #define setfunc_trampoline mips32_setfunc_trampoline 365 #define wbflush mips32_wbflush 366 #elif !defined(MIPS1) && !defined(MIPS3) && !defined(MIPS32) && defined(MIPS64) 367 /* all common with mips3 */ 368 #define tlb_set_asid mips64_tlb_set_asid 369 #define tlb_invalidate_asids mips64_tlb_invalidate_asids 370 #define tlb_invalidate_addr mips64_tlb_invalidate_addr 371 #define tlb_invalidate_globals mips64_tlb_invalidate_globals 372 #define tlb_invalidate_all mips64_tlb_invalidate_all 373 #define tlb_update mips64_tlb_update 374 #define tlb_read_indexed mips64_tlb_read_indexed 375 #define tlb_write_indexed_VPS mips64_tlb_write_indexed_VPS 376 #define lwp_trampoline mips64_lwp_trampoline 377 #define setfunc_trampoline mips64_setfunc_trampoline 378 #define wbflush mips64_wbflush 379 #elif !defined(MIPS1) && defined(MIPS3) && !defined(MIPS32) && !defined(MIPS64) && defined(MIPS3_5900) 380 #define tlb_set_asid mips5900_tlb_set_asid 381 #define tlb_invalidate_asids mips5900_tlb_invalidate_asids 382 #define tlb_invalidate_addr mips5900_tlb_invalidate_addr 383 #define tlb_invalidate_globals mips5900_tlb_invalidate_globals 384 #define tlb_invalidate_all mips5900_tlb_invalidate_all 385 #define tlb_update mips5900_tlb_update 386 #define tlb_read_indexed mips5900_tlb_read_indexed 387 #define tlb_write_indexed_VPS mips5900_tlb_write_indexed_VPS 388 #define lwp_trampoline mips5900_lwp_trampoline 389 #define setfunc_trampoline mips5900_setfunc_trampoline 390 #define wbflush mips5900_wbflush 391 #else 392 #define tlb_set_asid (*mips_locore_jumpvec.ljv_tlb_set_asid) 393 #define tlb_invalidate_asids (*mips_locore_jumpvec.ljv_tlb_invalidate_asids) 394 #define tlb_invalidate_addr (*mips_locore_jumpvec.ljv_tlb_invalidate_addr) 395 #define tlb_invalidate_globals (*mips_locore_jumpvec.ljv_tlb_invalidate_globals) 396 #define tlb_invalidate_all (*mips_locore_jumpvec.ljv_tlb_invalidate_all) 397 #define tlb_update (*mips_locore_jumpvec.ljv_tlb_update) 398 #define tlb_read_indexed (*mips_locore_jumpvec.ljv_tlb_read_indexed) 399 #define wbflush (*mips_locore_jumpvec.ljv_wbflush) 400 #define lwp_trampoline mips_locoresw.lsw_lwp_trampoline 401 #define setfunc_trampoline mips_locoresw.lsw_setfunc_trampoline 402 #endif 403 404 #define CPU_IDLE mips_locoresw.lsw_cpu_idle 405 406 /* cpu_switch_resume is called inside locore.S */ 407 408 /* 409 * CPU identification, from PRID register. 410 */ 411 #define MIPS_PRID_REV(x) (((x) >> 0) & 0x00ff) 412 #define MIPS_PRID_IMPL(x) (((x) >> 8) & 0x00ff) 413 414 /* pre-MIPS32/64 */ 415 #define MIPS_PRID_RSVD(x) (((x) >> 16) & 0xffff) 416 #define MIPS_PRID_REV_MIN(x) ((MIPS_PRID_REV(x) >> 0) & 0x0f) 417 #define MIPS_PRID_REV_MAJ(x) ((MIPS_PRID_REV(x) >> 4) & 0x0f) 418 419 /* MIPS32/64 */ 420 #define MIPS_PRID_CID(x) (((x) >> 16) & 0x00ff) /* Company ID */ 421 #define MIPS_PRID_CID_PREHISTORIC 0x00 /* Not MIPS32/64 */ 422 #define MIPS_PRID_CID_MTI 0x01 /* MIPS Technologies, Inc. */ 423 #define MIPS_PRID_CID_BROADCOM 0x02 /* Broadcom */ 424 #define MIPS_PRID_CID_ALCHEMY 0x03 /* Alchemy Semiconductor */ 425 #define MIPS_PRID_CID_SIBYTE 0x04 /* SiByte */ 426 #define MIPS_PRID_CID_SANDCRAFT 0x05 /* SandCraft */ 427 #define MIPS_PRID_CID_PHILIPS 0x06 /* Philips */ 428 #define MIPS_PRID_CID_TOSHIBA 0x07 /* Toshiba */ 429 #define MIPS_PRID_CID_LSI 0x08 /* LSI */ 430 /* 0x09 unannounced */ 431 /* 0x0a unannounced */ 432 #define MIPS_PRID_CID_LEXRA 0x0b /* Lexra */ 433 #define MIPS_PRID_CID_RMI 0x0c /* RMI / NetLogic */ 434 #define MIPS_PRID_COPTS(x) (((x) >> 24) & 0x00ff) /* Company Options */ 435 436 #ifdef _KERNEL 437 /* 438 * Global variables used to communicate CPU type, and parameters 439 * such as cache size, from locore to higher-level code (e.g., pmap). 440 */ 441 void mips_pagecopy(void *dst, void *src); 442 void mips_pagezero(void *dst); 443 444 #ifdef __HAVE_MIPS_MACHDEP_CACHE_CONFIG 445 void mips_machdep_cache_config(void); 446 #endif 447 448 /* 449 * trapframe argument passed to trap() 450 */ 451 452 #if 0 453 #define TF_AST 0 /* really zero */ 454 #define TF_V0 _R_V0 455 #define TF_V1 _R_V1 456 #define TF_A0 _R_A0 457 #define TF_A1 _R_A1 458 #define TF_A2 _R_A2 459 #define TF_A3 _R_A3 460 #define TF_T0 _R_T0 461 #define TF_T1 _R_T1 462 #define TF_T2 _R_T2 463 #define TF_T3 _R_T3 464 465 #if defined(__mips_n32) || defined(__mips_n64) 466 #define TF_A4 _R_A4 467 #define TF_A5 _R_A5 468 #define TF_A6 _R_A6 469 #define TF_A7 _R_A7 470 #else 471 #define TF_T4 _R_T4 472 #define TF_T5 _R_T5 473 #define TF_T6 _R_T6 474 #define TF_T7 _R_T7 475 #endif /* __mips_n32 || __mips_n64 */ 476 477 #define TF_TA0 _R_TA0 478 #define TF_TA1 _R_TA1 479 #define TF_TA2 _R_TA2 480 #define TF_TA3 _R_TA3 481 482 #define TF_T8 _R_T8 483 #define TF_T9 _R_T9 484 485 #define TF_RA _R_RA 486 #define TF_SR _R_SR 487 #define TF_MULLO _R_MULLO 488 #define TF_MULHI _R_MULLO 489 #define TF_EPC _R_PC /* may be changed by trap() call */ 490 491 #define TF_NREGS (sizeof(struct reg) / sizeof(mips_reg_t)) 492 #endif 493 494 struct trapframe { 495 struct reg tf_registers; 496 #define tf_regs tf_registers.r_regs 497 uint32_t tf_ppl; /* previous priority level */ 498 mips_reg_t tf_pad; /* for 8 byte aligned */ 499 }; 500 501 CTASSERT(sizeof(struct trapframe) % (4*sizeof(mips_reg_t)) == 0); 502 503 /* 504 * Stack frame for kernel traps. four args passed in registers. 505 * A trapframe is pointed to by the 5th arg, and a dummy sixth argument 506 * is used to avoid alignment problems 507 */ 508 509 struct kernframe { 510 #if defined(__mips_o32) || defined(__mips_o64) 511 register_t cf_args[4 + 1]; 512 #if defined(__mips_o32) 513 register_t cf_pad; /* (for 8 byte alignment) */ 514 #endif 515 #endif 516 #if defined(__mips_n32) || defined(__mips_n64) 517 register_t cf_pad[2]; /* for 16 byte alignment */ 518 #endif 519 register_t cf_sp; 520 register_t cf_ra; 521 struct trapframe cf_frame; 522 }; 523 524 CTASSERT(sizeof(struct kernframe) % (2*sizeof(mips_reg_t)) == 0); 525 526 #endif /* _KERNEL */ 527 #endif /* _MIPS_LOCORE_H */ 528
Indexes created Mon Oct 20 10:10:01 GMT 2025