locore.h revision 1.78.36.1.2.16
1 /* $NetBSD: locore.h,v 1.78.36.1.2.16 2010/02/27 07:58:52 matt Exp $ */ 2 3 /* 4 * This file should not be included by MI code!!! 5 */ 6 7 /* 8 * Copyright 1996 The Board of Trustees of The Leland Stanford 9 * Junior University. All Rights Reserved. 10 * 11 * Permission to use, copy, modify, and distribute this 12 * software and its documentation for any purpose and without 13 * fee is hereby granted, provided that the above copyright 14 * notice appear in all copies. Stanford University 15 * makes no representations about the suitability of this 16 * software for any purpose. It is provided "as is" without 17 * express or implied warranty. 18 */ 19 20 /* 21 * Jump table for MIPS CPU locore functions that are implemented 22 * differently on different generations, or instruction-level 23 * archtecture (ISA) level, the Mips family. 24 * 25 * We currently provide support for MIPS I and MIPS III. 26 */ 27 28 #ifndef _MIPS_LOCORE_H 29 #define _MIPS_LOCORE_H 30 31 #ifndef _LKM 32 #include "opt_cputype.h" 33 #endif 34 35 #include <mips/cpuregs.h> 36 #include <mips/reg.h> 37 38 struct tlbmask; 39 40 uint32_t mips_cp0_cause_read(void); 41 void mips_cp0_cause_write(uint32_t); 42 uint32_t mips_cp0_status_read(void); 43 void mips_cp0_status_write(uint32_t); 44 45 void softint_process(uint32_t); 46 void softint_fast_dispatch(struct lwp *, int); 47 48 typedef bool (*mips_fixup_callback_t)(int32_t, uint32_t [2]); 49 50 bool mips_fixup_exceptions(mips_fixup_callback_t); 51 bool mips_fixup_zero_relative(int32_t, uint32_t [2]); 52 53 #ifdef MIPS1 54 void mips1_tlb_set_asid(uint32_t); 55 void mips1_tlb_invalidate_all(void); 56 void mips1_tlb_invalidate_globals(void); 57 void mips1_tlb_invalidate_asids(uint32_t, uint32_t); 58 void mips1_tlb_invalidate_addr(vaddr_t); 59 u_int mips1_tlb_record_asids(u_long *, uint32_t); 60 int mips1_tlb_update(vaddr_t, uint32_t); 61 void mips1_tlb_enter(size_t, vaddr_t, uint32_t); 62 void mips1_tlb_read_indexed(size_t, struct tlbmask *); 63 void mips1_wbflush(void); 64 void mips1_lwp_trampoline(void); 65 void mips1_setfunc_trampoline(void); 66 void mips1_cpu_switch_resume(struct lwp *); 67 68 uint32_t tx3900_cp0_config_read(void); 69 #endif 70 71 #if defined(MIPS3) || defined(MIPS4) 72 void mips3_tlb_set_asid(uint32_t); 73 void mips3_tlb_invalidate_all(void); 74 void mips3_tlb_invalidate_globals(void); 75 void mips3_tlb_invalidate_asids(uint32_t, uint32_t); 76 void mips3_tlb_invalidate_addr(vaddr_t); 77 u_int mips3_tlb_record_asids(u_long *, uint32_t); 78 int mips3_tlb_update(vaddr_t, uint32_t); 79 void mips3_tlb_enter(size_t, vaddr_t, uint32_t); 80 void mips3_tlb_read_indexed(size_t, struct tlbmask *); 81 void mips3_tlb_write_indexed_VPS(size_t, struct tlbmask *); 82 void mips3_wbflush(void); 83 void mips3_lwp_trampoline(void); 84 void mips3_setfunc_trampoline(void); 85 void mips3_cpu_switch_resume(struct lwp *); 86 void mips3_pagezero(void *dst); 87 88 #ifdef MIPS3_5900 89 void mips5900_tlb_set_asid(uint32_t); 90 void mips5900_tlb_invalidate_all(void); 91 void mips5900_tlb_invalidate_globals(void); 92 void mips5900_tlb_invalidate_asids(uint32_t, uint32_t); 93 void mips5900_tlb_invalidate_addr(vaddr_t); 94 u_int mips5900_tlb_record_asids(u_long *, uint32_t); 95 int mips5900_tlb_update(vaddr_t, uint32_t); 96 void mips5900_tlb_enter(size_t, vaddr_t, uint32_t); 97 void mips5900_tlb_read_indexed(size_t, struct tlbmask *); 98 void mips5900_tlb_write_indexed_VPS(size_t, struct tlbmask *); 99 void mips5900_wbflush(void); 100 void mips5900_lwp_trampoline(void); 101 void mips5900_setfunc_trampoline(void); 102 void mips5900_cpu_switch_resume(struct lwp *); 103 void mips5900_pagezero(void *dst); 104 #endif 105 #endif 106 107 #ifdef MIPS32 108 void mips32_tlb_set_asid(uint32_t); 109 void mips32_tlb_invalidate_all(void); 110 void mips32_tlb_invalidate_globals(void); 111 void mips32_tlb_invalidate_asids(uint32_t, uint32_t); 112 void mips32_tlb_invalidate_addr(vaddr_t); 113 u_int mips32_tlb_record_asids(u_long *, uint32_t); 114 int mips32_tlb_update(vaddr_t, uint32_t); 115 void mips32_tlb_enter(size_t, vaddr_t, uint32_t); 116 void mips32_tlb_read_indexed(size_t, struct tlbmask *); 117 void mips32_tlb_write_indexed_VPS(size_t, struct tlbmask *); 118 void mips32_wbflush(void); 119 void mips32_lwp_trampoline(void); 120 void mips32_setfunc_trampoline(void); 121 void mips32_cpu_switch_resume(struct lwp *); 122 #endif 123 124 #ifdef MIPS64 125 void mips64_tlb_set_asid(uint32_t); 126 void mips64_tlb_invalidate_all(void); 127 void mips64_tlb_invalidate_globals(void); 128 void mips64_tlb_invalidate_asids(uint32_t, uint32_t); 129 void mips64_tlb_invalidate_addr(vaddr_t); 130 u_int mips64_tlb_record_asids(u_long *, uint32_t); 131 int mips64_tlb_update(vaddr_t, uint32_t); 132 void mips64_tlb_enter(size_t, vaddr_t, uint32_t); 133 void mips64_tlb_read_indexed(size_t, struct tlbmask *); 134 void mips64_tlb_write_indexed_VPS(size_t, struct tlbmask *); 135 void mips64_wbflush(void); 136 void mips64_lwp_trampoline(void); 137 void mips64_setfunc_trampoline(void); 138 void mips64_cpu_switch_resume(struct lwp *); 139 void mips64_pagezero(void *dst); 140 #endif 141 142 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64) 143 uint32_t mips3_cp0_compare_read(void); 144 void mips3_cp0_compare_write(uint32_t); 145 146 uint32_t mips3_cp0_config_read(void); 147 void mips3_cp0_config_write(uint32_t); 148 #if defined(MIPS32) || defined(MIPS64) 149 uint32_t mipsNN_cp0_config1_read(void); 150 void mipsNN_cp0_config1_write(uint32_t); 151 uint32_t mipsNN_cp0_config2_read(void); 152 uint32_t mipsNN_cp0_config3_read(void); 153 #endif 154 155 uint32_t mips3_cp0_count_read(void); 156 void mips3_cp0_count_write(uint32_t); 157 158 uint32_t mips3_cp0_wired_read(void); 159 void mips3_cp0_wired_write(uint32_t); 160 void mips3_cp0_pg_mask_write(uint32_t); 161 162 #if defined(__GNUC__) && !defined(__mips_o32) 163 static inline uint64_t 164 mips3_ld(const volatile uint64_t *va) 165 { 166 uint64_t rv; 167 #if defined(__mips_o32) 168 uint32_t sr; 169 170 sr = mips_cp0_status_read(); 171 mips_cp0_status_write(sr & ~MIPS_SR_INT_IE); 172 173 __asm volatile( 174 ".set push \n\t" 175 ".set mips3 \n\t" 176 ".set noreorder \n\t" 177 ".set noat \n\t" 178 "ld %M0,0(%1) \n\t" 179 "dsll32 %L0,%M0,0 \n\t" 180 "dsra32 %M0,%M0,0 \n\t" /* high word */ 181 "dsra32 %L0,%L0,0 \n\t" /* low word */ 182 "ld %0,0(%1) \n\t" 183 ".set pop" 184 : "=d"(rv) 185 : "r"(va)); 186 187 mips_cp0_status_write(sr); 188 #elif defined(_LP64) 189 rv = *va; 190 #else 191 __asm volatile("ld %0,0(%1)" : "=d"(rv) : "r"(va)); 192 #endif 193 194 return rv; 195 } 196 static inline void 197 mips3_sd(volatile uint64_t *va, uint64_t v) 198 { 199 #if defined(__mips_o32) 200 uint32_t sr; 201 202 sr = mips_cp0_status_read(); 203 mips_cp0_status_write(sr & ~MIPS_SR_INT_IE); 204 205 __asm volatile( 206 ".set push \n\t" 207 ".set mips3 \n\t" 208 ".set noreorder \n\t" 209 ".set noat \n\t" 210 "dsll32 %M0,%M0,0 \n\t" 211 "dsll32 %L0,%L0,0 \n\t" 212 "dsrl32 %L0,%L0,0 \n\t" 213 "or %0,%L0,%M0 \n\t" 214 "sd %0,0(%1) \n\t" 215 ".set pop" 216 : "=d"(v) : "0"(v), "r"(va)); 217 218 mips_cp0_status_write(sr); 219 #elif defined(_LP64) 220 *va = v; 221 #else 222 __asm volatile("sd %0,0(%1)" :: "r"(v), "r"(va)); 223 #endif 224 } 225 #else 226 uint64_t mips3_ld(volatile uint64_t *va); 227 void mips3_sd(volatile uint64_t *, uint64_t); 228 #endif /* __GNUC__ */ 229 #endif /* MIPS3 || MIPS4 || MIPS32 || MIPS64 */ 230 231 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS64) 232 static __inline uint32_t mips3_lw_a64(uint64_t addr) 233 __attribute__((__unused__)); 234 static __inline void mips3_sw_a64(uint64_t addr, uint32_t val) 235 __attribute__ ((__unused__)); 236 237 static __inline uint32_t 238 mips3_lw_a64(uint64_t addr) 239 { 240 uint32_t rv; 241 #if defined(__mips_o32) 242 uint32_t sr; 243 244 sr = mips_cp0_status_read(); 245 mips_cp0_status_write((sr & ~MIPS_SR_INT_IE) | MIPS3_SR_KX); 246 247 __asm volatile ( 248 ".set push \n\t" 249 ".set mips3 \n\t" 250 ".set noreorder \n\t" 251 ".set noat \n\t" 252 "dsll32 %M1,%M1,0 \n\t" 253 "dsll32 %L1,%L1,0 \n\t" 254 "dsrl32 %L1,%L1,0 \n\t" 255 "or %1,%M1,%L1 \n\t" 256 "lw %0, 0(%1) \n\t" 257 ".set pop" 258 : "=r"(rv), "=d"(addr) 259 : "1"(addr) 260 ); 261 262 mips_cp0_status_write(sr); 263 #elif defined(_LP64) 264 rv = *(const uint32_t *)addr; 265 #else 266 __asm volatile("lw %0, 0(%1)" : "=r"(rv) : "d"(addr)); 267 #endif 268 return (rv); 269 } 270 271 static __inline void 272 mips3_sw_a64(uint64_t addr, uint32_t val) 273 { 274 #if defined(__mips_o32) 275 uint32_t sr; 276 277 sr = mips_cp0_status_read(); 278 mips_cp0_status_write((sr & ~MIPS_SR_INT_IE) | MIPS3_SR_KX); 279 280 __asm volatile ( 281 ".set push \n\t" 282 ".set mips3 \n\t" 283 ".set noreorder \n\t" 284 ".set noat \n\t" 285 "dsll32 %M0,%M0,0 \n\t" 286 "dsll32 %L0,%L0,0 \n\t" 287 "dsrl32 %L0,%L0,0 \n\t" 288 "or %0,%M0,%L0 \n\t" 289 "sw %1, 0(%0) \n\t" 290 ".set pop" 291 : "=d"(addr): "r"(val), "0"(addr) 292 ); 293 294 mips_cp0_status_write(sr); 295 #elif defined(_LP64) 296 *(uint32_t *)addr = val; 297 #else 298 __asm volatile("sw %1, 0(%0)" :: "d"(addr), "r"(val)); 299 #endif 300 } 301 #endif /* MIPS3 || MIPS4 || MIPS64 */ 302 303 /* 304 * A vector with an entry for each mips-ISA-level dependent 305 * locore function, and macros which jump through it. 306 */ 307 typedef struct { 308 void (*ljv_tlb_set_asid)(uint32_t pid); 309 void (*ljv_tlb_invalidate_asids)(uint32_t, uint32_t); 310 void (*ljv_tlb_invalidate_addr)(vaddr_t); 311 void (*ljv_tlb_invalidate_globals)(void); 312 void (*ljv_tlb_invalidate_all)(void); 313 u_int (*ljv_tlb_record_asids)(u_long *, uint32_t); 314 int (*ljv_tlb_update)(vaddr_t, uint32_t); 315 void (*ljv_tlb_enter)(size_t, vaddr_t, uint32_t); 316 void (*ljv_tlb_read_indexed)(size_t, struct tlbmask *); 317 void (*ljv_wbflush)(void); 318 } mips_locore_jumpvec_t; 319 320 void mips_set_wbflush(void (*)(void)); 321 void mips_wait_idle(void); 322 323 void stacktrace(void); 324 void logstacktrace(void); 325 326 struct locoresw { 327 void (*lsw_cpu_switch_resume)(struct lwp *); 328 uintptr_t lsw_lwp_trampoline; 329 void (*lsw_cpu_idle)(void); 330 uintptr_t lsw_setfunc_trampoline; 331 void (*lsw_boot_secondary_processors)(void); 332 int (*lsw_send_ipi)(struct cpu_info *, int); 333 void (*lsw_cpu_offline_md)(void); 334 }; 335 336 struct mips_vmfreelist { 337 paddr_t fl_start; 338 paddr_t fl_end; 339 int fl_freelist; 340 }; 341 342 /* 343 * The "active" locore-fuction vector, and 344 */ 345 extern mips_locore_jumpvec_t mips_locore_jumpvec; 346 extern struct locoresw mips_locoresw; 347 348 #if defined(MIPS1) && !defined(MIPS3) && !defined(MIPS32) && !defined(MIPS64) 349 #define tlb_set_asid mips1_tlb_set_asid 350 #define tlb_invalidate_asids mips1_tlb_invalidate_asids 351 #define tlb_invalidate_addr mips1_tlb_invalidate_addr 352 #define tlb_invalidate_globals mips1_tlb_invalidate_globals 353 #define tlb_invalidate_all mips1_tlb_invalidate_all 354 #define tlb_record_asids mips1_tlb_record_asids 355 #define tlb_update mips1_tlb_update 356 #define tlb_enter mips1_tlb_enter 357 #define tlb_read_indexed mips1_tlb_read_indexed 358 #define wbflush mips1_wbflush 359 #define lwp_trampoline mips1_lwp_trampoline 360 #define setfunc_trampoline mips1_setfunc_trampoline 361 #elif !defined(MIPS1) && defined(MIPS3) && !defined(MIPS32) && !defined(MIPS64) && !defined(MIPS3_5900) 362 #define tlb_set_asid mips3_tlb_set_asid 363 #define tlb_invalidate_asids mips3_tlb_invalidate_asids 364 #define tlb_invalidate_addr mips3_tlb_invalidate_addr 365 #define tlb_invalidate_globals mips3_tlb_invalidate_globals 366 #define tlb_invalidate_all mips3_tlb_invalidate_all 367 #define tlb_record_asids mips3_tlb_record_asids 368 #define tlb_update mips3_tlb_update 369 #define tlb_enter mips3_tlb_enter 370 #define tlb_read_indexed mips3_tlb_read_indexed 371 #define tlb_write_indexed_VPS mips3_tlb_write_indexed_VPS 372 #define lwp_trampoline mips3_lwp_trampoline 373 #define setfunc_trampoline mips3_setfunc_trampoline 374 #define wbflush mips3_wbflush 375 #elif !defined(MIPS1) && !defined(MIPS3) && defined(MIPS32) && !defined(MIPS64) 376 #define tlb_set_asid mips32_tlb_set_asid 377 #define tlb_invalidate_asids mips32_tlb_invalidate_asids 378 #define tlb_invalidate_addr mips32_tlb_invalidate_addr 379 #define tlb_invalidate_globals mips32_tlb_invalidate_globals 380 #define tlb_invalidate_all mips32_tlb_invalidate_all 381 #define tlb_record_asids mips32_tlb_record_asids 382 #define tlb_update mips32_tlb_update 383 #define tlb_enter mips32_tlb_enter 384 #define tlb_read_indexed mips32_tlb_read_indexed 385 #define tlb_write_indexed_VPS mips32_tlb_write_indexed_VPS 386 #define lwp_trampoline mips32_lwp_trampoline 387 #define setfunc_trampoline mips32_setfunc_trampoline 388 #define wbflush mips32_wbflush 389 #elif !defined(MIPS1) && !defined(MIPS3) && !defined(MIPS32) && defined(MIPS64) 390 /* all common with mips3 */ 391 #define tlb_set_asid mips64_tlb_set_asid 392 #define tlb_invalidate_asids mips64_tlb_invalidate_asids 393 #define tlb_invalidate_addr mips64_tlb_invalidate_addr 394 #define tlb_invalidate_globals mips64_tlb_invalidate_globals 395 #define tlb_invalidate_all mips64_tlb_invalidate_all 396 #define tlb_record_asids mips64_tlb_record_asids 397 #define tlb_update mips64_tlb_update 398 #define tlb_enter mips64_tlb_enter 399 #define tlb_read_indexed mips64_tlb_read_indexed 400 #define tlb_write_indexed_VPS mips64_tlb_write_indexed_VPS 401 #define lwp_trampoline mips64_lwp_trampoline 402 #define setfunc_trampoline mips64_setfunc_trampoline 403 #define wbflush mips64_wbflush 404 #elif !defined(MIPS1) && defined(MIPS3) && !defined(MIPS32) && !defined(MIPS64) && defined(MIPS3_5900) 405 #define tlb_set_asid mips5900_tlb_set_asid 406 #define tlb_invalidate_asids mips5900_tlb_invalidate_asids 407 #define tlb_invalidate_addr mips5900_tlb_invalidate_addr 408 #define tlb_invalidate_globals mips5900_tlb_invalidate_globals 409 #define tlb_invalidate_all mips5900_tlb_invalidate_all 410 #define tlb_record_asids mips5900_tlb_record_asids 411 #define tlb_update mips5900_tlb_update 412 #define tlb_enter mips5900_tlb_enter 413 #define tlb_read_indexed mips5900_tlb_read_indexed 414 #define tlb_write_indexed_VPS mips5900_tlb_write_indexed_VPS 415 #define lwp_trampoline mips5900_lwp_trampoline 416 #define setfunc_trampoline mips5900_setfunc_trampoline 417 #define wbflush mips5900_wbflush 418 #else 419 #define tlb_set_asid (*mips_locore_jumpvec.ljv_tlb_set_asid) 420 #define tlb_invalidate_asids (*mips_locore_jumpvec.ljv_tlb_invalidate_asids) 421 #define tlb_invalidate_addr (*mips_locore_jumpvec.ljv_tlb_invalidate_addr) 422 #define tlb_invalidate_globals (*mips_locore_jumpvec.ljv_tlb_invalidate_globals) 423 #define tlb_invalidate_all (*mips_locore_jumpvec.ljv_tlb_invalidate_all) 424 #define tlb_record_asids (*mips_locore_jumpvec.ljv_tlb_record_asids) 425 #define tlb_update (*mips_locore_jumpvec.ljv_tlb_update) 426 #define tlb_enter (*mips_locore_jumpvec.ljv_tlb_enter) 427 #define tlb_read_indexed (*mips_locore_jumpvec.ljv_tlb_read_indexed) 428 #define wbflush (*mips_locore_jumpvec.ljv_wbflush) 429 #define lwp_trampoline mips_locoresw.lsw_lwp_trampoline 430 #define setfunc_trampoline mips_locoresw.lsw_setfunc_trampoline 431 #endif 432 433 #define CPU_IDLE mips_locoresw.lsw_cpu_idle 434 435 /* cpu_switch_resume is called inside locore.S */ 436 437 /* 438 * CPU identification, from PRID register. 439 */ 440 #define MIPS_PRID_REV(x) (((x) >> 0) & 0x00ff) 441 #define MIPS_PRID_IMPL(x) (((x) >> 8) & 0x00ff) 442 443 /* pre-MIPS32/64 */ 444 #define MIPS_PRID_RSVD(x) (((x) >> 16) & 0xffff) 445 #define MIPS_PRID_REV_MIN(x) ((MIPS_PRID_REV(x) >> 0) & 0x0f) 446 #define MIPS_PRID_REV_MAJ(x) ((MIPS_PRID_REV(x) >> 4) & 0x0f) 447 448 /* MIPS32/64 */ 449 #define MIPS_PRID_CID(x) (((x) >> 16) & 0x00ff) /* Company ID */ 450 #define MIPS_PRID_CID_PREHISTORIC 0x00 /* Not MIPS32/64 */ 451 #define MIPS_PRID_CID_MTI 0x01 /* MIPS Technologies, Inc. */ 452 #define MIPS_PRID_CID_BROADCOM 0x02 /* Broadcom */ 453 #define MIPS_PRID_CID_ALCHEMY 0x03 /* Alchemy Semiconductor */ 454 #define MIPS_PRID_CID_SIBYTE 0x04 /* SiByte */ 455 #define MIPS_PRID_CID_SANDCRAFT 0x05 /* SandCraft */ 456 #define MIPS_PRID_CID_PHILIPS 0x06 /* Philips */ 457 #define MIPS_PRID_CID_TOSHIBA 0x07 /* Toshiba */ 458 #define MIPS_PRID_CID_LSI 0x08 /* LSI */ 459 /* 0x09 unannounced */ 460 /* 0x0a unannounced */ 461 #define MIPS_PRID_CID_LEXRA 0x0b /* Lexra */ 462 #define MIPS_PRID_CID_RMI 0x0c /* RMI / NetLogic */ 463 #define MIPS_PRID_COPTS(x) (((x) >> 24) & 0x00ff) /* Company Options */ 464 465 #ifdef _KERNEL 466 /* 467 * Global variables used to communicate CPU type, and parameters 468 * such as cache size, from locore to higher-level code (e.g., pmap). 469 */ 470 void mips_pagecopy(void *dst, void *src); 471 void mips_pagezero(void *dst); 472 473 #ifdef __HAVE_MIPS_MACHDEP_CACHE_CONFIG 474 void mips_machdep_cache_config(void); 475 #endif 476 477 /* 478 * trapframe argument passed to trap() 479 */ 480 481 #if 0 482 #define TF_AST 0 /* really zero */ 483 #define TF_V0 _R_V0 484 #define TF_V1 _R_V1 485 #define TF_A0 _R_A0 486 #define TF_A1 _R_A1 487 #define TF_A2 _R_A2 488 #define TF_A3 _R_A3 489 #define TF_T0 _R_T0 490 #define TF_T1 _R_T1 491 #define TF_T2 _R_T2 492 #define TF_T3 _R_T3 493 494 #if defined(__mips_n32) || defined(__mips_n64) 495 #define TF_A4 _R_A4 496 #define TF_A5 _R_A5 497 #define TF_A6 _R_A6 498 #define TF_A7 _R_A7 499 #else 500 #define TF_T4 _R_T4 501 #define TF_T5 _R_T5 502 #define TF_T6 _R_T6 503 #define TF_T7 _R_T7 504 #endif /* __mips_n32 || __mips_n64 */ 505 506 #define TF_TA0 _R_TA0 507 #define TF_TA1 _R_TA1 508 #define TF_TA2 _R_TA2 509 #define TF_TA3 _R_TA3 510 511 #define TF_T8 _R_T8 512 #define TF_T9 _R_T9 513 514 #define TF_RA _R_RA 515 #define TF_SR _R_SR 516 #define TF_MULLO _R_MULLO 517 #define TF_MULHI _R_MULLO 518 #define TF_EPC _R_PC /* may be changed by trap() call */ 519 520 #define TF_NREGS (sizeof(struct reg) / sizeof(mips_reg_t)) 521 #endif 522 523 struct trapframe { 524 struct reg tf_registers; 525 #define tf_regs tf_registers.r_regs 526 uint32_t tf_ppl; /* previous priority level */ 527 mips_reg_t tf_pad; /* for 8 byte aligned */ 528 }; 529 530 CTASSERT(sizeof(struct trapframe) % (4*sizeof(mips_reg_t)) == 0); 531 532 /* 533 * Stack frame for kernel traps. four args passed in registers. 534 * A trapframe is pointed to by the 5th arg, and a dummy sixth argument 535 * is used to avoid alignment problems 536 */ 537 538 struct kernframe { 539 #if defined(__mips_o32) || defined(__mips_o64) 540 register_t cf_args[4 + 1]; 541 #if defined(__mips_o32) 542 register_t cf_pad; /* (for 8 byte alignment) */ 543 #endif 544 #endif 545 #if defined(__mips_n32) || defined(__mips_n64) 546 register_t cf_pad[2]; /* for 16 byte alignment */ 547 #endif 548 register_t cf_sp; 549 register_t cf_ra; 550 struct trapframe cf_frame; 551 }; 552 553 CTASSERT(sizeof(struct kernframe) % (2*sizeof(mips_reg_t)) == 0); 554 555 #endif /* _KERNEL */ 556 #endif /* _MIPS_LOCORE_H */ 557
Indexes created Mon Oct 20 08:09:54 GMT 2025