locore.h revision 1.78.36.1.2.17
1 /* $NetBSD: locore.h,v 1.78.36.1.2.17 2010/02/28 03:21:06 matt Exp $ */ 2 3 /* 4 * This file should not be included by MI code!!! 5 */ 6 7 /* 8 * Copyright 1996 The Board of Trustees of The Leland Stanford 9 * Junior University. All Rights Reserved. 10 * 11 * Permission to use, copy, modify, and distribute this 12 * software and its documentation for any purpose and without 13 * fee is hereby granted, provided that the above copyright 14 * notice appear in all copies. Stanford University 15 * makes no representations about the suitability of this 16 * software for any purpose. It is provided "as is" without 17 * express or implied warranty. 18 */ 19 20 /* 21 * Jump table for MIPS CPU locore functions that are implemented 22 * differently on different generations, or instruction-level 23 * archtecture (ISA) level, the Mips family. 24 * 25 * We currently provide support for MIPS I and MIPS III. 26 */ 27 28 #ifndef _MIPS_LOCORE_H 29 #define _MIPS_LOCORE_H 30 31 #ifndef _LKM 32 #include "opt_cputype.h" 33 #endif 34 35 #include <mips/cpuregs.h> 36 #include <mips/reg.h> 37 38 struct tlbmask; 39 40 uint32_t mips_cp0_cause_read(void); 41 void mips_cp0_cause_write(uint32_t); 42 uint32_t mips_cp0_status_read(void); 43 void mips_cp0_status_write(uint32_t); 44 45 void softint_process(uint32_t); 46 void softint_fast_dispatch(struct lwp *, int); 47 48 typedef bool (*mips_fixup_callback_t)(int32_t, uint32_t [2]); 49 50 void fixup_splcalls(void); /* splstubs.c */ 51 bool mips_fixup_exceptions(mips_fixup_callback_t); 52 bool mips_fixup_zero_relative(int32_t, uint32_t [2]); 53 void mips_fixup_stubs(uint32_t *, uint32_t *, const uint32_t *, 54 const uint32_t *, size_t); 55 void fixup_mips_cpu_switch_resume(void); 56 57 void mips_cpu_switch_resume(struct lwp *); 58 59 #ifdef MIPS1 60 void mips1_tlb_set_asid(uint32_t); 61 void mips1_tlb_invalidate_all(void); 62 void mips1_tlb_invalidate_globals(void); 63 void mips1_tlb_invalidate_asids(uint32_t, uint32_t); 64 void mips1_tlb_invalidate_addr(vaddr_t); 65 u_int mips1_tlb_record_asids(u_long *, uint32_t); 66 int mips1_tlb_update(vaddr_t, uint32_t); 67 void mips1_tlb_enter(size_t, vaddr_t, uint32_t); 68 void mips1_tlb_read_indexed(size_t, struct tlbmask *); 69 void mips1_wbflush(void); 70 void mips1_lwp_trampoline(void); 71 void mips1_setfunc_trampoline(void); 72 void mips1_cpu_switch_resume(struct lwp *); 73 74 uint32_t tx3900_cp0_config_read(void); 75 #endif 76 77 #if defined(MIPS3) || defined(MIPS4) 78 void mips3_tlb_set_asid(uint32_t); 79 void mips3_tlb_invalidate_all(void); 80 void mips3_tlb_invalidate_globals(void); 81 void mips3_tlb_invalidate_asids(uint32_t, uint32_t); 82 void mips3_tlb_invalidate_addr(vaddr_t); 83 u_int mips3_tlb_record_asids(u_long *, uint32_t); 84 int mips3_tlb_update(vaddr_t, uint32_t); 85 void mips3_tlb_enter(size_t, vaddr_t, uint32_t); 86 void mips3_tlb_read_indexed(size_t, struct tlbmask *); 87 void mips3_tlb_write_indexed_VPS(size_t, struct tlbmask *); 88 void mips3_wbflush(void); 89 void mips3_lwp_trampoline(void); 90 void mips3_setfunc_trampoline(void); 91 void mips3_cpu_switch_resume(struct lwp *); 92 void mips3_pagezero(void *dst); 93 94 #ifdef MIPS3_5900 95 void mips5900_tlb_set_asid(uint32_t); 96 void mips5900_tlb_invalidate_all(void); 97 void mips5900_tlb_invalidate_globals(void); 98 void mips5900_tlb_invalidate_asids(uint32_t, uint32_t); 99 void mips5900_tlb_invalidate_addr(vaddr_t); 100 u_int mips5900_tlb_record_asids(u_long *, uint32_t); 101 int mips5900_tlb_update(vaddr_t, uint32_t); 102 void mips5900_tlb_enter(size_t, vaddr_t, uint32_t); 103 void mips5900_tlb_read_indexed(size_t, struct tlbmask *); 104 void mips5900_tlb_write_indexed_VPS(size_t, struct tlbmask *); 105 void mips5900_wbflush(void); 106 void mips5900_lwp_trampoline(void); 107 void mips5900_setfunc_trampoline(void); 108 void mips5900_cpu_switch_resume(struct lwp *); 109 void mips5900_pagezero(void *dst); 110 #endif 111 #endif 112 113 #ifdef MIPS32 114 void mips32_tlb_set_asid(uint32_t); 115 void mips32_tlb_invalidate_all(void); 116 void mips32_tlb_invalidate_globals(void); 117 void mips32_tlb_invalidate_asids(uint32_t, uint32_t); 118 void mips32_tlb_invalidate_addr(vaddr_t); 119 u_int mips32_tlb_record_asids(u_long *, uint32_t); 120 int mips32_tlb_update(vaddr_t, uint32_t); 121 void mips32_tlb_enter(size_t, vaddr_t, uint32_t); 122 void mips32_tlb_read_indexed(size_t, struct tlbmask *); 123 void mips32_tlb_write_indexed_VPS(size_t, struct tlbmask *); 124 void mips32_wbflush(void); 125 void mips32_lwp_trampoline(void); 126 void mips32_setfunc_trampoline(void); 127 void mips32_cpu_switch_resume(struct lwp *); 128 #endif 129 130 #ifdef MIPS64 131 void mips64_tlb_set_asid(uint32_t); 132 void mips64_tlb_invalidate_all(void); 133 void mips64_tlb_invalidate_globals(void); 134 void mips64_tlb_invalidate_asids(uint32_t, uint32_t); 135 void mips64_tlb_invalidate_addr(vaddr_t); 136 u_int mips64_tlb_record_asids(u_long *, uint32_t); 137 int mips64_tlb_update(vaddr_t, uint32_t); 138 void mips64_tlb_enter(size_t, vaddr_t, uint32_t); 139 void mips64_tlb_read_indexed(size_t, struct tlbmask *); 140 void mips64_tlb_write_indexed_VPS(size_t, struct tlbmask *); 141 void mips64_wbflush(void); 142 void mips64_lwp_trampoline(void); 143 void mips64_setfunc_trampoline(void); 144 void mips64_cpu_switch_resume(struct lwp *); 145 void mips64_pagezero(void *dst); 146 #endif 147 148 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64) 149 uint32_t mips3_cp0_compare_read(void); 150 void mips3_cp0_compare_write(uint32_t); 151 152 uint32_t mips3_cp0_config_read(void); 153 void mips3_cp0_config_write(uint32_t); 154 #if defined(MIPS32) || defined(MIPS64) 155 uint32_t mipsNN_cp0_config1_read(void); 156 void mipsNN_cp0_config1_write(uint32_t); 157 uint32_t mipsNN_cp0_config2_read(void); 158 uint32_t mipsNN_cp0_config3_read(void); 159 #endif 160 161 uint32_t mips3_cp0_count_read(void); 162 void mips3_cp0_count_write(uint32_t); 163 164 uint32_t mips3_cp0_wired_read(void); 165 void mips3_cp0_wired_write(uint32_t); 166 void mips3_cp0_pg_mask_write(uint32_t); 167 168 #if defined(__GNUC__) && !defined(__mips_o32) 169 static inline uint64_t 170 mips3_ld(const volatile uint64_t *va) 171 { 172 uint64_t rv; 173 #if defined(__mips_o32) 174 uint32_t sr; 175 176 sr = mips_cp0_status_read(); 177 mips_cp0_status_write(sr & ~MIPS_SR_INT_IE); 178 179 __asm volatile( 180 ".set push \n\t" 181 ".set mips3 \n\t" 182 ".set noreorder \n\t" 183 ".set noat \n\t" 184 "ld %M0,0(%1) \n\t" 185 "dsll32 %L0,%M0,0 \n\t" 186 "dsra32 %M0,%M0,0 \n\t" /* high word */ 187 "dsra32 %L0,%L0,0 \n\t" /* low word */ 188 "ld %0,0(%1) \n\t" 189 ".set pop" 190 : "=d"(rv) 191 : "r"(va)); 192 193 mips_cp0_status_write(sr); 194 #elif defined(_LP64) 195 rv = *va; 196 #else 197 __asm volatile("ld %0,0(%1)" : "=d"(rv) : "r"(va)); 198 #endif 199 200 return rv; 201 } 202 static inline void 203 mips3_sd(volatile uint64_t *va, uint64_t v) 204 { 205 #if defined(__mips_o32) 206 uint32_t sr; 207 208 sr = mips_cp0_status_read(); 209 mips_cp0_status_write(sr & ~MIPS_SR_INT_IE); 210 211 __asm volatile( 212 ".set push \n\t" 213 ".set mips3 \n\t" 214 ".set noreorder \n\t" 215 ".set noat \n\t" 216 "dsll32 %M0,%M0,0 \n\t" 217 "dsll32 %L0,%L0,0 \n\t" 218 "dsrl32 %L0,%L0,0 \n\t" 219 "or %0,%L0,%M0 \n\t" 220 "sd %0,0(%1) \n\t" 221 ".set pop" 222 : "=d"(v) : "0"(v), "r"(va)); 223 224 mips_cp0_status_write(sr); 225 #elif defined(_LP64) 226 *va = v; 227 #else 228 __asm volatile("sd %0,0(%1)" :: "r"(v), "r"(va)); 229 #endif 230 } 231 #else 232 uint64_t mips3_ld(volatile uint64_t *va); 233 void mips3_sd(volatile uint64_t *, uint64_t); 234 #endif /* __GNUC__ */ 235 #endif /* MIPS3 || MIPS4 || MIPS32 || MIPS64 */ 236 237 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS64) 238 static __inline uint32_t mips3_lw_a64(uint64_t addr) 239 __attribute__((__unused__)); 240 static __inline void mips3_sw_a64(uint64_t addr, uint32_t val) 241 __attribute__ ((__unused__)); 242 243 static __inline uint32_t 244 mips3_lw_a64(uint64_t addr) 245 { 246 uint32_t rv; 247 #if defined(__mips_o32) 248 uint32_t sr; 249 250 sr = mips_cp0_status_read(); 251 mips_cp0_status_write((sr & ~MIPS_SR_INT_IE) | MIPS3_SR_KX); 252 253 __asm volatile ( 254 ".set push \n\t" 255 ".set mips3 \n\t" 256 ".set noreorder \n\t" 257 ".set noat \n\t" 258 "dsll32 %M1,%M1,0 \n\t" 259 "dsll32 %L1,%L1,0 \n\t" 260 "dsrl32 %L1,%L1,0 \n\t" 261 "or %1,%M1,%L1 \n\t" 262 "lw %0, 0(%1) \n\t" 263 ".set pop" 264 : "=r"(rv), "=d"(addr) 265 : "1"(addr) 266 ); 267 268 mips_cp0_status_write(sr); 269 #elif defined(_LP64) 270 rv = *(const uint32_t *)addr; 271 #else 272 __asm volatile("lw %0, 0(%1)" : "=r"(rv) : "d"(addr)); 273 #endif 274 return (rv); 275 } 276 277 static __inline void 278 mips3_sw_a64(uint64_t addr, uint32_t val) 279 { 280 #if defined(__mips_o32) 281 uint32_t sr; 282 283 sr = mips_cp0_status_read(); 284 mips_cp0_status_write((sr & ~MIPS_SR_INT_IE) | MIPS3_SR_KX); 285 286 __asm volatile ( 287 ".set push \n\t" 288 ".set mips3 \n\t" 289 ".set noreorder \n\t" 290 ".set noat \n\t" 291 "dsll32 %M0,%M0,0 \n\t" 292 "dsll32 %L0,%L0,0 \n\t" 293 "dsrl32 %L0,%L0,0 \n\t" 294 "or %0,%M0,%L0 \n\t" 295 "sw %1, 0(%0) \n\t" 296 ".set pop" 297 : "=d"(addr): "r"(val), "0"(addr) 298 ); 299 300 mips_cp0_status_write(sr); 301 #elif defined(_LP64) 302 *(uint32_t *)addr = val; 303 #else 304 __asm volatile("sw %1, 0(%0)" :: "d"(addr), "r"(val)); 305 #endif 306 } 307 #endif /* MIPS3 || MIPS4 || MIPS64 */ 308 309 /* 310 * A vector with an entry for each mips-ISA-level dependent 311 * locore function, and macros which jump through it. 312 */ 313 typedef struct { 314 void (*ljv_tlb_set_asid)(uint32_t pid); 315 void (*ljv_tlb_invalidate_asids)(uint32_t, uint32_t); 316 void (*ljv_tlb_invalidate_addr)(vaddr_t); 317 void (*ljv_tlb_invalidate_globals)(void); 318 void (*ljv_tlb_invalidate_all)(void); 319 u_int (*ljv_tlb_record_asids)(u_long *, uint32_t); 320 int (*ljv_tlb_update)(vaddr_t, uint32_t); 321 void (*ljv_tlb_enter)(size_t, vaddr_t, uint32_t); 322 void (*ljv_tlb_read_indexed)(size_t, struct tlbmask *); 323 void (*ljv_wbflush)(void); 324 } mips_locore_jumpvec_t; 325 326 void mips_set_wbflush(void (*)(void)); 327 void mips_wait_idle(void); 328 329 void stacktrace(void); 330 void logstacktrace(void); 331 332 struct locoresw { 333 void (*lsw_cpu_switch_resume)(struct lwp *); 334 uintptr_t lsw_lwp_trampoline; 335 void (*lsw_cpu_idle)(void); 336 uintptr_t lsw_setfunc_trampoline; 337 void (*lsw_boot_secondary_processors)(void); 338 int (*lsw_send_ipi)(struct cpu_info *, int); 339 void (*lsw_cpu_offline_md)(void); 340 }; 341 342 struct mips_vmfreelist { 343 paddr_t fl_start; 344 paddr_t fl_end; 345 int fl_freelist; 346 }; 347 348 /* 349 * The "active" locore-fuction vector, and 350 */ 351 extern mips_locore_jumpvec_t mips_locore_jumpvec; 352 extern struct locoresw mips_locoresw; 353 354 #if defined(MIPS1) && !defined(MIPS3) && !defined(MIPS32) && !defined(MIPS64) 355 #define tlb_set_asid mips1_tlb_set_asid 356 #define tlb_invalidate_asids mips1_tlb_invalidate_asids 357 #define tlb_invalidate_addr mips1_tlb_invalidate_addr 358 #define tlb_invalidate_globals mips1_tlb_invalidate_globals 359 #define tlb_invalidate_all mips1_tlb_invalidate_all 360 #define tlb_record_asids mips1_tlb_record_asids 361 #define tlb_update mips1_tlb_update 362 #define tlb_enter mips1_tlb_enter 363 #define tlb_read_indexed mips1_tlb_read_indexed 364 #define wbflush mips1_wbflush 365 #define lwp_trampoline mips1_lwp_trampoline 366 #define setfunc_trampoline mips1_setfunc_trampoline 367 #elif !defined(MIPS1) && defined(MIPS3) && !defined(MIPS32) && !defined(MIPS64) && !defined(MIPS3_5900) 368 #define tlb_set_asid mips3_tlb_set_asid 369 #define tlb_invalidate_asids mips3_tlb_invalidate_asids 370 #define tlb_invalidate_addr mips3_tlb_invalidate_addr 371 #define tlb_invalidate_globals mips3_tlb_invalidate_globals 372 #define tlb_invalidate_all mips3_tlb_invalidate_all 373 #define tlb_record_asids mips3_tlb_record_asids 374 #define tlb_update mips3_tlb_update 375 #define tlb_enter mips3_tlb_enter 376 #define tlb_read_indexed mips3_tlb_read_indexed 377 #define tlb_write_indexed_VPS mips3_tlb_write_indexed_VPS 378 #define lwp_trampoline mips3_lwp_trampoline 379 #define setfunc_trampoline mips3_setfunc_trampoline 380 #define wbflush mips3_wbflush 381 #elif !defined(MIPS1) && !defined(MIPS3) && defined(MIPS32) && !defined(MIPS64) 382 #define tlb_set_asid mips32_tlb_set_asid 383 #define tlb_invalidate_asids mips32_tlb_invalidate_asids 384 #define tlb_invalidate_addr mips32_tlb_invalidate_addr 385 #define tlb_invalidate_globals mips32_tlb_invalidate_globals 386 #define tlb_invalidate_all mips32_tlb_invalidate_all 387 #define tlb_record_asids mips32_tlb_record_asids 388 #define tlb_update mips32_tlb_update 389 #define tlb_enter mips32_tlb_enter 390 #define tlb_read_indexed mips32_tlb_read_indexed 391 #define tlb_write_indexed_VPS mips32_tlb_write_indexed_VPS 392 #define lwp_trampoline mips32_lwp_trampoline 393 #define setfunc_trampoline mips32_setfunc_trampoline 394 #define wbflush mips32_wbflush 395 #elif !defined(MIPS1) && !defined(MIPS3) && !defined(MIPS32) && defined(MIPS64) 396 /* all common with mips3 */ 397 #define tlb_set_asid mips64_tlb_set_asid 398 #define tlb_invalidate_asids mips64_tlb_invalidate_asids 399 #define tlb_invalidate_addr mips64_tlb_invalidate_addr 400 #define tlb_invalidate_globals mips64_tlb_invalidate_globals 401 #define tlb_invalidate_all mips64_tlb_invalidate_all 402 #define tlb_record_asids mips64_tlb_record_asids 403 #define tlb_update mips64_tlb_update 404 #define tlb_enter mips64_tlb_enter 405 #define tlb_read_indexed mips64_tlb_read_indexed 406 #define tlb_write_indexed_VPS mips64_tlb_write_indexed_VPS 407 #define lwp_trampoline mips64_lwp_trampoline 408 #define setfunc_trampoline mips64_setfunc_trampoline 409 #define wbflush mips64_wbflush 410 #elif !defined(MIPS1) && defined(MIPS3) && !defined(MIPS32) && !defined(MIPS64) && defined(MIPS3_5900) 411 #define tlb_set_asid mips5900_tlb_set_asid 412 #define tlb_invalidate_asids mips5900_tlb_invalidate_asids 413 #define tlb_invalidate_addr mips5900_tlb_invalidate_addr 414 #define tlb_invalidate_globals mips5900_tlb_invalidate_globals 415 #define tlb_invalidate_all mips5900_tlb_invalidate_all 416 #define tlb_record_asids mips5900_tlb_record_asids 417 #define tlb_update mips5900_tlb_update 418 #define tlb_enter mips5900_tlb_enter 419 #define tlb_read_indexed mips5900_tlb_read_indexed 420 #define tlb_write_indexed_VPS mips5900_tlb_write_indexed_VPS 421 #define lwp_trampoline mips5900_lwp_trampoline 422 #define setfunc_trampoline mips5900_setfunc_trampoline 423 #define wbflush mips5900_wbflush 424 #else 425 #define tlb_set_asid (*mips_locore_jumpvec.ljv_tlb_set_asid) 426 #define tlb_invalidate_asids (*mips_locore_jumpvec.ljv_tlb_invalidate_asids) 427 #define tlb_invalidate_addr (*mips_locore_jumpvec.ljv_tlb_invalidate_addr) 428 #define tlb_invalidate_globals (*mips_locore_jumpvec.ljv_tlb_invalidate_globals) 429 #define tlb_invalidate_all (*mips_locore_jumpvec.ljv_tlb_invalidate_all) 430 #define tlb_record_asids (*mips_locore_jumpvec.ljv_tlb_record_asids) 431 #define tlb_update (*mips_locore_jumpvec.ljv_tlb_update) 432 #define tlb_enter (*mips_locore_jumpvec.ljv_tlb_enter) 433 #define tlb_read_indexed (*mips_locore_jumpvec.ljv_tlb_read_indexed) 434 #define wbflush (*mips_locore_jumpvec.ljv_wbflush) 435 #define lwp_trampoline mips_locoresw.lsw_lwp_trampoline 436 #define setfunc_trampoline mips_locoresw.lsw_setfunc_trampoline 437 #endif 438 439 #define CPU_IDLE mips_locoresw.lsw_cpu_idle 440 441 /* cpu_switch_resume is called inside locore.S */ 442 443 /* 444 * CPU identification, from PRID register. 445 */ 446 #define MIPS_PRID_REV(x) (((x) >> 0) & 0x00ff) 447 #define MIPS_PRID_IMPL(x) (((x) >> 8) & 0x00ff) 448 449 /* pre-MIPS32/64 */ 450 #define MIPS_PRID_RSVD(x) (((x) >> 16) & 0xffff) 451 #define MIPS_PRID_REV_MIN(x) ((MIPS_PRID_REV(x) >> 0) & 0x0f) 452 #define MIPS_PRID_REV_MAJ(x) ((MIPS_PRID_REV(x) >> 4) & 0x0f) 453 454 /* MIPS32/64 */ 455 #define MIPS_PRID_CID(x) (((x) >> 16) & 0x00ff) /* Company ID */ 456 #define MIPS_PRID_CID_PREHISTORIC 0x00 /* Not MIPS32/64 */ 457 #define MIPS_PRID_CID_MTI 0x01 /* MIPS Technologies, Inc. */ 458 #define MIPS_PRID_CID_BROADCOM 0x02 /* Broadcom */ 459 #define MIPS_PRID_CID_ALCHEMY 0x03 /* Alchemy Semiconductor */ 460 #define MIPS_PRID_CID_SIBYTE 0x04 /* SiByte */ 461 #define MIPS_PRID_CID_SANDCRAFT 0x05 /* SandCraft */ 462 #define MIPS_PRID_CID_PHILIPS 0x06 /* Philips */ 463 #define MIPS_PRID_CID_TOSHIBA 0x07 /* Toshiba */ 464 #define MIPS_PRID_CID_LSI 0x08 /* LSI */ 465 /* 0x09 unannounced */ 466 /* 0x0a unannounced */ 467 #define MIPS_PRID_CID_LEXRA 0x0b /* Lexra */ 468 #define MIPS_PRID_CID_RMI 0x0c /* RMI / NetLogic */ 469 #define MIPS_PRID_COPTS(x) (((x) >> 24) & 0x00ff) /* Company Options */ 470 471 #ifdef _KERNEL 472 /* 473 * Global variables used to communicate CPU type, and parameters 474 * such as cache size, from locore to higher-level code (e.g., pmap). 475 */ 476 void mips_pagecopy(void *dst, void *src); 477 void mips_pagezero(void *dst); 478 479 #ifdef __HAVE_MIPS_MACHDEP_CACHE_CONFIG 480 void mips_machdep_cache_config(void); 481 #endif 482 483 /* 484 * trapframe argument passed to trap() 485 */ 486 487 #if 0 488 #define TF_AST 0 /* really zero */ 489 #define TF_V0 _R_V0 490 #define TF_V1 _R_V1 491 #define TF_A0 _R_A0 492 #define TF_A1 _R_A1 493 #define TF_A2 _R_A2 494 #define TF_A3 _R_A3 495 #define TF_T0 _R_T0 496 #define TF_T1 _R_T1 497 #define TF_T2 _R_T2 498 #define TF_T3 _R_T3 499 500 #if defined(__mips_n32) || defined(__mips_n64) 501 #define TF_A4 _R_A4 502 #define TF_A5 _R_A5 503 #define TF_A6 _R_A6 504 #define TF_A7 _R_A7 505 #else 506 #define TF_T4 _R_T4 507 #define TF_T5 _R_T5 508 #define TF_T6 _R_T6 509 #define TF_T7 _R_T7 510 #endif /* __mips_n32 || __mips_n64 */ 511 512 #define TF_TA0 _R_TA0 513 #define TF_TA1 _R_TA1 514 #define TF_TA2 _R_TA2 515 #define TF_TA3 _R_TA3 516 517 #define TF_T8 _R_T8 518 #define TF_T9 _R_T9 519 520 #define TF_RA _R_RA 521 #define TF_SR _R_SR 522 #define TF_MULLO _R_MULLO 523 #define TF_MULHI _R_MULLO 524 #define TF_EPC _R_PC /* may be changed by trap() call */ 525 526 #define TF_NREGS (sizeof(struct reg) / sizeof(mips_reg_t)) 527 #endif 528 529 struct trapframe { 530 struct reg tf_registers; 531 #define tf_regs tf_registers.r_regs 532 uint32_t tf_ppl; /* previous priority level */ 533 mips_reg_t tf_pad; /* for 8 byte aligned */ 534 }; 535 536 CTASSERT(sizeof(struct trapframe) % (4*sizeof(mips_reg_t)) == 0); 537 538 /* 539 * Stack frame for kernel traps. four args passed in registers. 540 * A trapframe is pointed to by the 5th arg, and a dummy sixth argument 541 * is used to avoid alignment problems 542 */ 543 544 struct kernframe { 545 #if defined(__mips_o32) || defined(__mips_o64) 546 register_t cf_args[4 + 1]; 547 #if defined(__mips_o32) 548 register_t cf_pad; /* (for 8 byte alignment) */ 549 #endif 550 #endif 551 #if defined(__mips_n32) || defined(__mips_n64) 552 register_t cf_pad[2]; /* for 16 byte alignment */ 553 #endif 554 register_t cf_sp; 555 register_t cf_ra; 556 struct trapframe cf_frame; 557 }; 558 559 CTASSERT(sizeof(struct kernframe) % (2*sizeof(mips_reg_t)) == 0); 560 561 #endif /* _KERNEL */ 562 #endif /* _MIPS_LOCORE_H */ 563
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