locore.h revision 1.78.36.1.2.32
1 /* locore.h,v 1.78.36.1.2.29 2011/04/29 08:26:21 matt Exp */ 2 3 /* 4 * This file should not be included by MI code!!! 5 */ 6 7 /* 8 * Copyright 1996 The Board of Trustees of The Leland Stanford 9 * Junior University. All Rights Reserved. 10 * 11 * Permission to use, copy, modify, and distribute this 12 * software and its documentation for any purpose and without 13 * fee is hereby granted, provided that the above copyright 14 * notice appear in all copies. Stanford University 15 * makes no representations about the suitability of this 16 * software for any purpose. It is provided "as is" without 17 * express or implied warranty. 18 */ 19 20 /* 21 * Jump table for MIPS CPU locore functions that are implemented 22 * differently on different generations, or instruction-level 23 * architecture (ISA) level, the Mips family. 24 * 25 * We currently provide support for MIPS I and MIPS III. 26 */ 27 28 #ifndef _MIPS_LOCORE_H 29 #define _MIPS_LOCORE_H 30 31 #ifndef _LKM 32 #include "opt_cputype.h" 33 #endif 34 35 #include <mips/mutex.h> 36 #include <mips/cpuregs.h> 37 #include <mips/reg.h> 38 39 struct tlbmask; 40 struct trapframe; 41 42 void trap(uint32_t, uint32_t, vaddr_t, vaddr_t, struct trapframe *); 43 void ast(void); 44 45 void mips_fpu_trap(vaddr_t, struct trapframe *); 46 void mips_fpu_intr(vaddr_t, struct trapframe *); 47 48 vaddr_t mips_emul_branch(struct trapframe *, vaddr_t, uint32_t, bool); 49 void mips_emul_inst(uint32_t, uint32_t, vaddr_t, struct trapframe *); 50 51 void mips_emul_fp(uint32_t, struct trapframe *, uint32_t); 52 void mips_emul_branchdelayslot(uint32_t, struct trapframe *, uint32_t); 53 54 void mips_emul_lwc0(uint32_t, struct trapframe *, uint32_t); 55 void mips_emul_swc0(uint32_t, struct trapframe *, uint32_t); 56 void mips_emul_special(uint32_t, struct trapframe *, uint32_t); 57 void mips_emul_special3(uint32_t, struct trapframe *, uint32_t); 58 59 void mips_emul_lwc1(uint32_t, struct trapframe *, uint32_t); 60 void mips_emul_swc1(uint32_t, struct trapframe *, uint32_t); 61 void mips_emul_ldc1(uint32_t, struct trapframe *, uint32_t); 62 void mips_emul_sdc1(uint32_t, struct trapframe *, uint32_t); 63 64 void mips_emul_lb(uint32_t, struct trapframe *, uint32_t); 65 void mips_emul_lbu(uint32_t, struct trapframe *, uint32_t); 66 void mips_emul_lh(uint32_t, struct trapframe *, uint32_t); 67 void mips_emul_lhu(uint32_t, struct trapframe *, uint32_t); 68 void mips_emul_lw(uint32_t, struct trapframe *, uint32_t); 69 void mips_emul_lwl(uint32_t, struct trapframe *, uint32_t); 70 void mips_emul_lwr(uint32_t, struct trapframe *, uint32_t); 71 #if defined(__mips_n32) || defined(__mips_n64) || defined(__mips_o64) 72 void mips_emul_lwu(uint32_t, struct trapframe *, uint32_t); 73 void mips_emul_ld(uint32_t, struct trapframe *, uint32_t); 74 void mips_emul_ldl(uint32_t, struct trapframe *, uint32_t); 75 void mips_emul_ldr(uint32_t, struct trapframe *, uint32_t); 76 #endif 77 void mips_emul_sb(uint32_t, struct trapframe *, uint32_t); 78 void mips_emul_sh(uint32_t, struct trapframe *, uint32_t); 79 void mips_emul_sw(uint32_t, struct trapframe *, uint32_t); 80 void mips_emul_swl(uint32_t, struct trapframe *, uint32_t); 81 void mips_emul_swr(uint32_t, struct trapframe *, uint32_t); 82 #if defined(__mips_n32) || defined(__mips_n64) || defined(__mips_o64) 83 void mips_emul_sd(uint32_t, struct trapframe *, uint32_t); 84 void mips_emul_sdl(uint32_t, struct trapframe *, uint32_t); 85 void mips_emul_sdr(uint32_t, struct trapframe *, uint32_t); 86 #endif 87 88 uint32_t mips_cp0_cause_read(void); 89 void mips_cp0_cause_write(uint32_t); 90 uint32_t mips_cp0_status_read(void); 91 void mips_cp0_status_write(uint32_t); 92 93 void softint_process(uint32_t); 94 void softint_fast_dispatch(struct lwp *, int); 95 96 /* 97 * Convert an address to an offset used in a MIPS jump instruction. The offset 98 * contains the low 28 bits (allowing a jump to anywhere within the same 256MB 99 * segment of address space) of the address but since mips instructions are 100 * always on a 4 byte boundary the low 2 bits are always zero so the 28 bits 101 * get shifted right by 2 bits leaving us with a 26 bit result. To make the 102 * offset, we shift left to clear the upper four bits and then right by 6. 103 */ 104 #define fixup_addr2offset(x) ((((uint32_t)(uintptr_t)(x)) << 4) >> 6) 105 typedef bool (*mips_fixup_callback_t)(int32_t, uint32_t [2]); 106 struct mips_jump_fixup_info { 107 uint32_t jfi_stub; 108 uint32_t jfi_real; 109 }; 110 111 void fixup_splcalls(void); /* splstubs.c */ 112 bool mips_fixup_exceptions(mips_fixup_callback_t); 113 bool mips_fixup_zero_relative(int32_t, uint32_t [2]); 114 intptr_t 115 mips_fixup_addr(const uint32_t *); 116 void mips_fixup_stubs(uint32_t *, uint32_t *); 117 118 /* 119 * Define these stubs... 120 */ 121 void mips_cpu_switch_resume(struct lwp *); 122 void tlb_set_asid(uint32_t); 123 void tlb_invalidate_all(void); 124 void tlb_invalidate_globals(void); 125 void tlb_invalidate_asids(uint32_t, uint32_t); 126 void tlb_invalidate_addr(vaddr_t); 127 u_int tlb_record_asids(u_long *, uint32_t); 128 int tlb_update(vaddr_t, uint32_t); 129 void tlb_enter(size_t, vaddr_t, uint32_t); 130 void tlb_read_indexed(size_t, struct tlbmask *); 131 void tlb_write_indexed(size_t, const struct tlbmask *); 132 void wbflush(void); 133 134 #ifdef MIPS1 135 void mips1_tlb_invalidate_all(void); 136 137 uint32_t tx3900_cp0_config_read(void); 138 #endif 139 140 #if (MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2 + MIPS64_RMIXL + MIPS64R2_RMIXL) > 0 141 uint32_t mips3_cp0_compare_read(void); 142 void mips3_cp0_compare_write(uint32_t); 143 144 uint32_t mips3_cp0_config_read(void); 145 void mips3_cp0_config_write(uint32_t); 146 147 #if (MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2 + MIPS64_RMIXL + MIPS64R2_RMIXL) > 0 148 uint32_t mipsNN_cp0_config1_read(void); 149 void mipsNN_cp0_config1_write(uint32_t); 150 uint32_t mipsNN_cp0_config2_read(void); 151 void mipsNN_cp0_config2_write(uint32_t); 152 uint32_t mipsNN_cp0_config3_read(void); 153 void mipsNN_cp0_config3_write(uint32_t); 154 uint32_t mipsNN_cp0_config4_read(void); 155 void mipsNN_cp0_config4_write(uint32_t); 156 uint32_t mipsNN_cp0_config5_read(void); 157 void mipsNN_cp0_config5_write(uint32_t); 158 uint32_t mipsNN_cp0_config6_read(void); 159 void mipsNN_cp0_config6_write(uint32_t); 160 uint32_t mipsNN_cp0_config7_read(void); 161 void mipsNN_cp0_config7_write(uint32_t); 162 uint64_t mips64_cp0_config7_read(void); 163 void mips64_cp0_config7_write(uint32_t); 164 165 uintptr_t mipsNN_cp0_watchlo_read(u_int); 166 void mipsNN_cp0_watchlo_write(u_int, uintptr_t); 167 uint32_t mipsNN_cp0_watchhi_read(u_int); 168 void mipsNN_cp0_watchhi_write(u_int, uint32_t); 169 170 #if (MIPS32R2 + MIPS64R2 + MIPS64R2_RMIXL) > 0 171 void mipsNN_cp0_hwrena_write(uint32_t); 172 void mipsNN_cp0_userlocal_write(void *); 173 #endif 174 #endif 175 176 uint32_t mips3_cp0_count_read(void); 177 void mips3_cp0_count_write(uint32_t); 178 179 uint32_t mips3_cp0_random_read(void); 180 181 uint32_t mips3_cp0_wired_read(void); 182 void mips3_cp0_wired_write(uint32_t); 183 void mips3_cp0_pg_mask_write(uint32_t); 184 185 #if defined(__GNUC__) && !defined(__mips_o32) 186 static inline uint64_t 187 mips3_ld(const volatile uint64_t *va) 188 { 189 uint64_t rv; 190 #if defined(__mips_o32) 191 uint32_t sr; 192 193 sr = mips_cp0_status_read(); 194 mips_cp0_status_write(sr & ~MIPS_SR_INT_IE); 195 196 __asm volatile( 197 ".set push \n\t" 198 ".set mips3 \n\t" 199 ".set noreorder \n\t" 200 ".set noat \n\t" 201 "ld %M0,0(%1) \n\t" 202 "dsll32 %L0,%M0,0 \n\t" 203 "dsra32 %M0,%M0,0 \n\t" /* high word */ 204 "dsra32 %L0,%L0,0 \n\t" /* low word */ 205 "ld %0,0(%1) \n\t" 206 ".set pop" 207 : "=d"(rv) 208 : "r"(va)); 209 210 mips_cp0_status_write(sr); 211 #elif defined(_LP64) 212 rv = *va; 213 #else 214 __asm volatile("ld %0,0(%1)" : "=d"(rv) : "r"(va)); 215 #endif 216 217 return rv; 218 } 219 static inline void 220 mips3_sd(volatile uint64_t *va, uint64_t v) 221 { 222 #if defined(__mips_o32) 223 uint32_t sr; 224 225 sr = mips_cp0_status_read(); 226 mips_cp0_status_write(sr & ~MIPS_SR_INT_IE); 227 228 __asm volatile( 229 ".set push \n\t" 230 ".set mips3 \n\t" 231 ".set noreorder \n\t" 232 ".set noat \n\t" 233 "dsll32 %M0,%M0,0 \n\t" 234 "dsll32 %L0,%L0,0 \n\t" 235 "dsrl32 %L0,%L0,0 \n\t" 236 "or %0,%L0,%M0 \n\t" 237 "sd %0,0(%1) \n\t" 238 ".set pop" 239 : "=d"(v) : "0"(v), "r"(va)); 240 241 mips_cp0_status_write(sr); 242 #elif defined(_LP64) 243 *va = v; 244 #else 245 __asm volatile("sd %0,0(%1)" :: "r"(v), "r"(va)); 246 #endif 247 } 248 #else 249 uint64_t mips3_ld(volatile uint64_t *va); 250 void mips3_sd(volatile uint64_t *, uint64_t); 251 #endif /* __GNUC__ */ 252 #endif /* (MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2 + MIPS64_RMIXL + MIPS64R2_RMIXL) > 0 */ 253 254 #if (MIPS3 + MIPS4 + MIPS64 + MIPS64R2 + MIPS64_RMIXL + MIPS64R2_RMIXL) > 0 255 static __inline uint32_t mips3_lw_a64(uint64_t addr) __unused; 256 static __inline void mips3_sw_a64(uint64_t addr, uint32_t val) __unused; 257 258 static __inline uint32_t 259 mips3_lw_a64(uint64_t addr) 260 { 261 uint32_t rv; 262 #if defined(__mips_o32) 263 uint32_t sr; 264 265 sr = mips_cp0_status_read(); 266 mips_cp0_status_write((sr & ~MIPS_SR_INT_IE) | MIPS3_SR_KX); 267 268 __asm volatile ( 269 ".set push \n\t" 270 ".set mips3 \n\t" 271 ".set noreorder \n\t" 272 ".set noat \n\t" 273 "dsll32 %M1,%M1,0 \n\t" 274 "dsll32 %L1,%L1,0 \n\t" 275 "dsrl32 %L1,%L1,0 \n\t" 276 "or %1,%M1,%L1 \n\t" 277 "lw %0, 0(%1) \n\t" 278 ".set pop" 279 : "=r"(rv), "=d"(addr) 280 : "1"(addr) 281 ); 282 283 mips_cp0_status_write(sr); 284 #elif defined(__mips_n32) 285 uint32_t sr = mips_cp0_status_read(); 286 mips_cp0_status_write((sr & ~MIPS_SR_INT_IE) | MIPS3_SR_KX); 287 __asm volatile("lw %0, 0(%1)" : "=r"(rv) : "d"(addr)); 288 mips_cp0_status_write(sr); 289 #elif defined(_LP64) 290 rv = *(const uint32_t *)addr; 291 #else 292 #error unknown ABI 293 #endif 294 return (rv); 295 } 296 297 static __inline void 298 mips3_sw_a64(uint64_t addr, uint32_t val) 299 { 300 #if defined(__mips_o32) 301 uint32_t sr; 302 303 sr = mips_cp0_status_read(); 304 mips_cp0_status_write((sr & ~MIPS_SR_INT_IE) | MIPS3_SR_KX); 305 306 __asm volatile ( 307 ".set push \n\t" 308 ".set mips3 \n\t" 309 ".set noreorder \n\t" 310 ".set noat \n\t" 311 "dsll32 %M0,%M0,0 \n\t" 312 "dsll32 %L0,%L0,0 \n\t" 313 "dsrl32 %L0,%L0,0 \n\t" 314 "or %0,%M0,%L0 \n\t" 315 "sw %1, 0(%0) \n\t" 316 ".set pop" 317 : "=d"(addr): "r"(val), "0"(addr) 318 ); 319 320 mips_cp0_status_write(sr); 321 #elif defined(__mips_n32) 322 uint32_t sr = mips_cp0_status_read(); 323 mips_cp0_status_write((sr & ~MIPS_SR_INT_IE) | MIPS3_SR_KX); 324 __asm volatile("sw %1, 0(%0)" :: "d"(addr), "r"(val)); 325 mips_cp0_status_write(sr); 326 #elif defined(_LP64) 327 *(uint32_t *)addr = val; 328 #else 329 #error unknown ABI 330 #endif 331 } 332 #endif /* (MIPS3 + MIPS4 + MIPS64 + MIPS64R2 + MIPS64_RMIXL + MIPS64R2_RMIXL) > 0 */ 333 334 /* 335 * A vector with an entry for each mips-ISA-level dependent 336 * locore function, and macros which jump through it. 337 */ 338 typedef struct { 339 void (*ljv_cpu_switch_resume)(struct lwp *); 340 intptr_t ljv_lwp_trampoline; 341 intptr_t ljv_setfunc_trampoline; 342 void (*ljv_wbflush)(void); 343 void (*ljv_tlb_set_asid)(uint32_t pid); 344 void (*ljv_tlb_invalidate_asids)(uint32_t, uint32_t); 345 void (*ljv_tlb_invalidate_addr)(vaddr_t); 346 void (*ljv_tlb_invalidate_globals)(void); 347 void (*ljv_tlb_invalidate_all)(void); 348 u_int (*ljv_tlb_record_asids)(u_long *, uint32_t); 349 int (*ljv_tlb_update)(vaddr_t, uint32_t); 350 void (*ljv_tlb_enter)(size_t, vaddr_t, uint32_t); 351 void (*ljv_tlb_read_indexed)(size_t, struct tlbmask *); 352 void (*ljv_tlb_write_indexed)(size_t, const struct tlbmask *); 353 lwp_t * (*ljv_cpu_switchto)(lwp_t *, lwp_t *, bool); 354 } mips_locore_jumpvec_t; 355 356 typedef struct { 357 u_int (*lav_atomic_cas_uint)(volatile u_int *, u_int, u_int); 358 u_long (*lav_atomic_cas_ulong)(volatile u_long *, u_long, u_long); 359 int (*lav_ucas_uint)(volatile u_int *, u_int, u_int, u_int *); 360 int (*lav_ucas_ulong)(volatile u_long *, u_long, u_long, u_long *); 361 void (*lav_mutex_enter)(kmutex_t *); 362 void (*lav_mutex_exit)(kmutex_t *); 363 void (*lav_mutex_spin_enter)(kmutex_t *); 364 void (*lav_mutex_spin_exit)(kmutex_t *); 365 } mips_locore_atomicvec_t; 366 367 void mips_set_wbflush(void (*)(void)); 368 void mips_wait_idle(void); 369 370 void stacktrace(void); 371 void logstacktrace(void); 372 373 struct cpu_info; 374 struct splsw; 375 376 struct locoresw { 377 void (*lsw_wbflush)(void); 378 void (*lsw_cpu_idle)(void); 379 int (*lsw_send_ipi)(struct cpu_info *, int); 380 void (*lsw_cpu_offline_md)(void); 381 void (*lsw_cpu_init)(struct cpu_info *); 382 void (*lsw_cpu_run)(struct cpu_info *); 383 int (*lsw_bus_error)(unsigned int); 384 }; 385 386 struct mips_vmfreelist { 387 paddr_t fl_start; 388 paddr_t fl_end; 389 int fl_freelist; 390 }; 391 392 /* 393 * The "active" locore-function vector, and 394 */ 395 extern const mips_locore_atomicvec_t mips_llsc_locore_atomicvec; 396 extern const mips_locore_atomicvec_t mips_ras_locore_atomicvec; 397 398 extern mips_locore_atomicvec_t mips_locore_atomicvec; 399 extern mips_locore_jumpvec_t mips_locore_jumpvec; 400 extern struct locoresw mips_locoresw; 401 402 struct splsw; 403 struct mips_vmfreelist; 404 struct phys_ram_seg; 405 406 void mips_vector_init(const struct splsw *, bool); 407 void mips_init_msgbuf(void); 408 void mips_init_lwp0_uarea(void); 409 void mips_page_physload(vaddr_t, vaddr_t, 410 const struct phys_ram_seg *, size_t, 411 const struct mips_vmfreelist *, size_t); 412 413 414 /* 415 * CPU identification, from PRID register. 416 */ 417 #define MIPS_PRID_REV(x) (((x) >> 0) & 0x00ff) 418 #define MIPS_PRID_IMPL(x) (((x) >> 8) & 0x00ff) 419 420 /* pre-MIPS32/64 */ 421 #define MIPS_PRID_RSVD(x) (((x) >> 16) & 0xffff) 422 #define MIPS_PRID_REV_MIN(x) ((MIPS_PRID_REV(x) >> 0) & 0x0f) 423 #define MIPS_PRID_REV_MAJ(x) ((MIPS_PRID_REV(x) >> 4) & 0x0f) 424 425 /* MIPS32/64 */ 426 #define MIPS_PRID_CID(x) (((x) >> 16) & 0x00ff) /* Company ID */ 427 #define MIPS_PRID_CID_PREHISTORIC 0x00 /* Not MIPS32/64 */ 428 #define MIPS_PRID_CID_MTI 0x01 /* MIPS Technologies, Inc. */ 429 #define MIPS_PRID_CID_BROADCOM 0x02 /* Broadcom */ 430 #define MIPS_PRID_CID_ALCHEMY 0x03 /* Alchemy Semiconductor */ 431 #define MIPS_PRID_CID_SIBYTE 0x04 /* SiByte */ 432 #define MIPS_PRID_CID_SANDCRAFT 0x05 /* SandCraft */ 433 #define MIPS_PRID_CID_PHILIPS 0x06 /* Philips */ 434 #define MIPS_PRID_CID_TOSHIBA 0x07 /* Toshiba */ 435 #define MIPS_PRID_CID_LSI 0x08 /* LSI */ 436 /* 0x09 unannounced */ 437 /* 0x0a unannounced */ 438 #define MIPS_PRID_CID_LEXRA 0x0b /* Lexra */ 439 #define MIPS_PRID_CID_RMI 0x0c /* RMI / NetLogic */ 440 #define MIPS_PRID_COPTS(x) (((x) >> 24) & 0x00ff) /* Company Options */ 441 442 #ifdef _KERNEL 443 /* 444 * Global variables used to communicate CPU type, and parameters 445 * such as cache size, from locore to higher-level code (e.g., pmap). 446 */ 447 void mips_pagecopy(void *dst, void *src); 448 void mips_pagezero(void *dst); 449 450 #ifdef __HAVE_MIPS_MACHDEP_CACHE_CONFIG 451 void mips_machdep_cache_config(void); 452 #endif 453 454 /* 455 * trapframe argument passed to trap() 456 */ 457 458 #if 0 459 #define TF_AST 0 /* really zero */ 460 #define TF_V0 _R_V0 461 #define TF_V1 _R_V1 462 #define TF_A0 _R_A0 463 #define TF_A1 _R_A1 464 #define TF_A2 _R_A2 465 #define TF_A3 _R_A3 466 #define TF_T0 _R_T0 467 #define TF_T1 _R_T1 468 #define TF_T2 _R_T2 469 #define TF_T3 _R_T3 470 471 #if defined(__mips_n32) || defined(__mips_n64) 472 #define TF_A4 _R_A4 473 #define TF_A5 _R_A5 474 #define TF_A6 _R_A6 475 #define TF_A7 _R_A7 476 #else 477 #define TF_T4 _R_T4 478 #define TF_T5 _R_T5 479 #define TF_T6 _R_T6 480 #define TF_T7 _R_T7 481 #endif /* __mips_n32 || __mips_n64 */ 482 483 #define TF_TA0 _R_TA0 484 #define TF_TA1 _R_TA1 485 #define TF_TA2 _R_TA2 486 #define TF_TA3 _R_TA3 487 488 #define TF_T8 _R_T8 489 #define TF_T9 _R_T9 490 491 #define TF_RA _R_RA 492 #define TF_SR _R_SR 493 #define TF_MULLO _R_MULLO 494 #define TF_MULHI _R_MULLO 495 #define TF_EPC _R_PC /* may be changed by trap() call */ 496 497 #define TF_NREGS (sizeof(struct reg) / sizeof(mips_reg_t)) 498 #endif 499 500 struct trapframe { 501 struct reg tf_registers; 502 #define tf_regs tf_registers.r_regs 503 uint32_t tf_ppl; /* previous priority level */ 504 mips_reg_t tf_pad; /* for 8 byte aligned */ 505 }; 506 507 CTASSERT(sizeof(struct trapframe) % (4*sizeof(mips_reg_t)) == 0); 508 509 /* 510 * Stack frame for kernel traps. four args passed in registers. 511 * A trapframe is pointed to by the 5th arg, and a dummy sixth argument 512 * is used to avoid alignment problems 513 */ 514 515 struct kernframe { 516 #if defined(__mips_o32) || defined(__mips_o64) 517 register_t cf_args[4 + 1]; 518 #if defined(__mips_o32) 519 register_t cf_pad; /* (for 8 byte alignment) */ 520 #endif 521 #endif 522 #if defined(__mips_n32) || defined(__mips_n64) 523 register_t cf_pad[2]; /* for 16 byte alignment */ 524 #endif 525 register_t cf_sp; 526 register_t cf_ra; 527 struct trapframe cf_frame; 528 }; 529 530 CTASSERT(sizeof(struct kernframe) % (2*sizeof(mips_reg_t)) == 0); 531 532 /* 533 * PRocessor IDentity TABle 534 */ 535 536 struct pridtab { 537 int cpu_cid; 538 int cpu_pid; 539 int cpu_rev; /* -1 == wildcard */ 540 int cpu_copts; /* -1 == wildcard */ 541 int cpu_isa; /* -1 == probed (mips32/mips64) */ 542 int cpu_ntlb; /* -1 == unknown, 0 == probed */ 543 int cpu_flags; 544 u_int cpu_cp0flags; /* presence of some cp0 regs */ 545 u_int cpu_cidflags; /* company-specific flags */ 546 const char *cpu_name; 547 }; 548 549 /* 550 * bitfield defines for cpu_cp0flags 551 */ 552 #define MIPS_CP0FL_USE __BIT(0) /* use these flags */ 553 #define MIPS_CP0FL_ECC __BIT(1) 554 #define MIPS_CP0FL_CACHE_ERR __BIT(2) 555 #define MIPS_CP0FL_EIRR __BIT(3) 556 #define MIPS_CP0FL_EIMR __BIT(4) 557 #define MIPS_CP0FL_EBASE __BIT(5) 558 #define MIPS_CP0FL_CONFIG __BIT(6) 559 #define MIPS_CP0FL_CONFIG1 __BIT(7) 560 #define MIPS_CP0FL_CONFIG2 __BIT(8) 561 #define MIPS_CP0FL_CONFIG3 __BIT(9) 562 #define MIPS_CP0FL_CONFIG4 __BIT(10) 563 #define MIPS_CP0FL_CONFIG5 __BIT(11) 564 #define MIPS_CP0FL_CONFIG6 __BIT(12) 565 #define MIPS_CP0FL_CONFIG7 __BIT(13) 566 #define MIPS_CP0FL_USERLOCAL __BIT(14) 567 #define MIPS_CP0FL_HWRENA __BIT(15) 568 569 /* 570 * cpu_cidflags defines, by company 571 */ 572 /* 573 * RMI company-specific cpu_cidflags 574 */ 575 #define MIPS_CIDFL_RMI_TYPE __BITS(2,0) 576 # define CIDFL_RMI_TYPE_XLR 0 577 # define CIDFL_RMI_TYPE_XLS 1 578 # define CIDFL_RMI_TYPE_XLP 2 579 #define MIPS_CIDFL_RMI_THREADS_MASK __BITS(6,3) 580 #define MIPS_CIDFL_RMI_CORES_MASK __BITS(10,7) 581 # define LOG2_1 0 582 # define LOG2_2 1 583 # define LOG2_4 2 584 # define LOG2_8 3 585 # define MIPS_CIDFL_RMI_CPUS(ncores, nthreads) \ 586 (__SHIFTIN(LOG2_ ## ncores, MIPS_CIDFL_RMI_CORES_MASK) \ 587 |__SHIFTIN(LOG2_ ## nthreads, MIPS_CIDFL_RMI_THREADS_MASK)) 588 # define MIPS_CIDFL_RMI_NTHREADS(cidfl) \ 589 (1 << __SHIFTOUT((cidfl), MIPS_CIDFL_RMI_THREADS_MASK)) 590 # define MIPS_CIDFL_RMI_NCORES(cidfl) \ 591 (1 << __SHIFTOUT((cidfl), MIPS_CIDFL_RMI_CORES_MASK)) 592 #define MIPS_CIDFL_RMI_L2SZ_MASK __BITS(14,11) 593 # define RMI_L2SZ_256KB 0 594 # define RMI_L2SZ_512KB 1 595 # define RMI_L2SZ_1MB 2 596 # define RMI_L2SZ_2MB 3 597 # define RMI_L2SZ_4MB 4 598 # define MIPS_CIDFL_RMI_L2(l2sz) \ 599 __SHIFTIN(RMI_L2SZ_ ## l2sz, MIPS_CIDFL_RMI_L2SZ_MASK) 600 # define MIPS_CIDFL_RMI_L2SZ(cidfl) \ 601 ((256*1024) << __SHIFTOUT((cidfl), MIPS_CIDFL_RMI_L2SZ_MASK)) 602 #define MIPS_CIDFL_RMI_L3SZ_MASK __BITS(18,15) 603 # define RMI_L3SZ_256KB 0 604 # define RMI_L3SZ_512KB 1 605 # define RMI_L3SZ_1MB 2 606 # define RMI_L3SZ_2MB 3 607 # define RMI_L3SZ_4MB 4 608 # define MIPS_CIDFL_RMI_L3(l3sz) \ 609 __SHIFTIN(RMI_L3SZ_ ## l3sz, MIPS_CIDFL_RMI_L3SZ_MASK) 610 # define MIPS_CIDFL_RMI_L3SZ(cidfl) \ 611 ((256*1024) << __SHIFTOUT((cidfl), MIPS_CIDFL_RMI_L3SZ_MASK)) 612 613 #endif /* _KERNEL */ 614 #endif /* _MIPS_LOCORE_H */ 615
Indexes created Sun Oct 19 19:09:49 GMT 2025